1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_CPU_H 19 #define HEXAGON_CPU_H 20 21 #include "fpu/softfloat-types.h" 22 23 #include "exec/cpu-defs.h" 24 #include "hex_regs.h" 25 #include "mmvec/mmvec.h" 26 #include "qom/object.h" 27 #include "hw/core/cpu.h" 28 #include "hw/registerfields.h" 29 30 #define NUM_PREGS 4 31 #define TOTAL_PER_THREAD_REGS 64 32 33 #define SLOTS_MAX 4 34 #define STORES_MAX 2 35 #define REG_WRITES_MAX 32 36 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ 37 #define VSTORES_MAX 2 38 39 #define TYPE_HEXAGON_CPU "hexagon-cpu" 40 41 #define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU 42 #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU 44 45 #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") 46 #define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") 47 #define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") 48 #define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") 49 #define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") 50 51 void hexagon_cpu_list(void); 52 #define cpu_list hexagon_cpu_list 53 54 #define MMU_USER_IDX 0 55 56 typedef struct { 57 target_ulong va; 58 uint8_t width; 59 uint32_t data32; 60 uint64_t data64; 61 } MemLog; 62 63 typedef struct { 64 target_ulong va; 65 int size; 66 DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16); 67 MMVector data QEMU_ALIGNED(16); 68 } VStoreLog; 69 70 #define EXEC_STATUS_OK 0x0000 71 #define EXEC_STATUS_STOP 0x0002 72 #define EXEC_STATUS_REPLAY 0x0010 73 #define EXEC_STATUS_LOCKED 0x0020 74 #define EXEC_STATUS_EXCEPTION 0x0100 75 76 77 #define EXCEPTION_DETECTED (env->status & EXEC_STATUS_EXCEPTION) 78 #define REPLAY_DETECTED (env->status & EXEC_STATUS_REPLAY) 79 #define CLEAR_EXCEPTION (env->status &= (~EXEC_STATUS_EXCEPTION)) 80 #define SET_EXCEPTION (env->status |= EXEC_STATUS_EXCEPTION) 81 82 /* Maximum number of vector temps in a packet */ 83 #define VECTOR_TEMPS_MAX 4 84 85 typedef struct CPUArchState { 86 target_ulong gpr[TOTAL_PER_THREAD_REGS]; 87 target_ulong pred[NUM_PREGS]; 88 89 /* For comparing with LLDB on target - see adjust_stack_ptrs function */ 90 target_ulong last_pc_dumped; 91 target_ulong stack_start; 92 93 uint8_t slot_cancelled; 94 target_ulong new_value_usr; 95 96 /* 97 * Only used when HEX_DEBUG is on, but unconditionally included 98 * to reduce recompile time when turning HEX_DEBUG on/off. 99 */ 100 target_ulong reg_written[TOTAL_PER_THREAD_REGS]; 101 102 MemLog mem_log_stores[STORES_MAX]; 103 104 float_status fp_status; 105 106 target_ulong llsc_addr; 107 target_ulong llsc_val; 108 uint64_t llsc_val_i64; 109 110 MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16); 111 MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 112 MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 113 114 MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); 115 MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16); 116 117 /* Temporaries used within instructions */ 118 MMVectorPair VuuV QEMU_ALIGNED(16); 119 MMVectorPair VvvV QEMU_ALIGNED(16); 120 MMVectorPair VxxV QEMU_ALIGNED(16); 121 MMVector vtmp QEMU_ALIGNED(16); 122 MMQReg qtmp QEMU_ALIGNED(16); 123 124 VStoreLog vstore[VSTORES_MAX]; 125 target_ulong vstore_pending[VSTORES_MAX]; 126 bool vtcm_pending; 127 VTCMStoreLog vtcm_log; 128 } CPUHexagonState; 129 130 OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) 131 132 typedef struct HexagonCPUClass { 133 /*< private >*/ 134 CPUClass parent_class; 135 /*< public >*/ 136 DeviceRealize parent_realize; 137 ResettablePhases parent_phases; 138 } HexagonCPUClass; 139 140 struct ArchCPU { 141 /*< private >*/ 142 CPUState parent_obj; 143 /*< public >*/ 144 CPUNegativeOffsetState neg; 145 CPUHexagonState env; 146 147 bool lldb_compat; 148 target_ulong lldb_stack_adjust; 149 bool short_circuit; 150 }; 151 152 #include "cpu_bits.h" 153 154 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) 155 156 static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc, 157 target_ulong *cs_base, uint32_t *flags) 158 { 159 uint32_t hex_flags = 0; 160 *pc = env->gpr[HEX_REG_PC]; 161 *cs_base = 0; 162 if (*pc == env->gpr[HEX_REG_SA0]) { 163 hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); 164 } 165 *flags = hex_flags; 166 } 167 168 static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) 169 { 170 #ifdef CONFIG_USER_ONLY 171 return MMU_USER_IDX; 172 #else 173 #error System mode not supported on Hexagon yet 174 #endif 175 } 176 177 typedef HexagonCPU ArchCPU; 178 179 void hexagon_translate_init(void); 180 181 #include "exec/cpu-all.h" 182 183 #endif /* HEXAGON_CPU_H */ 184