1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/qemu-print.h" 20 #include "cpu.h" 21 #include "internal.h" 22 #include "exec/exec-all.h" 23 #include "qapi/error.h" 24 #include "hw/qdev-properties.h" 25 #include "fpu/softfloat-helpers.h" 26 #include "tcg/tcg.h" 27 #include "exec/gdbstub.h" 28 29 static void hexagon_v67_cpu_init(Object *obj) { } 30 static void hexagon_v68_cpu_init(Object *obj) { } 31 static void hexagon_v69_cpu_init(Object *obj) { } 32 static void hexagon_v71_cpu_init(Object *obj) { } 33 static void hexagon_v73_cpu_init(Object *obj) { } 34 35 static void hexagon_cpu_list_entry(gpointer data, gpointer user_data) 36 { 37 ObjectClass *oc = data; 38 char *name = g_strdup(object_class_get_name(oc)); 39 if (g_str_has_suffix(name, HEXAGON_CPU_TYPE_SUFFIX)) { 40 name[strlen(name) - strlen(HEXAGON_CPU_TYPE_SUFFIX)] = '\0'; 41 } 42 qemu_printf(" %s\n", name); 43 g_free(name); 44 } 45 46 void hexagon_cpu_list(void) 47 { 48 GSList *list; 49 list = object_class_get_list_sorted(TYPE_HEXAGON_CPU, false); 50 qemu_printf("Available CPUs:\n"); 51 g_slist_foreach(list, hexagon_cpu_list_entry, NULL); 52 g_slist_free(list); 53 } 54 55 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) 56 { 57 ObjectClass *oc; 58 char *typename; 59 char **cpuname; 60 61 cpuname = g_strsplit(cpu_model, ",", 1); 62 typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]); 63 oc = object_class_by_name(typename); 64 g_strfreev(cpuname); 65 g_free(typename); 66 67 return oc; 68 } 69 70 static Property hexagon_lldb_compat_property = 71 DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false); 72 static Property hexagon_lldb_stack_adjust_property = 73 DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 74 0, qdev_prop_uint32, target_ulong); 75 static Property hexagon_short_circuit_property = 76 DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true); 77 78 const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = { 79 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 80 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 81 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 82 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 83 "sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1", 84 "usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15", 85 "c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "hvx_cnt", "c23", 86 "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31", 87 }; 88 89 /* 90 * One of the main debugging techniques is to use "-d cpu" and compare against 91 * LLDB output when single stepping. However, the target and qemu put the 92 * stacks at different locations. This is used to compensate so the diff is 93 * cleaner. 94 */ 95 static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr) 96 { 97 HexagonCPU *cpu = env_archcpu(env); 98 target_ulong stack_adjust = cpu->lldb_stack_adjust; 99 target_ulong stack_start = env->stack_start; 100 target_ulong stack_size = 0x10000; 101 102 if (stack_adjust == 0) { 103 return addr; 104 } 105 106 if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) { 107 return addr - stack_adjust; 108 } 109 return addr; 110 } 111 112 /* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */ 113 static target_ulong read_p3_0(CPUHexagonState *env) 114 { 115 int32_t control_reg = 0; 116 int i; 117 for (i = NUM_PREGS - 1; i >= 0; i--) { 118 control_reg <<= 8; 119 control_reg |= env->pred[i] & 0xff; 120 } 121 return control_reg; 122 } 123 124 static void print_reg(FILE *f, CPUHexagonState *env, int regnum) 125 { 126 target_ulong value; 127 128 if (regnum == HEX_REG_P3_0_ALIASED) { 129 value = read_p3_0(env); 130 } else { 131 value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum]) 132 : env->gpr[regnum]; 133 } 134 135 qemu_fprintf(f, " %s = 0x" TARGET_FMT_lx "\n", 136 hexagon_regnames[regnum], value); 137 } 138 139 static void print_vreg(FILE *f, CPUHexagonState *env, int regnum, 140 bool skip_if_zero) 141 { 142 if (skip_if_zero) { 143 bool nonzero_found = false; 144 for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) { 145 if (env->VRegs[regnum].ub[i] != 0) { 146 nonzero_found = true; 147 break; 148 } 149 } 150 if (!nonzero_found) { 151 return; 152 } 153 } 154 155 qemu_fprintf(f, " v%d = ( ", regnum); 156 qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]); 157 for (int i = MAX_VEC_SIZE_BYTES - 2; i >= 0; i--) { 158 qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]); 159 } 160 qemu_fprintf(f, " )\n"); 161 } 162 163 void hexagon_debug_vreg(CPUHexagonState *env, int regnum) 164 { 165 print_vreg(stdout, env, regnum, false); 166 } 167 168 static void print_qreg(FILE *f, CPUHexagonState *env, int regnum, 169 bool skip_if_zero) 170 { 171 if (skip_if_zero) { 172 bool nonzero_found = false; 173 for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { 174 if (env->QRegs[regnum].ub[i] != 0) { 175 nonzero_found = true; 176 break; 177 } 178 } 179 if (!nonzero_found) { 180 return; 181 } 182 } 183 184 qemu_fprintf(f, " q%d = ( ", regnum); 185 qemu_fprintf(f, "0x%02x", 186 env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]); 187 for (int i = MAX_VEC_SIZE_BYTES / 8 - 2; i >= 0; i--) { 188 qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]); 189 } 190 qemu_fprintf(f, " )\n"); 191 } 192 193 void hexagon_debug_qreg(CPUHexagonState *env, int regnum) 194 { 195 print_qreg(stdout, env, regnum, false); 196 } 197 198 static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags) 199 { 200 HexagonCPU *cpu = env_archcpu(env); 201 202 if (cpu->lldb_compat) { 203 /* 204 * When comparing with LLDB, it doesn't step through single-cycle 205 * hardware loops the same way. So, we just skip them here 206 */ 207 if (env->gpr[HEX_REG_PC] == env->last_pc_dumped) { 208 return; 209 } 210 env->last_pc_dumped = env->gpr[HEX_REG_PC]; 211 } 212 213 qemu_fprintf(f, "General Purpose Registers = {\n"); 214 for (int i = 0; i < 32; i++) { 215 print_reg(f, env, i); 216 } 217 print_reg(f, env, HEX_REG_SA0); 218 print_reg(f, env, HEX_REG_LC0); 219 print_reg(f, env, HEX_REG_SA1); 220 print_reg(f, env, HEX_REG_LC1); 221 print_reg(f, env, HEX_REG_M0); 222 print_reg(f, env, HEX_REG_M1); 223 print_reg(f, env, HEX_REG_USR); 224 print_reg(f, env, HEX_REG_P3_0_ALIASED); 225 print_reg(f, env, HEX_REG_GP); 226 print_reg(f, env, HEX_REG_UGP); 227 print_reg(f, env, HEX_REG_PC); 228 #ifdef CONFIG_USER_ONLY 229 /* 230 * Not modelled in user mode, print junk to minimize the diff's 231 * with LLDB output 232 */ 233 qemu_fprintf(f, " cause = 0x000000db\n"); 234 qemu_fprintf(f, " badva = 0x00000000\n"); 235 qemu_fprintf(f, " cs0 = 0x00000000\n"); 236 qemu_fprintf(f, " cs1 = 0x00000000\n"); 237 #else 238 print_reg(f, env, HEX_REG_CAUSE); 239 print_reg(f, env, HEX_REG_BADVA); 240 print_reg(f, env, HEX_REG_CS0); 241 print_reg(f, env, HEX_REG_CS1); 242 #endif 243 qemu_fprintf(f, "}\n"); 244 245 if (flags & CPU_DUMP_FPU) { 246 qemu_fprintf(f, "Vector Registers = {\n"); 247 for (int i = 0; i < NUM_VREGS; i++) { 248 print_vreg(f, env, i, true); 249 } 250 for (int i = 0; i < NUM_QREGS; i++) { 251 print_qreg(f, env, i, true); 252 } 253 qemu_fprintf(f, "}\n"); 254 } 255 } 256 257 static void hexagon_dump_state(CPUState *cs, FILE *f, int flags) 258 { 259 HexagonCPU *cpu = HEXAGON_CPU(cs); 260 CPUHexagonState *env = &cpu->env; 261 262 hexagon_dump(env, f, flags); 263 } 264 265 void hexagon_debug(CPUHexagonState *env) 266 { 267 hexagon_dump(env, stdout, CPU_DUMP_FPU); 268 } 269 270 static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) 271 { 272 HexagonCPU *cpu = HEXAGON_CPU(cs); 273 CPUHexagonState *env = &cpu->env; 274 env->gpr[HEX_REG_PC] = value; 275 } 276 277 static vaddr hexagon_cpu_get_pc(CPUState *cs) 278 { 279 HexagonCPU *cpu = HEXAGON_CPU(cs); 280 CPUHexagonState *env = &cpu->env; 281 return env->gpr[HEX_REG_PC]; 282 } 283 284 static void hexagon_cpu_synchronize_from_tb(CPUState *cs, 285 const TranslationBlock *tb) 286 { 287 HexagonCPU *cpu = HEXAGON_CPU(cs); 288 CPUHexagonState *env = &cpu->env; 289 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 290 env->gpr[HEX_REG_PC] = tb->pc; 291 } 292 293 static bool hexagon_cpu_has_work(CPUState *cs) 294 { 295 return true; 296 } 297 298 static void hexagon_restore_state_to_opc(CPUState *cs, 299 const TranslationBlock *tb, 300 const uint64_t *data) 301 { 302 HexagonCPU *cpu = HEXAGON_CPU(cs); 303 CPUHexagonState *env = &cpu->env; 304 305 env->gpr[HEX_REG_PC] = data[0]; 306 } 307 308 static void hexagon_cpu_reset_hold(Object *obj) 309 { 310 CPUState *cs = CPU(obj); 311 HexagonCPU *cpu = HEXAGON_CPU(cs); 312 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu); 313 CPUHexagonState *env = &cpu->env; 314 315 if (mcc->parent_phases.hold) { 316 mcc->parent_phases.hold(obj); 317 } 318 319 set_default_nan_mode(1, &env->fp_status); 320 set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); 321 } 322 323 static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) 324 { 325 info->print_insn = print_insn_hexagon; 326 } 327 328 static void hexagon_cpu_realize(DeviceState *dev, Error **errp) 329 { 330 CPUState *cs = CPU(dev); 331 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev); 332 Error *local_err = NULL; 333 334 cpu_exec_realizefn(cs, &local_err); 335 if (local_err != NULL) { 336 error_propagate(errp, local_err); 337 return; 338 } 339 340 gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register, 341 hexagon_hvx_gdb_write_register, 342 NUM_VREGS + NUM_QREGS, 343 "hexagon-hvx.xml", 0); 344 345 qemu_init_vcpu(cs); 346 cpu_reset(cs); 347 348 mcc->parent_realize(dev, errp); 349 } 350 351 static void hexagon_cpu_init(Object *obj) 352 { 353 qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property); 354 qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property); 355 qdev_property_add_static(DEVICE(obj), &hexagon_short_circuit_property); 356 } 357 358 #include "hw/core/tcg-cpu-ops.h" 359 360 static const struct TCGCPUOps hexagon_tcg_ops = { 361 .initialize = hexagon_translate_init, 362 .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, 363 .restore_state_to_opc = hexagon_restore_state_to_opc, 364 }; 365 366 static void hexagon_cpu_class_init(ObjectClass *c, void *data) 367 { 368 HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c); 369 CPUClass *cc = CPU_CLASS(c); 370 DeviceClass *dc = DEVICE_CLASS(c); 371 ResettableClass *rc = RESETTABLE_CLASS(c); 372 373 device_class_set_parent_realize(dc, hexagon_cpu_realize, 374 &mcc->parent_realize); 375 376 resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL, 377 &mcc->parent_phases); 378 379 cc->class_by_name = hexagon_cpu_class_by_name; 380 cc->has_work = hexagon_cpu_has_work; 381 cc->dump_state = hexagon_dump_state; 382 cc->set_pc = hexagon_cpu_set_pc; 383 cc->get_pc = hexagon_cpu_get_pc; 384 cc->gdb_read_register = hexagon_gdb_read_register; 385 cc->gdb_write_register = hexagon_gdb_write_register; 386 cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS; 387 cc->gdb_stop_before_watchpoint = true; 388 cc->gdb_core_xml_file = "hexagon-core.xml"; 389 cc->disas_set_info = hexagon_cpu_disas_set_info; 390 cc->tcg_ops = &hexagon_tcg_ops; 391 } 392 393 #define DEFINE_CPU(type_name, initfn) \ 394 { \ 395 .name = type_name, \ 396 .parent = TYPE_HEXAGON_CPU, \ 397 .instance_init = initfn \ 398 } 399 400 static const TypeInfo hexagon_cpu_type_infos[] = { 401 { 402 .name = TYPE_HEXAGON_CPU, 403 .parent = TYPE_CPU, 404 .instance_size = sizeof(HexagonCPU), 405 .instance_align = __alignof(HexagonCPU), 406 .instance_init = hexagon_cpu_init, 407 .abstract = true, 408 .class_size = sizeof(HexagonCPUClass), 409 .class_init = hexagon_cpu_class_init, 410 }, 411 DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init), 412 DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init), 413 DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init), 414 DEFINE_CPU(TYPE_HEXAGON_CPU_V71, hexagon_v71_cpu_init), 415 DEFINE_CPU(TYPE_HEXAGON_CPU_V73, hexagon_v73_cpu_init), 416 }; 417 418 DEFINE_TYPES(hexagon_cpu_type_infos) 419