1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/qemu-print.h" 20 #include "cpu.h" 21 #include "internal.h" 22 #include "exec/exec-all.h" 23 #include "qapi/error.h" 24 #include "hw/qdev-properties.h" 25 #include "fpu/softfloat-helpers.h" 26 #include "tcg/tcg.h" 27 #include "exec/gdbstub.h" 28 29 static void hexagon_v66_cpu_init(Object *obj) { } 30 static void hexagon_v67_cpu_init(Object *obj) { } 31 static void hexagon_v68_cpu_init(Object *obj) { } 32 static void hexagon_v69_cpu_init(Object *obj) { } 33 static void hexagon_v71_cpu_init(Object *obj) { } 34 static void hexagon_v73_cpu_init(Object *obj) { } 35 36 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) 37 { 38 ObjectClass *oc; 39 char *typename; 40 char **cpuname; 41 42 cpuname = g_strsplit(cpu_model, ",", 1); 43 typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]); 44 oc = object_class_by_name(typename); 45 g_strfreev(cpuname); 46 g_free(typename); 47 48 return oc; 49 } 50 51 static Property hexagon_cpu_properties[] = { 52 DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false), 53 DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 0, 54 qdev_prop_uint32, target_ulong), 55 DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true), 56 DEFINE_PROP_END_OF_LIST() 57 }; 58 59 const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = { 60 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 61 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 62 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 63 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 64 "sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1", 65 "usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15", 66 "c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "hvx_cnt", "c23", 67 "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31", 68 }; 69 70 /* 71 * One of the main debugging techniques is to use "-d cpu" and compare against 72 * LLDB output when single stepping. However, the target and qemu put the 73 * stacks at different locations. This is used to compensate so the diff is 74 * cleaner. 75 */ 76 static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr) 77 { 78 HexagonCPU *cpu = env_archcpu(env); 79 target_ulong stack_adjust = cpu->lldb_stack_adjust; 80 target_ulong stack_start = env->stack_start; 81 target_ulong stack_size = 0x10000; 82 83 if (stack_adjust == 0) { 84 return addr; 85 } 86 87 if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) { 88 return addr - stack_adjust; 89 } 90 return addr; 91 } 92 93 /* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */ 94 static target_ulong read_p3_0(CPUHexagonState *env) 95 { 96 int32_t control_reg = 0; 97 int i; 98 for (i = NUM_PREGS - 1; i >= 0; i--) { 99 control_reg <<= 8; 100 control_reg |= env->pred[i] & 0xff; 101 } 102 return control_reg; 103 } 104 105 static void print_reg(FILE *f, CPUHexagonState *env, int regnum) 106 { 107 target_ulong value; 108 109 if (regnum == HEX_REG_P3_0_ALIASED) { 110 value = read_p3_0(env); 111 } else { 112 value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum]) 113 : env->gpr[regnum]; 114 } 115 116 qemu_fprintf(f, " %s = 0x" TARGET_FMT_lx "\n", 117 hexagon_regnames[regnum], value); 118 } 119 120 static void print_vreg(FILE *f, CPUHexagonState *env, int regnum, 121 bool skip_if_zero) 122 { 123 if (skip_if_zero) { 124 bool nonzero_found = false; 125 for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) { 126 if (env->VRegs[regnum].ub[i] != 0) { 127 nonzero_found = true; 128 break; 129 } 130 } 131 if (!nonzero_found) { 132 return; 133 } 134 } 135 136 qemu_fprintf(f, " v%d = ( ", regnum); 137 qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]); 138 for (int i = MAX_VEC_SIZE_BYTES - 2; i >= 0; i--) { 139 qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]); 140 } 141 qemu_fprintf(f, " )\n"); 142 } 143 144 void hexagon_debug_vreg(CPUHexagonState *env, int regnum) 145 { 146 print_vreg(stdout, env, regnum, false); 147 } 148 149 static void print_qreg(FILE *f, CPUHexagonState *env, int regnum, 150 bool skip_if_zero) 151 { 152 if (skip_if_zero) { 153 bool nonzero_found = false; 154 for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { 155 if (env->QRegs[regnum].ub[i] != 0) { 156 nonzero_found = true; 157 break; 158 } 159 } 160 if (!nonzero_found) { 161 return; 162 } 163 } 164 165 qemu_fprintf(f, " q%d = ( ", regnum); 166 qemu_fprintf(f, "0x%02x", 167 env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]); 168 for (int i = MAX_VEC_SIZE_BYTES / 8 - 2; i >= 0; i--) { 169 qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]); 170 } 171 qemu_fprintf(f, " )\n"); 172 } 173 174 void hexagon_debug_qreg(CPUHexagonState *env, int regnum) 175 { 176 print_qreg(stdout, env, regnum, false); 177 } 178 179 static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags) 180 { 181 HexagonCPU *cpu = env_archcpu(env); 182 183 if (cpu->lldb_compat) { 184 /* 185 * When comparing with LLDB, it doesn't step through single-cycle 186 * hardware loops the same way. So, we just skip them here 187 */ 188 if (env->gpr[HEX_REG_PC] == env->last_pc_dumped) { 189 return; 190 } 191 env->last_pc_dumped = env->gpr[HEX_REG_PC]; 192 } 193 194 qemu_fprintf(f, "General Purpose Registers = {\n"); 195 for (int i = 0; i < 32; i++) { 196 print_reg(f, env, i); 197 } 198 print_reg(f, env, HEX_REG_SA0); 199 print_reg(f, env, HEX_REG_LC0); 200 print_reg(f, env, HEX_REG_SA1); 201 print_reg(f, env, HEX_REG_LC1); 202 print_reg(f, env, HEX_REG_M0); 203 print_reg(f, env, HEX_REG_M1); 204 print_reg(f, env, HEX_REG_USR); 205 print_reg(f, env, HEX_REG_P3_0_ALIASED); 206 print_reg(f, env, HEX_REG_GP); 207 print_reg(f, env, HEX_REG_UGP); 208 print_reg(f, env, HEX_REG_PC); 209 #ifdef CONFIG_USER_ONLY 210 /* 211 * Not modelled in user mode, print junk to minimize the diff's 212 * with LLDB output 213 */ 214 qemu_fprintf(f, " cause = 0x000000db\n"); 215 qemu_fprintf(f, " badva = 0x00000000\n"); 216 qemu_fprintf(f, " cs0 = 0x00000000\n"); 217 qemu_fprintf(f, " cs1 = 0x00000000\n"); 218 #else 219 print_reg(f, env, HEX_REG_CAUSE); 220 print_reg(f, env, HEX_REG_BADVA); 221 print_reg(f, env, HEX_REG_CS0); 222 print_reg(f, env, HEX_REG_CS1); 223 #endif 224 qemu_fprintf(f, "}\n"); 225 226 if (flags & CPU_DUMP_FPU) { 227 qemu_fprintf(f, "Vector Registers = {\n"); 228 for (int i = 0; i < NUM_VREGS; i++) { 229 print_vreg(f, env, i, true); 230 } 231 for (int i = 0; i < NUM_QREGS; i++) { 232 print_qreg(f, env, i, true); 233 } 234 qemu_fprintf(f, "}\n"); 235 } 236 } 237 238 static void hexagon_dump_state(CPUState *cs, FILE *f, int flags) 239 { 240 hexagon_dump(cpu_env(cs), f, flags); 241 } 242 243 void hexagon_debug(CPUHexagonState *env) 244 { 245 hexagon_dump(env, stdout, CPU_DUMP_FPU); 246 } 247 248 static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) 249 { 250 cpu_env(cs)->gpr[HEX_REG_PC] = value; 251 } 252 253 static vaddr hexagon_cpu_get_pc(CPUState *cs) 254 { 255 return cpu_env(cs)->gpr[HEX_REG_PC]; 256 } 257 258 static void hexagon_cpu_synchronize_from_tb(CPUState *cs, 259 const TranslationBlock *tb) 260 { 261 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 262 cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc; 263 } 264 265 static bool hexagon_cpu_has_work(CPUState *cs) 266 { 267 return true; 268 } 269 270 static void hexagon_restore_state_to_opc(CPUState *cs, 271 const TranslationBlock *tb, 272 const uint64_t *data) 273 { 274 cpu_env(cs)->gpr[HEX_REG_PC] = data[0]; 275 } 276 277 static void hexagon_cpu_reset_hold(Object *obj, ResetType type) 278 { 279 CPUState *cs = CPU(obj); 280 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj); 281 CPUHexagonState *env = cpu_env(cs); 282 283 if (mcc->parent_phases.hold) { 284 mcc->parent_phases.hold(obj, type); 285 } 286 287 set_default_nan_mode(1, &env->fp_status); 288 set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); 289 } 290 291 static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) 292 { 293 info->print_insn = print_insn_hexagon; 294 } 295 296 static void hexagon_cpu_realize(DeviceState *dev, Error **errp) 297 { 298 CPUState *cs = CPU(dev); 299 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev); 300 Error *local_err = NULL; 301 302 cpu_exec_realizefn(cs, &local_err); 303 if (local_err != NULL) { 304 error_propagate(errp, local_err); 305 return; 306 } 307 308 gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register, 309 hexagon_hvx_gdb_write_register, 310 gdb_find_static_feature("hexagon-hvx.xml"), 0); 311 312 qemu_init_vcpu(cs); 313 cpu_reset(cs); 314 315 mcc->parent_realize(dev, errp); 316 } 317 318 static void hexagon_cpu_init(Object *obj) 319 { 320 } 321 322 #include "hw/core/tcg-cpu-ops.h" 323 324 static const TCGCPUOps hexagon_tcg_ops = { 325 .initialize = hexagon_translate_init, 326 .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, 327 .restore_state_to_opc = hexagon_restore_state_to_opc, 328 }; 329 330 static void hexagon_cpu_class_init(ObjectClass *c, void *data) 331 { 332 HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c); 333 CPUClass *cc = CPU_CLASS(c); 334 DeviceClass *dc = DEVICE_CLASS(c); 335 ResettableClass *rc = RESETTABLE_CLASS(c); 336 337 device_class_set_parent_realize(dc, hexagon_cpu_realize, 338 &mcc->parent_realize); 339 340 device_class_set_props(dc, hexagon_cpu_properties); 341 resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL, 342 &mcc->parent_phases); 343 344 cc->class_by_name = hexagon_cpu_class_by_name; 345 cc->has_work = hexagon_cpu_has_work; 346 cc->dump_state = hexagon_dump_state; 347 cc->set_pc = hexagon_cpu_set_pc; 348 cc->get_pc = hexagon_cpu_get_pc; 349 cc->gdb_read_register = hexagon_gdb_read_register; 350 cc->gdb_write_register = hexagon_gdb_write_register; 351 cc->gdb_stop_before_watchpoint = true; 352 cc->gdb_core_xml_file = "hexagon-core.xml"; 353 cc->disas_set_info = hexagon_cpu_disas_set_info; 354 cc->tcg_ops = &hexagon_tcg_ops; 355 } 356 357 #define DEFINE_CPU(type_name, initfn) \ 358 { \ 359 .name = type_name, \ 360 .parent = TYPE_HEXAGON_CPU, \ 361 .instance_init = initfn \ 362 } 363 364 static const TypeInfo hexagon_cpu_type_infos[] = { 365 { 366 .name = TYPE_HEXAGON_CPU, 367 .parent = TYPE_CPU, 368 .instance_size = sizeof(HexagonCPU), 369 .instance_align = __alignof(HexagonCPU), 370 .instance_init = hexagon_cpu_init, 371 .abstract = true, 372 .class_size = sizeof(HexagonCPUClass), 373 .class_init = hexagon_cpu_class_init, 374 }, 375 DEFINE_CPU(TYPE_HEXAGON_CPU_V66, hexagon_v66_cpu_init), 376 DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init), 377 DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init), 378 DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init), 379 DEFINE_CPU(TYPE_HEXAGON_CPU_V71, hexagon_v71_cpu_init), 380 DEFINE_CPU(TYPE_HEXAGON_CPU_V73, hexagon_v73_cpu_init), 381 }; 382 383 DEFINE_TYPES(hexagon_cpu_type_infos) 384