1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/qemu-print.h" 20 #include "cpu.h" 21 #include "internal.h" 22 #include "exec/exec-all.h" 23 #include "qapi/error.h" 24 #include "hw/qdev-properties.h" 25 #include "fpu/softfloat-helpers.h" 26 #include "tcg/tcg.h" 27 #include "exec/gdbstub.h" 28 29 static void hexagon_v67_cpu_init(Object *obj) { } 30 static void hexagon_v68_cpu_init(Object *obj) { } 31 static void hexagon_v69_cpu_init(Object *obj) { } 32 static void hexagon_v71_cpu_init(Object *obj) { } 33 static void hexagon_v73_cpu_init(Object *obj) { } 34 35 static void hexagon_cpu_list_entry(gpointer data, gpointer user_data) 36 { 37 ObjectClass *oc = data; 38 char *name = g_strdup(object_class_get_name(oc)); 39 if (g_str_has_suffix(name, HEXAGON_CPU_TYPE_SUFFIX)) { 40 name[strlen(name) - strlen(HEXAGON_CPU_TYPE_SUFFIX)] = '\0'; 41 } 42 qemu_printf(" %s\n", name); 43 g_free(name); 44 } 45 46 void hexagon_cpu_list(void) 47 { 48 GSList *list; 49 list = object_class_get_list_sorted(TYPE_HEXAGON_CPU, false); 50 qemu_printf("Available CPUs:\n"); 51 g_slist_foreach(list, hexagon_cpu_list_entry, NULL); 52 g_slist_free(list); 53 } 54 55 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) 56 { 57 ObjectClass *oc; 58 char *typename; 59 char **cpuname; 60 61 cpuname = g_strsplit(cpu_model, ",", 1); 62 typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]); 63 oc = object_class_by_name(typename); 64 g_strfreev(cpuname); 65 g_free(typename); 66 if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU) || 67 object_class_is_abstract(oc)) { 68 return NULL; 69 } 70 return oc; 71 } 72 73 static Property hexagon_lldb_compat_property = 74 DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false); 75 static Property hexagon_lldb_stack_adjust_property = 76 DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 77 0, qdev_prop_uint32, target_ulong); 78 static Property hexagon_short_circuit_property = 79 DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true); 80 81 const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = { 82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 84 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 85 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 86 "sa0", "lc0", "sa1", "lc1", "p3_0", "c5", "m0", "m1", 87 "usr", "pc", "ugp", "gp", "cs0", "cs1", "c14", "c15", 88 "c16", "c17", "c18", "c19", "pkt_cnt", "insn_cnt", "hvx_cnt", "c23", 89 "c24", "c25", "c26", "c27", "c28", "c29", "c30", "c31", 90 }; 91 92 /* 93 * One of the main debugging techniques is to use "-d cpu" and compare against 94 * LLDB output when single stepping. However, the target and qemu put the 95 * stacks at different locations. This is used to compensate so the diff is 96 * cleaner. 97 */ 98 static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr) 99 { 100 HexagonCPU *cpu = env_archcpu(env); 101 target_ulong stack_adjust = cpu->lldb_stack_adjust; 102 target_ulong stack_start = env->stack_start; 103 target_ulong stack_size = 0x10000; 104 105 if (stack_adjust == 0) { 106 return addr; 107 } 108 109 if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) { 110 return addr - stack_adjust; 111 } 112 return addr; 113 } 114 115 /* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */ 116 static target_ulong read_p3_0(CPUHexagonState *env) 117 { 118 int32_t control_reg = 0; 119 int i; 120 for (i = NUM_PREGS - 1; i >= 0; i--) { 121 control_reg <<= 8; 122 control_reg |= env->pred[i] & 0xff; 123 } 124 return control_reg; 125 } 126 127 static void print_reg(FILE *f, CPUHexagonState *env, int regnum) 128 { 129 target_ulong value; 130 131 if (regnum == HEX_REG_P3_0_ALIASED) { 132 value = read_p3_0(env); 133 } else { 134 value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum]) 135 : env->gpr[regnum]; 136 } 137 138 qemu_fprintf(f, " %s = 0x" TARGET_FMT_lx "\n", 139 hexagon_regnames[regnum], value); 140 } 141 142 static void print_vreg(FILE *f, CPUHexagonState *env, int regnum, 143 bool skip_if_zero) 144 { 145 if (skip_if_zero) { 146 bool nonzero_found = false; 147 for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) { 148 if (env->VRegs[regnum].ub[i] != 0) { 149 nonzero_found = true; 150 break; 151 } 152 } 153 if (!nonzero_found) { 154 return; 155 } 156 } 157 158 qemu_fprintf(f, " v%d = ( ", regnum); 159 qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]); 160 for (int i = MAX_VEC_SIZE_BYTES - 2; i >= 0; i--) { 161 qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]); 162 } 163 qemu_fprintf(f, " )\n"); 164 } 165 166 void hexagon_debug_vreg(CPUHexagonState *env, int regnum) 167 { 168 print_vreg(stdout, env, regnum, false); 169 } 170 171 static void print_qreg(FILE *f, CPUHexagonState *env, int regnum, 172 bool skip_if_zero) 173 { 174 if (skip_if_zero) { 175 bool nonzero_found = false; 176 for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { 177 if (env->QRegs[regnum].ub[i] != 0) { 178 nonzero_found = true; 179 break; 180 } 181 } 182 if (!nonzero_found) { 183 return; 184 } 185 } 186 187 qemu_fprintf(f, " q%d = ( ", regnum); 188 qemu_fprintf(f, "0x%02x", 189 env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]); 190 for (int i = MAX_VEC_SIZE_BYTES / 8 - 2; i >= 0; i--) { 191 qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]); 192 } 193 qemu_fprintf(f, " )\n"); 194 } 195 196 void hexagon_debug_qreg(CPUHexagonState *env, int regnum) 197 { 198 print_qreg(stdout, env, regnum, false); 199 } 200 201 static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags) 202 { 203 HexagonCPU *cpu = env_archcpu(env); 204 205 if (cpu->lldb_compat) { 206 /* 207 * When comparing with LLDB, it doesn't step through single-cycle 208 * hardware loops the same way. So, we just skip them here 209 */ 210 if (env->gpr[HEX_REG_PC] == env->last_pc_dumped) { 211 return; 212 } 213 env->last_pc_dumped = env->gpr[HEX_REG_PC]; 214 } 215 216 qemu_fprintf(f, "General Purpose Registers = {\n"); 217 for (int i = 0; i < 32; i++) { 218 print_reg(f, env, i); 219 } 220 print_reg(f, env, HEX_REG_SA0); 221 print_reg(f, env, HEX_REG_LC0); 222 print_reg(f, env, HEX_REG_SA1); 223 print_reg(f, env, HEX_REG_LC1); 224 print_reg(f, env, HEX_REG_M0); 225 print_reg(f, env, HEX_REG_M1); 226 print_reg(f, env, HEX_REG_USR); 227 print_reg(f, env, HEX_REG_P3_0_ALIASED); 228 print_reg(f, env, HEX_REG_GP); 229 print_reg(f, env, HEX_REG_UGP); 230 print_reg(f, env, HEX_REG_PC); 231 #ifdef CONFIG_USER_ONLY 232 /* 233 * Not modelled in user mode, print junk to minimize the diff's 234 * with LLDB output 235 */ 236 qemu_fprintf(f, " cause = 0x000000db\n"); 237 qemu_fprintf(f, " badva = 0x00000000\n"); 238 qemu_fprintf(f, " cs0 = 0x00000000\n"); 239 qemu_fprintf(f, " cs1 = 0x00000000\n"); 240 #else 241 print_reg(f, env, HEX_REG_CAUSE); 242 print_reg(f, env, HEX_REG_BADVA); 243 print_reg(f, env, HEX_REG_CS0); 244 print_reg(f, env, HEX_REG_CS1); 245 #endif 246 qemu_fprintf(f, "}\n"); 247 248 if (flags & CPU_DUMP_FPU) { 249 qemu_fprintf(f, "Vector Registers = {\n"); 250 for (int i = 0; i < NUM_VREGS; i++) { 251 print_vreg(f, env, i, true); 252 } 253 for (int i = 0; i < NUM_QREGS; i++) { 254 print_qreg(f, env, i, true); 255 } 256 qemu_fprintf(f, "}\n"); 257 } 258 } 259 260 static void hexagon_dump_state(CPUState *cs, FILE *f, int flags) 261 { 262 HexagonCPU *cpu = HEXAGON_CPU(cs); 263 CPUHexagonState *env = &cpu->env; 264 265 hexagon_dump(env, f, flags); 266 } 267 268 void hexagon_debug(CPUHexagonState *env) 269 { 270 hexagon_dump(env, stdout, CPU_DUMP_FPU); 271 } 272 273 static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) 274 { 275 HexagonCPU *cpu = HEXAGON_CPU(cs); 276 CPUHexagonState *env = &cpu->env; 277 env->gpr[HEX_REG_PC] = value; 278 } 279 280 static vaddr hexagon_cpu_get_pc(CPUState *cs) 281 { 282 HexagonCPU *cpu = HEXAGON_CPU(cs); 283 CPUHexagonState *env = &cpu->env; 284 return env->gpr[HEX_REG_PC]; 285 } 286 287 static void hexagon_cpu_synchronize_from_tb(CPUState *cs, 288 const TranslationBlock *tb) 289 { 290 HexagonCPU *cpu = HEXAGON_CPU(cs); 291 CPUHexagonState *env = &cpu->env; 292 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 293 env->gpr[HEX_REG_PC] = tb->pc; 294 } 295 296 static bool hexagon_cpu_has_work(CPUState *cs) 297 { 298 return true; 299 } 300 301 static void hexagon_restore_state_to_opc(CPUState *cs, 302 const TranslationBlock *tb, 303 const uint64_t *data) 304 { 305 HexagonCPU *cpu = HEXAGON_CPU(cs); 306 CPUHexagonState *env = &cpu->env; 307 308 env->gpr[HEX_REG_PC] = data[0]; 309 } 310 311 static void hexagon_cpu_reset_hold(Object *obj) 312 { 313 CPUState *cs = CPU(obj); 314 HexagonCPU *cpu = HEXAGON_CPU(cs); 315 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu); 316 CPUHexagonState *env = &cpu->env; 317 318 if (mcc->parent_phases.hold) { 319 mcc->parent_phases.hold(obj); 320 } 321 322 set_default_nan_mode(1, &env->fp_status); 323 set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); 324 } 325 326 static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) 327 { 328 info->print_insn = print_insn_hexagon; 329 } 330 331 static void hexagon_cpu_realize(DeviceState *dev, Error **errp) 332 { 333 CPUState *cs = CPU(dev); 334 HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev); 335 Error *local_err = NULL; 336 337 cpu_exec_realizefn(cs, &local_err); 338 if (local_err != NULL) { 339 error_propagate(errp, local_err); 340 return; 341 } 342 343 gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register, 344 hexagon_hvx_gdb_write_register, 345 NUM_VREGS + NUM_QREGS, 346 "hexagon-hvx.xml", 0); 347 348 qemu_init_vcpu(cs); 349 cpu_reset(cs); 350 351 mcc->parent_realize(dev, errp); 352 } 353 354 static void hexagon_cpu_init(Object *obj) 355 { 356 qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property); 357 qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property); 358 qdev_property_add_static(DEVICE(obj), &hexagon_short_circuit_property); 359 } 360 361 #include "hw/core/tcg-cpu-ops.h" 362 363 static const struct TCGCPUOps hexagon_tcg_ops = { 364 .initialize = hexagon_translate_init, 365 .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, 366 .restore_state_to_opc = hexagon_restore_state_to_opc, 367 }; 368 369 static void hexagon_cpu_class_init(ObjectClass *c, void *data) 370 { 371 HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c); 372 CPUClass *cc = CPU_CLASS(c); 373 DeviceClass *dc = DEVICE_CLASS(c); 374 ResettableClass *rc = RESETTABLE_CLASS(c); 375 376 device_class_set_parent_realize(dc, hexagon_cpu_realize, 377 &mcc->parent_realize); 378 379 resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL, 380 &mcc->parent_phases); 381 382 cc->class_by_name = hexagon_cpu_class_by_name; 383 cc->has_work = hexagon_cpu_has_work; 384 cc->dump_state = hexagon_dump_state; 385 cc->set_pc = hexagon_cpu_set_pc; 386 cc->get_pc = hexagon_cpu_get_pc; 387 cc->gdb_read_register = hexagon_gdb_read_register; 388 cc->gdb_write_register = hexagon_gdb_write_register; 389 cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS; 390 cc->gdb_stop_before_watchpoint = true; 391 cc->gdb_core_xml_file = "hexagon-core.xml"; 392 cc->disas_set_info = hexagon_cpu_disas_set_info; 393 cc->tcg_ops = &hexagon_tcg_ops; 394 } 395 396 #define DEFINE_CPU(type_name, initfn) \ 397 { \ 398 .name = type_name, \ 399 .parent = TYPE_HEXAGON_CPU, \ 400 .instance_init = initfn \ 401 } 402 403 static const TypeInfo hexagon_cpu_type_infos[] = { 404 { 405 .name = TYPE_HEXAGON_CPU, 406 .parent = TYPE_CPU, 407 .instance_size = sizeof(HexagonCPU), 408 .instance_align = __alignof(HexagonCPU), 409 .instance_init = hexagon_cpu_init, 410 .abstract = true, 411 .class_size = sizeof(HexagonCPUClass), 412 .class_init = hexagon_cpu_class_init, 413 }, 414 DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init), 415 DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init), 416 DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init), 417 DEFINE_CPU(TYPE_HEXAGON_CPU_V71, hexagon_v71_cpu_init), 418 DEFINE_CPU(TYPE_HEXAGON_CPU_V73, hexagon_v73_cpu_init), 419 }; 420 421 DEFINE_TYPES(hexagon_cpu_type_infos) 422