1/*
2 *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 *  This program is free software; you can redistribute it and/or modify
5 *  it under the terms of the GNU General Public License as published by
6 *  the Free Software Foundation; either version 2 of the License, or
7 *  (at your option) any later version.
8 *
9 *  This program is distributed in the hope that it will be useful,
10 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 *  GNU General Public License for more details.
13 *
14 *  You should have received a copy of the GNU General Public License
15 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18/* Keep this as the first attribute: */
19DEF_ATTRIB(AA_DUMMY, "Dummy Zeroth Attribute", "", "")
20
21/* Misc */
22DEF_ATTRIB(EXTENSION, "Extension instruction", "", "")
23
24DEF_ATTRIB(PRIV, "Not available in user or guest mode", "", "")
25DEF_ATTRIB(GUEST, "Not available in user mode", "", "")
26
27DEF_ATTRIB(FPOP, "Floating Point Operation", "", "")
28
29DEF_ATTRIB(EXTENDABLE, "Immediate may be extended", "", "")
30
31DEF_ATTRIB(ARCHV2, "V2 architecture", "", "")
32DEF_ATTRIB(ARCHV3, "V3 architecture", "", "")
33DEF_ATTRIB(ARCHV4, "V4 architecture", "", "")
34DEF_ATTRIB(ARCHV5, "V5 architecture", "", "")
35
36DEF_ATTRIB(SUBINSN, "sub-instruction", "", "")
37
38/* Load and Store attributes */
39DEF_ATTRIB(LOAD, "Loads from memory", "", "")
40DEF_ATTRIB(STORE, "Stores to memory", "", "")
41DEF_ATTRIB(STOREIMMED, "Stores immed to memory", "", "")
42DEF_ATTRIB(MEMSIZE_0B, "Memory width is 0 byte", "", "")
43DEF_ATTRIB(MEMSIZE_1B, "Memory width is 1 byte", "", "")
44DEF_ATTRIB(MEMSIZE_2B, "Memory width is 2 bytes", "", "")
45DEF_ATTRIB(MEMSIZE_4B, "Memory width is 4 bytes", "", "")
46DEF_ATTRIB(MEMSIZE_8B, "Memory width is 8 bytes", "", "")
47DEF_ATTRIB(SCALAR_LOAD, "Load is scalar", "", "")
48DEF_ATTRIB(SCALAR_STORE, "Store is scalar", "", "")
49DEF_ATTRIB(REGWRSIZE_1B, "Memory width is 1 byte", "", "")
50DEF_ATTRIB(REGWRSIZE_2B, "Memory width is 2 bytes", "", "")
51DEF_ATTRIB(REGWRSIZE_4B, "Memory width is 4 bytes", "", "")
52DEF_ATTRIB(REGWRSIZE_8B, "Memory width is 8 bytes", "", "")
53DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "")
54DEF_ATTRIB(MEMLIKE_PACKET_RULES, "follows Memory-like packet rules", "", "")
55DEF_ATTRIB(RELEASE, "Releases a lock", "", "")
56DEF_ATTRIB(ACQUIRE, "Acquires a lock", "", "")
57
58DEF_ATTRIB(RLS_INNER, "Store release inner visibility", "", "")
59DEF_ATTRIB(RLS_ALL_THREAD, "Store release among all threads", "", "")
60DEF_ATTRIB(RLS_SAME_THREAD, "Store release with the same thread", "", "")
61
62/* V6 Vector attributes */
63DEF_ATTRIB(CVI, "Executes on the HVX extension", "", "")
64
65DEF_ATTRIB(CVI_NEW, "New value memory instruction executes on HVX", "", "")
66DEF_ATTRIB(CVI_VM, "Memory instruction executes on HVX", "", "")
67DEF_ATTRIB(CVI_VP, "Permute instruction executes on HVX", "", "")
68DEF_ATTRIB(CVI_VP_VS, "Double vector permute/shft insn executes on HVX", "", "")
69DEF_ATTRIB(CVI_VX, "Multiply instruction executes on HVX", "", "")
70DEF_ATTRIB(CVI_VX_DV, "Double vector multiply insn executes on HVX", "", "")
71DEF_ATTRIB(CVI_VS, "Shift instruction executes on HVX", "", "")
72DEF_ATTRIB(CVI_VS_3SRC, "This shift needs to borrow a source register", "", "")
73DEF_ATTRIB(CVI_VS_VX, "Permute/shift and multiply insn executes on HVX", "", "")
74DEF_ATTRIB(CVI_VA, "ALU instruction executes on HVX", "", "")
75DEF_ATTRIB(CVI_VA_DV, "Double vector alu instruction executes on HVX", "", "")
76DEF_ATTRIB(CVI_4SLOT, "Consumes all the vector execution resources", "", "")
77DEF_ATTRIB(CVI_TMP, "Transient Memory Load not written to register", "", "")
78DEF_ATTRIB(CVI_REMAP, "Register Renaming not written to register file", "", "")
79DEF_ATTRIB(CVI_GATHER, "CVI Gather operation", "", "")
80DEF_ATTRIB(CVI_SCATTER, "CVI Scatter operation", "", "")
81DEF_ATTRIB(CVI_SCATTER_RELEASE, "CVI Store Release for scatter", "", "")
82DEF_ATTRIB(CVI_TMP_DST, "CVI instruction that doesn't write a register", "", "")
83DEF_ATTRIB(CVI_SLOT23, "Can execute in slot 2 or slot 3 (HVX)", "", "")
84
85DEF_ATTRIB(VTCM_ALLBANK_ACCESS, "Allocates in all VTCM schedulers.", "", "")
86
87/* Change-of-flow attributes */
88DEF_ATTRIB(JUMP, "Jump-type instruction", "", "")
89DEF_ATTRIB(INDIRECT, "Absolute register jump", "", "")
90DEF_ATTRIB(CALL, "Function call instruction", "", "")
91DEF_ATTRIB(COF, "Change-of-flow instruction", "", "")
92DEF_ATTRIB(HINTED_COF, "This instruction is a hinted change-of-flow", "", "")
93DEF_ATTRIB(CONDEXEC, "May be cancelled by a predicate", "", "")
94DEF_ATTRIB(DOTNEWVALUE, "Uses a register value generated in this pkt", "", "")
95DEF_ATTRIB(NEWCMPJUMP, "Compound compare and jump", "", "")
96DEF_ATTRIB(NVSTORE, "New-value store", "", "")
97DEF_ATTRIB(MEMOP, "memop", "", "")
98
99DEF_ATTRIB(ROPS_2, "Compound instruction worth 2 RISC-ops", "", "")
100DEF_ATTRIB(ROPS_3, "Compound instruction worth 3 RISC-ops", "", "")
101
102/* access to implicit registers */
103DEF_ATTRIB(IMPLICIT_WRITES_LR, "Writes the link register", "", "UREG.LR")
104DEF_ATTRIB(IMPLICIT_WRITES_SP, "Writes the stack pointer", "", "UREG.SP")
105DEF_ATTRIB(IMPLICIT_WRITES_FP, "Writes the frame pointer", "", "UREG.FP")
106DEF_ATTRIB(IMPLICIT_WRITES_LC0, "Writes loop count for loop 0", "", "UREG.LC0")
107DEF_ATTRIB(IMPLICIT_WRITES_LC1, "Writes loop count for loop 1", "", "UREG.LC1")
108DEF_ATTRIB(IMPLICIT_WRITES_SA0, "Writes start addr for loop 0", "", "UREG.SA0")
109DEF_ATTRIB(IMPLICIT_WRITES_SA1, "Writes start addr for loop 1", "", "UREG.SA1")
110DEF_ATTRIB(IMPLICIT_WRITES_P0, "Writes Predicate 0", "", "UREG.P0")
111DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1")
112DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2")
113DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3")
114DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "")
115DEF_ATTRIB(IMPLICIT_READS_P0, "Reads the P0 register", "", "")
116DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1 register", "", "")
117DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "")
118DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "")
119DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
120DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "")
121DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "")
122DEF_ATTRIB(DEALLOCRET, "dealloc_return", "", "")
123DEF_ATTRIB(DEALLOCFRAME, "deallocframe", "", "")
124
125DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "")
126DEF_ATTRIB(IT_NOP, "nop instruction", "", "")
127DEF_ATTRIB(IT_EXTENDER, "constant extender instruction", "", "")
128
129
130/* Restrictions to make note of */
131DEF_ATTRIB(RESTRICT_COF_MAX1, "One change-of-flow per packet", "", "")
132DEF_ATTRIB(RESTRICT_NOPACKET, "Not allowed in a packet", "", "")
133DEF_ATTRIB(RESTRICT_SLOT0ONLY, "Must execute on slot0", "", "")
134DEF_ATTRIB(RESTRICT_SLOT1ONLY, "Must execute on slot1", "", "")
135DEF_ATTRIB(RESTRICT_SLOT2ONLY, "Must execute on slot2", "", "")
136DEF_ATTRIB(RESTRICT_SLOT3ONLY, "Must execute on slot3", "", "")
137DEF_ATTRIB(RESTRICT_NOSLOT1, "No slot 1 instruction in parallel", "", "")
138DEF_ATTRIB(RESTRICT_PREFERSLOT0, "Try to encode into slot 0", "", "")
139DEF_ATTRIB(RESTRICT_PACKET_AXOK, "May exist with A-type or X-type", "", "")
140
141DEF_ATTRIB(ICOP, "Instruction cache op", "", "")
142
143DEF_ATTRIB(HWLOOP0_END, "Ends HW loop0", "", "")
144DEF_ATTRIB(HWLOOP1_END, "Ends HW loop1", "", "")
145DEF_ATTRIB(RET_TYPE, "return type", "", "")
146DEF_ATTRIB(DCZEROA, "dczeroa type", "", "")
147DEF_ATTRIB(ICFLUSHOP, "icflush op type", "", "")
148DEF_ATTRIB(DCFLUSHOP, "dcflush op type", "", "")
149DEF_ATTRIB(L2FLUSHOP, "l2flush op type", "", "")
150DEF_ATTRIB(DCFETCH, "dcfetch type", "", "")
151
152DEF_ATTRIB(L2FETCH, "Instruction is l2fetch type", "", "")
153
154DEF_ATTRIB(ICINVA, "icinva", "", "")
155DEF_ATTRIB(DCCLEANINVA, "dccleaninva", "", "")
156
157DEF_ATTRIB(NO_INTRINSIC, "Don't generate an intrisic", "", "")
158
159/* Documentation Notes */
160DEF_ATTRIB(NOTE_CONDITIONAL, "can be conditionally executed", "", "")
161DEF_ATTRIB(NOTE_NEWVAL_SLOT0, "New-value oprnd must execute on slot 0", "", "")
162DEF_ATTRIB(NOTE_PRIV, "Monitor-level feature", "", "")
163DEF_ATTRIB(NOTE_NOPACKET, "solo instruction", "", "")
164DEF_ATTRIB(NOTE_AXOK, "May only be grouped with ALU32 or non-FP XTYPE.", "", "")
165DEF_ATTRIB(NOTE_LATEPRED, "The predicate can not be used as a .new", "", "")
166DEF_ATTRIB(NOTE_NVSLOT0, "Can execute only in slot 0 (ST)", "", "")
167DEF_ATTRIB(NOTE_NOVP, "Cannot be paired with a HVX permute instruction", "", "")
168DEF_ATTRIB(NOTE_VA_UNARY, "Combined with HVX ALU op (must be unary)", "", "")
169
170/* V6 MMVector Notes for Documentation */
171DEF_ATTRIB(NOTE_SHIFT_RESOURCE, "Uses the HVX shift resource.", "", "")
172/* Restrictions to make note of */
173DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, "Packet must not have slot 1 store", "", "")
174DEF_ATTRIB(RESTRICT_LATEPRED, "Predicate can not be used as a .new.", "", "")
175
176/* Keep this as the last attribute: */
177DEF_ATTRIB(ZZ_LASTATTRIB, "Last attribute in the file", "", "")
178