1 /* 2 * CRIS emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2008 AXIS Communications AB 5 * Written by Edgar E. Iglesias. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 /* 22 * FIXME: 23 * The condition code translation is in need of attention. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "cpu.h" 28 #include "disas/disas.h" 29 #include "exec/exec-all.h" 30 #include "tcg/tcg-op.h" 31 #include "exec/helper-proto.h" 32 #include "mmu.h" 33 #include "exec/cpu_ldst.h" 34 #include "exec/translator.h" 35 #include "crisv32-decode.h" 36 #include "qemu/qemu-print.h" 37 38 #include "exec/helper-gen.h" 39 40 #include "exec/log.h" 41 42 43 #define DISAS_CRIS 0 44 #if DISAS_CRIS 45 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 46 #else 47 # define LOG_DIS(...) do { } while (0) 48 #endif 49 50 #define D(x) 51 #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) 52 #define BUG_ON(x) ({if (x) BUG();}) 53 54 /* 55 * Target-specific is_jmp field values 56 */ 57 /* Only pc was modified dynamically */ 58 #define DISAS_JUMP DISAS_TARGET_0 59 /* Cpu state was modified dynamically, including pc */ 60 #define DISAS_UPDATE DISAS_TARGET_1 61 /* Cpu state was modified dynamically, excluding pc -- use npc */ 62 #define DISAS_UPDATE_NEXT DISAS_TARGET_2 63 /* PC update for delayed branch, see cpustate_changed otherwise */ 64 #define DISAS_DBRANCH DISAS_TARGET_3 65 66 /* Used by the decoder. */ 67 #define EXTRACT_FIELD(src, start, end) \ 68 (((src) >> start) & ((1 << (end - start + 1)) - 1)) 69 70 #define CC_MASK_NZ 0xc 71 #define CC_MASK_NZV 0xe 72 #define CC_MASK_NZVC 0xf 73 #define CC_MASK_RNZV 0x10e 74 75 static TCGv cpu_R[16]; 76 static TCGv cpu_PR[16]; 77 static TCGv cc_x; 78 static TCGv cc_src; 79 static TCGv cc_dest; 80 static TCGv cc_result; 81 static TCGv cc_op; 82 static TCGv cc_size; 83 static TCGv cc_mask; 84 85 static TCGv env_btaken; 86 static TCGv env_btarget; 87 static TCGv env_pc; 88 89 #include "exec/gen-icount.h" 90 91 /* This is the state at translation time. */ 92 typedef struct DisasContext { 93 DisasContextBase base; 94 95 CRISCPU *cpu; 96 target_ulong pc, ppc; 97 98 /* Decoder. */ 99 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc); 100 uint32_t ir; 101 uint32_t opcode; 102 unsigned int op1; 103 unsigned int op2; 104 unsigned int zsize, zzsize; 105 unsigned int mode; 106 unsigned int postinc; 107 108 unsigned int size; 109 unsigned int src; 110 unsigned int dst; 111 unsigned int cond; 112 113 int update_cc; 114 int cc_op; 115 int cc_size; 116 uint32_t cc_mask; 117 118 int cc_size_uptodate; /* -1 invalid or last written value. */ 119 120 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */ 121 int flags_uptodate; /* Whether or not $ccs is up-to-date. */ 122 int flags_x; 123 124 int clear_x; /* Clear x after this insn? */ 125 int clear_prefix; /* Clear prefix after this insn? */ 126 int clear_locked_irq; /* Clear the irq lockout. */ 127 int cpustate_changed; 128 unsigned int tb_flags; /* tb dependent flags. */ 129 130 #define JMP_NOJMP 0 131 #define JMP_DIRECT 1 132 #define JMP_DIRECT_CC 2 133 #define JMP_INDIRECT 3 134 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */ 135 uint32_t jmp_pc; 136 137 int delayed_branch; 138 } DisasContext; 139 140 static void gen_BUG(DisasContext *dc, const char *file, int line) 141 { 142 cpu_abort(CPU(dc->cpu), "%s:%d pc=%x\n", file, line, dc->pc); 143 } 144 145 static const char * const regnames_v32[] = 146 { 147 "$r0", "$r1", "$r2", "$r3", 148 "$r4", "$r5", "$r6", "$r7", 149 "$r8", "$r9", "$r10", "$r11", 150 "$r12", "$r13", "$sp", "$acr", 151 }; 152 153 static const char * const pregnames_v32[] = 154 { 155 "$bz", "$vr", "$pid", "$srs", 156 "$wz", "$exs", "$eda", "$mof", 157 "$dz", "$ebp", "$erp", "$srp", 158 "$nrp", "$ccs", "$usp", "$spc", 159 }; 160 161 /* We need this table to handle preg-moves with implicit width. */ 162 static const int preg_sizes[] = { 163 1, /* bz. */ 164 1, /* vr. */ 165 4, /* pid. */ 166 1, /* srs. */ 167 2, /* wz. */ 168 4, 4, 4, 169 4, 4, 4, 4, 170 4, 4, 4, 4, 171 }; 172 173 #define t_gen_mov_TN_env(tn, member) \ 174 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member)) 175 #define t_gen_mov_env_TN(member, tn) \ 176 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member)) 177 #define t_gen_movi_env_TN(member, c) \ 178 do { \ 179 TCGv tc = tcg_const_tl(c); \ 180 t_gen_mov_env_TN(member, tc); \ 181 } while (0) 182 183 static inline void t_gen_mov_TN_preg(TCGv tn, int r) 184 { 185 assert(r >= 0 && r <= 15); 186 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { 187 tcg_gen_movi_tl(tn, 0); 188 } else if (r == PR_VR) { 189 tcg_gen_movi_tl(tn, 32); 190 } else { 191 tcg_gen_mov_tl(tn, cpu_PR[r]); 192 } 193 } 194 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn) 195 { 196 assert(r >= 0 && r <= 15); 197 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { 198 return; 199 } else if (r == PR_SRS) { 200 tcg_gen_andi_tl(cpu_PR[r], tn, 3); 201 } else { 202 if (r == PR_PID) { 203 gen_helper_tlb_flush_pid(cpu_env, tn); 204 } 205 if (dc->tb_flags & S_FLAG && r == PR_SPC) { 206 gen_helper_spc_write(cpu_env, tn); 207 } else if (r == PR_CCS) { 208 dc->cpustate_changed = 1; 209 } 210 tcg_gen_mov_tl(cpu_PR[r], tn); 211 } 212 } 213 214 /* Sign extend at translation time. */ 215 static int sign_extend(unsigned int val, unsigned int width) 216 { 217 int sval; 218 219 /* LSL. */ 220 val <<= 31 - width; 221 sval = val; 222 /* ASR. */ 223 sval >>= 31 - width; 224 return sval; 225 } 226 227 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr, 228 unsigned int size, unsigned int sign) 229 { 230 int r; 231 232 switch (size) { 233 case 4: 234 { 235 r = cpu_ldl_code(env, addr); 236 break; 237 } 238 case 2: 239 { 240 if (sign) { 241 r = cpu_ldsw_code(env, addr); 242 } else { 243 r = cpu_lduw_code(env, addr); 244 } 245 break; 246 } 247 case 1: 248 { 249 if (sign) { 250 r = cpu_ldsb_code(env, addr); 251 } else { 252 r = cpu_ldub_code(env, addr); 253 } 254 break; 255 } 256 default: 257 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size); 258 break; 259 } 260 return r; 261 } 262 263 static void cris_lock_irq(DisasContext *dc) 264 { 265 dc->clear_locked_irq = 0; 266 t_gen_movi_env_TN(locked_irq, 1); 267 } 268 269 static inline void t_gen_raise_exception(uint32_t index) 270 { 271 TCGv_i32 tmp = tcg_const_i32(index); 272 gen_helper_raise_exception(cpu_env, tmp); 273 } 274 275 static void t_gen_lsl(TCGv d, TCGv a, TCGv b) 276 { 277 TCGv t0, t_31; 278 279 t0 = tcg_temp_new(); 280 t_31 = tcg_const_tl(31); 281 tcg_gen_shl_tl(d, a, b); 282 283 tcg_gen_sub_tl(t0, t_31, b); 284 tcg_gen_sar_tl(t0, t0, t_31); 285 tcg_gen_and_tl(t0, t0, d); 286 tcg_gen_xor_tl(d, d, t0); 287 } 288 289 static void t_gen_lsr(TCGv d, TCGv a, TCGv b) 290 { 291 TCGv t0, t_31; 292 293 t0 = tcg_temp_new(); 294 t_31 = tcg_temp_new(); 295 tcg_gen_shr_tl(d, a, b); 296 297 tcg_gen_movi_tl(t_31, 31); 298 tcg_gen_sub_tl(t0, t_31, b); 299 tcg_gen_sar_tl(t0, t0, t_31); 300 tcg_gen_and_tl(t0, t0, d); 301 tcg_gen_xor_tl(d, d, t0); 302 } 303 304 static void t_gen_asr(TCGv d, TCGv a, TCGv b) 305 { 306 TCGv t0, t_31; 307 308 t0 = tcg_temp_new(); 309 t_31 = tcg_temp_new(); 310 tcg_gen_sar_tl(d, a, b); 311 312 tcg_gen_movi_tl(t_31, 31); 313 tcg_gen_sub_tl(t0, t_31, b); 314 tcg_gen_sar_tl(t0, t0, t_31); 315 tcg_gen_or_tl(d, d, t0); 316 } 317 318 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b) 319 { 320 TCGv t = tcg_temp_new(); 321 322 /* 323 * d <<= 1 324 * if (d >= s) 325 * d -= s; 326 */ 327 tcg_gen_shli_tl(d, a, 1); 328 tcg_gen_sub_tl(t, d, b); 329 tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d); 330 } 331 332 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs) 333 { 334 TCGv t; 335 336 /* 337 * d <<= 1 338 * if (n) 339 * d += s; 340 */ 341 t = tcg_temp_new(); 342 tcg_gen_shli_tl(d, a, 1); 343 tcg_gen_shli_tl(t, ccs, 31 - 3); 344 tcg_gen_sari_tl(t, t, 31); 345 tcg_gen_and_tl(t, t, b); 346 tcg_gen_add_tl(d, d, t); 347 } 348 349 /* Extended arithmetics on CRIS. */ 350 static inline void t_gen_add_flag(TCGv d, int flag) 351 { 352 TCGv c; 353 354 c = tcg_temp_new(); 355 t_gen_mov_TN_preg(c, PR_CCS); 356 /* Propagate carry into d. */ 357 tcg_gen_andi_tl(c, c, 1 << flag); 358 if (flag) { 359 tcg_gen_shri_tl(c, c, flag); 360 } 361 tcg_gen_add_tl(d, d, c); 362 } 363 364 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d) 365 { 366 if (dc->flags_x) { 367 TCGv c = tcg_temp_new(); 368 369 t_gen_mov_TN_preg(c, PR_CCS); 370 /* C flag is already at bit 0. */ 371 tcg_gen_andi_tl(c, c, C_FLAG); 372 tcg_gen_add_tl(d, d, c); 373 } 374 } 375 376 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d) 377 { 378 if (dc->flags_x) { 379 TCGv c = tcg_temp_new(); 380 381 t_gen_mov_TN_preg(c, PR_CCS); 382 /* C flag is already at bit 0. */ 383 tcg_gen_andi_tl(c, c, C_FLAG); 384 tcg_gen_sub_tl(d, d, c); 385 } 386 } 387 388 /* Swap the two bytes within each half word of the s operand. 389 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */ 390 static inline void t_gen_swapb(TCGv d, TCGv s) 391 { 392 TCGv t, org_s; 393 394 t = tcg_temp_new(); 395 org_s = tcg_temp_new(); 396 397 /* d and s may refer to the same object. */ 398 tcg_gen_mov_tl(org_s, s); 399 tcg_gen_shli_tl(t, org_s, 8); 400 tcg_gen_andi_tl(d, t, 0xff00ff00); 401 tcg_gen_shri_tl(t, org_s, 8); 402 tcg_gen_andi_tl(t, t, 0x00ff00ff); 403 tcg_gen_or_tl(d, d, t); 404 } 405 406 /* Swap the halfwords of the s operand. */ 407 static inline void t_gen_swapw(TCGv d, TCGv s) 408 { 409 TCGv t; 410 /* d and s refer the same object. */ 411 t = tcg_temp_new(); 412 tcg_gen_mov_tl(t, s); 413 tcg_gen_shli_tl(d, t, 16); 414 tcg_gen_shri_tl(t, t, 16); 415 tcg_gen_or_tl(d, d, t); 416 } 417 418 /* Reverse the within each byte. 419 T0 = (((T0 << 7) & 0x80808080) | 420 ((T0 << 5) & 0x40404040) | 421 ((T0 << 3) & 0x20202020) | 422 ((T0 << 1) & 0x10101010) | 423 ((T0 >> 1) & 0x08080808) | 424 ((T0 >> 3) & 0x04040404) | 425 ((T0 >> 5) & 0x02020202) | 426 ((T0 >> 7) & 0x01010101)); 427 */ 428 static void t_gen_swapr(TCGv d, TCGv s) 429 { 430 static const struct { 431 int shift; /* LSL when positive, LSR when negative. */ 432 uint32_t mask; 433 } bitrev[] = { 434 {7, 0x80808080}, 435 {5, 0x40404040}, 436 {3, 0x20202020}, 437 {1, 0x10101010}, 438 {-1, 0x08080808}, 439 {-3, 0x04040404}, 440 {-5, 0x02020202}, 441 {-7, 0x01010101} 442 }; 443 int i; 444 TCGv t, org_s; 445 446 /* d and s refer the same object. */ 447 t = tcg_temp_new(); 448 org_s = tcg_temp_new(); 449 tcg_gen_mov_tl(org_s, s); 450 451 tcg_gen_shli_tl(t, org_s, bitrev[0].shift); 452 tcg_gen_andi_tl(d, t, bitrev[0].mask); 453 for (i = 1; i < ARRAY_SIZE(bitrev); i++) { 454 if (bitrev[i].shift >= 0) { 455 tcg_gen_shli_tl(t, org_s, bitrev[i].shift); 456 } else { 457 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift); 458 } 459 tcg_gen_andi_tl(t, t, bitrev[i].mask); 460 tcg_gen_or_tl(d, d, t); 461 } 462 } 463 464 static bool use_goto_tb(DisasContext *dc, target_ulong dest) 465 { 466 return translator_use_goto_tb(&dc->base, dest); 467 } 468 469 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) 470 { 471 if (use_goto_tb(dc, dest)) { 472 tcg_gen_goto_tb(n); 473 tcg_gen_movi_tl(env_pc, dest); 474 tcg_gen_exit_tb(dc->base.tb, n); 475 } else { 476 tcg_gen_movi_tl(env_pc, dest); 477 tcg_gen_lookup_and_goto_ptr(); 478 } 479 } 480 481 static inline void cris_clear_x_flag(DisasContext *dc) 482 { 483 if (dc->flags_x) { 484 dc->flags_uptodate = 0; 485 } 486 dc->flags_x = 0; 487 } 488 489 static void cris_flush_cc_state(DisasContext *dc) 490 { 491 if (dc->cc_size_uptodate != dc->cc_size) { 492 tcg_gen_movi_tl(cc_size, dc->cc_size); 493 dc->cc_size_uptodate = dc->cc_size; 494 } 495 tcg_gen_movi_tl(cc_op, dc->cc_op); 496 tcg_gen_movi_tl(cc_mask, dc->cc_mask); 497 } 498 499 static void cris_evaluate_flags(DisasContext *dc) 500 { 501 if (dc->flags_uptodate) { 502 return; 503 } 504 505 cris_flush_cc_state(dc); 506 507 switch (dc->cc_op) { 508 case CC_OP_MCP: 509 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env, 510 cpu_PR[PR_CCS], cc_src, 511 cc_dest, cc_result); 512 break; 513 case CC_OP_MULS: 514 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env, 515 cpu_PR[PR_CCS], cc_result, 516 cpu_PR[PR_MOF]); 517 break; 518 case CC_OP_MULU: 519 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env, 520 cpu_PR[PR_CCS], cc_result, 521 cpu_PR[PR_MOF]); 522 break; 523 case CC_OP_MOVE: 524 case CC_OP_AND: 525 case CC_OP_OR: 526 case CC_OP_XOR: 527 case CC_OP_ASR: 528 case CC_OP_LSR: 529 case CC_OP_LSL: 530 switch (dc->cc_size) { 531 case 4: 532 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], 533 cpu_env, cpu_PR[PR_CCS], cc_result); 534 break; 535 case 2: 536 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], 537 cpu_env, cpu_PR[PR_CCS], cc_result); 538 break; 539 default: 540 gen_helper_evaluate_flags(cpu_env); 541 break; 542 } 543 break; 544 case CC_OP_FLAGS: 545 /* live. */ 546 break; 547 case CC_OP_SUB: 548 case CC_OP_CMP: 549 if (dc->cc_size == 4) { 550 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env, 551 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); 552 } else { 553 gen_helper_evaluate_flags(cpu_env); 554 } 555 556 break; 557 default: 558 switch (dc->cc_size) { 559 case 4: 560 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env, 561 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); 562 break; 563 default: 564 gen_helper_evaluate_flags(cpu_env); 565 break; 566 } 567 break; 568 } 569 570 if (dc->flags_x) { 571 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG); 572 } else if (dc->cc_op == CC_OP_FLAGS) { 573 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG); 574 } 575 dc->flags_uptodate = 1; 576 } 577 578 static void cris_cc_mask(DisasContext *dc, unsigned int mask) 579 { 580 uint32_t ovl; 581 582 if (!mask) { 583 dc->update_cc = 0; 584 return; 585 } 586 587 /* Check if we need to evaluate the condition codes due to 588 CC overlaying. */ 589 ovl = (dc->cc_mask ^ mask) & ~mask; 590 if (ovl) { 591 /* TODO: optimize this case. It trigs all the time. */ 592 cris_evaluate_flags(dc); 593 } 594 dc->cc_mask = mask; 595 dc->update_cc = 1; 596 } 597 598 static void cris_update_cc_op(DisasContext *dc, int op, int size) 599 { 600 dc->cc_op = op; 601 dc->cc_size = size; 602 dc->flags_uptodate = 0; 603 } 604 605 static inline void cris_update_cc_x(DisasContext *dc) 606 { 607 /* Save the x flag state at the time of the cc snapshot. */ 608 if (dc->cc_x_uptodate == (2 | dc->flags_x)) { 609 return; 610 } 611 tcg_gen_movi_tl(cc_x, dc->flags_x); 612 dc->cc_x_uptodate = 2 | dc->flags_x; 613 } 614 615 /* Update cc prior to executing ALU op. Needs source operands untouched. */ 616 static void cris_pre_alu_update_cc(DisasContext *dc, int op, 617 TCGv dst, TCGv src, int size) 618 { 619 if (dc->update_cc) { 620 cris_update_cc_op(dc, op, size); 621 tcg_gen_mov_tl(cc_src, src); 622 623 if (op != CC_OP_MOVE 624 && op != CC_OP_AND 625 && op != CC_OP_OR 626 && op != CC_OP_XOR 627 && op != CC_OP_ASR 628 && op != CC_OP_LSR 629 && op != CC_OP_LSL) { 630 tcg_gen_mov_tl(cc_dest, dst); 631 } 632 633 cris_update_cc_x(dc); 634 } 635 } 636 637 /* Update cc after executing ALU op. needs the result. */ 638 static inline void cris_update_result(DisasContext *dc, TCGv res) 639 { 640 if (dc->update_cc) { 641 tcg_gen_mov_tl(cc_result, res); 642 } 643 } 644 645 /* Returns one if the write back stage should execute. */ 646 static void cris_alu_op_exec(DisasContext *dc, int op, 647 TCGv dst, TCGv a, TCGv b, int size) 648 { 649 /* Emit the ALU insns. */ 650 switch (op) { 651 case CC_OP_ADD: 652 tcg_gen_add_tl(dst, a, b); 653 /* Extended arithmetics. */ 654 t_gen_addx_carry(dc, dst); 655 break; 656 case CC_OP_ADDC: 657 tcg_gen_add_tl(dst, a, b); 658 t_gen_add_flag(dst, 0); /* C_FLAG. */ 659 break; 660 case CC_OP_MCP: 661 tcg_gen_add_tl(dst, a, b); 662 t_gen_add_flag(dst, 8); /* R_FLAG. */ 663 break; 664 case CC_OP_SUB: 665 tcg_gen_sub_tl(dst, a, b); 666 /* Extended arithmetics. */ 667 t_gen_subx_carry(dc, dst); 668 break; 669 case CC_OP_MOVE: 670 tcg_gen_mov_tl(dst, b); 671 break; 672 case CC_OP_OR: 673 tcg_gen_or_tl(dst, a, b); 674 break; 675 case CC_OP_AND: 676 tcg_gen_and_tl(dst, a, b); 677 break; 678 case CC_OP_XOR: 679 tcg_gen_xor_tl(dst, a, b); 680 break; 681 case CC_OP_LSL: 682 t_gen_lsl(dst, a, b); 683 break; 684 case CC_OP_LSR: 685 t_gen_lsr(dst, a, b); 686 break; 687 case CC_OP_ASR: 688 t_gen_asr(dst, a, b); 689 break; 690 case CC_OP_NEG: 691 tcg_gen_neg_tl(dst, b); 692 /* Extended arithmetics. */ 693 t_gen_subx_carry(dc, dst); 694 break; 695 case CC_OP_LZ: 696 tcg_gen_clzi_tl(dst, b, TARGET_LONG_BITS); 697 break; 698 case CC_OP_MULS: 699 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b); 700 break; 701 case CC_OP_MULU: 702 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b); 703 break; 704 case CC_OP_DSTEP: 705 t_gen_cris_dstep(dst, a, b); 706 break; 707 case CC_OP_MSTEP: 708 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]); 709 break; 710 case CC_OP_BOUND: 711 tcg_gen_movcond_tl(TCG_COND_LEU, dst, a, b, a, b); 712 break; 713 case CC_OP_CMP: 714 tcg_gen_sub_tl(dst, a, b); 715 /* Extended arithmetics. */ 716 t_gen_subx_carry(dc, dst); 717 break; 718 default: 719 qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n"); 720 BUG(); 721 break; 722 } 723 724 if (size == 1) { 725 tcg_gen_andi_tl(dst, dst, 0xff); 726 } else if (size == 2) { 727 tcg_gen_andi_tl(dst, dst, 0xffff); 728 } 729 } 730 731 static void cris_alu(DisasContext *dc, int op, 732 TCGv d, TCGv op_a, TCGv op_b, int size) 733 { 734 TCGv tmp; 735 int writeback; 736 737 writeback = 1; 738 739 if (op == CC_OP_CMP) { 740 tmp = tcg_temp_new(); 741 writeback = 0; 742 } else if (size == 4) { 743 tmp = d; 744 writeback = 0; 745 } else { 746 tmp = tcg_temp_new(); 747 } 748 749 750 cris_pre_alu_update_cc(dc, op, op_a, op_b, size); 751 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size); 752 cris_update_result(dc, tmp); 753 754 /* Writeback. */ 755 if (writeback) { 756 if (size == 1) { 757 tcg_gen_andi_tl(d, d, ~0xff); 758 } else { 759 tcg_gen_andi_tl(d, d, ~0xffff); 760 } 761 tcg_gen_or_tl(d, d, tmp); 762 } 763 } 764 765 static int arith_cc(DisasContext *dc) 766 { 767 if (dc->update_cc) { 768 switch (dc->cc_op) { 769 case CC_OP_ADDC: return 1; 770 case CC_OP_ADD: return 1; 771 case CC_OP_SUB: return 1; 772 case CC_OP_DSTEP: return 1; 773 case CC_OP_LSL: return 1; 774 case CC_OP_LSR: return 1; 775 case CC_OP_ASR: return 1; 776 case CC_OP_CMP: return 1; 777 case CC_OP_NEG: return 1; 778 case CC_OP_OR: return 1; 779 case CC_OP_AND: return 1; 780 case CC_OP_XOR: return 1; 781 case CC_OP_MULU: return 1; 782 case CC_OP_MULS: return 1; 783 default: 784 return 0; 785 } 786 } 787 return 0; 788 } 789 790 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond) 791 { 792 int arith_opt, move_opt; 793 794 /* TODO: optimize more condition codes. */ 795 796 /* 797 * If the flags are live, we've gotta look into the bits of CCS. 798 * Otherwise, if we just did an arithmetic operation we try to 799 * evaluate the condition code faster. 800 * 801 * When this function is done, T0 should be non-zero if the condition 802 * code is true. 803 */ 804 arith_opt = arith_cc(dc) && !dc->flags_uptodate; 805 move_opt = (dc->cc_op == CC_OP_MOVE); 806 switch (cond) { 807 case CC_EQ: 808 if ((arith_opt || move_opt) 809 && dc->cc_x_uptodate != (2 | X_FLAG)) { 810 tcg_gen_setcondi_tl(TCG_COND_EQ, cc, cc_result, 0); 811 } else { 812 cris_evaluate_flags(dc); 813 tcg_gen_andi_tl(cc, 814 cpu_PR[PR_CCS], Z_FLAG); 815 } 816 break; 817 case CC_NE: 818 if ((arith_opt || move_opt) 819 && dc->cc_x_uptodate != (2 | X_FLAG)) { 820 tcg_gen_mov_tl(cc, cc_result); 821 } else { 822 cris_evaluate_flags(dc); 823 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], 824 Z_FLAG); 825 tcg_gen_andi_tl(cc, cc, Z_FLAG); 826 } 827 break; 828 case CC_CS: 829 cris_evaluate_flags(dc); 830 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG); 831 break; 832 case CC_CC: 833 cris_evaluate_flags(dc); 834 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG); 835 tcg_gen_andi_tl(cc, cc, C_FLAG); 836 break; 837 case CC_VS: 838 cris_evaluate_flags(dc); 839 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG); 840 break; 841 case CC_VC: 842 cris_evaluate_flags(dc); 843 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], 844 V_FLAG); 845 tcg_gen_andi_tl(cc, cc, V_FLAG); 846 break; 847 case CC_PL: 848 if (arith_opt || move_opt) { 849 int bits = 31; 850 851 if (dc->cc_size == 1) { 852 bits = 7; 853 } else if (dc->cc_size == 2) { 854 bits = 15; 855 } 856 857 tcg_gen_shri_tl(cc, cc_result, bits); 858 tcg_gen_xori_tl(cc, cc, 1); 859 } else { 860 cris_evaluate_flags(dc); 861 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], 862 N_FLAG); 863 tcg_gen_andi_tl(cc, cc, N_FLAG); 864 } 865 break; 866 case CC_MI: 867 if (arith_opt || move_opt) { 868 int bits = 31; 869 870 if (dc->cc_size == 1) { 871 bits = 7; 872 } else if (dc->cc_size == 2) { 873 bits = 15; 874 } 875 876 tcg_gen_shri_tl(cc, cc_result, bits); 877 tcg_gen_andi_tl(cc, cc, 1); 878 } else { 879 cris_evaluate_flags(dc); 880 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], 881 N_FLAG); 882 } 883 break; 884 case CC_LS: 885 cris_evaluate_flags(dc); 886 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], 887 C_FLAG | Z_FLAG); 888 break; 889 case CC_HI: 890 cris_evaluate_flags(dc); 891 { 892 TCGv tmp; 893 894 tmp = tcg_temp_new(); 895 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS], 896 C_FLAG | Z_FLAG); 897 /* Overlay the C flag on top of the Z. */ 898 tcg_gen_shli_tl(cc, tmp, 2); 899 tcg_gen_and_tl(cc, tmp, cc); 900 tcg_gen_andi_tl(cc, cc, Z_FLAG); 901 } 902 break; 903 case CC_GE: 904 cris_evaluate_flags(dc); 905 /* Overlay the V flag on top of the N. */ 906 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2); 907 tcg_gen_xor_tl(cc, 908 cpu_PR[PR_CCS], cc); 909 tcg_gen_andi_tl(cc, cc, N_FLAG); 910 tcg_gen_xori_tl(cc, cc, N_FLAG); 911 break; 912 case CC_LT: 913 cris_evaluate_flags(dc); 914 /* Overlay the V flag on top of the N. */ 915 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2); 916 tcg_gen_xor_tl(cc, 917 cpu_PR[PR_CCS], cc); 918 tcg_gen_andi_tl(cc, cc, N_FLAG); 919 break; 920 case CC_GT: 921 cris_evaluate_flags(dc); 922 { 923 TCGv n, z; 924 925 n = tcg_temp_new(); 926 z = tcg_temp_new(); 927 928 /* To avoid a shift we overlay everything on 929 the V flag. */ 930 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2); 931 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1); 932 /* invert Z. */ 933 tcg_gen_xori_tl(z, z, 2); 934 935 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); 936 tcg_gen_xori_tl(n, n, 2); 937 tcg_gen_and_tl(cc, z, n); 938 tcg_gen_andi_tl(cc, cc, 2); 939 } 940 break; 941 case CC_LE: 942 cris_evaluate_flags(dc); 943 { 944 TCGv n, z; 945 946 n = tcg_temp_new(); 947 z = tcg_temp_new(); 948 949 /* To avoid a shift we overlay everything on 950 the V flag. */ 951 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2); 952 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1); 953 954 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); 955 tcg_gen_or_tl(cc, z, n); 956 tcg_gen_andi_tl(cc, cc, 2); 957 } 958 break; 959 case CC_P: 960 cris_evaluate_flags(dc); 961 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG); 962 break; 963 case CC_A: 964 tcg_gen_movi_tl(cc, 1); 965 break; 966 default: 967 BUG(); 968 break; 969 }; 970 } 971 972 static void cris_store_direct_jmp(DisasContext *dc) 973 { 974 /* Store the direct jmp state into the cpu-state. */ 975 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { 976 if (dc->jmp == JMP_DIRECT) { 977 tcg_gen_movi_tl(env_btaken, 1); 978 } 979 tcg_gen_movi_tl(env_btarget, dc->jmp_pc); 980 dc->jmp = JMP_INDIRECT; 981 } 982 } 983 984 static void cris_prepare_cc_branch (DisasContext *dc, 985 int offset, int cond) 986 { 987 /* This helps us re-schedule the micro-code to insns in delay-slots 988 before the actual jump. */ 989 dc->delayed_branch = 2; 990 dc->jmp = JMP_DIRECT_CC; 991 dc->jmp_pc = dc->pc + offset; 992 993 gen_tst_cc(dc, env_btaken, cond); 994 tcg_gen_movi_tl(env_btarget, dc->jmp_pc); 995 } 996 997 998 /* jumps, when the dest is in a live reg for example. Direct should be set 999 when the dest addr is constant to allow tb chaining. */ 1000 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type) 1001 { 1002 /* This helps us re-schedule the micro-code to insns in delay-slots 1003 before the actual jump. */ 1004 dc->delayed_branch = 2; 1005 dc->jmp = type; 1006 if (type == JMP_INDIRECT) { 1007 tcg_gen_movi_tl(env_btaken, 1); 1008 } 1009 } 1010 1011 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr) 1012 { 1013 int mem_index = cpu_mmu_index(&dc->cpu->env, false); 1014 1015 /* If we get a fault on a delayslot we must keep the jmp state in 1016 the cpu-state to be able to re-execute the jmp. */ 1017 if (dc->delayed_branch == 1) { 1018 cris_store_direct_jmp(dc); 1019 } 1020 1021 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEUQ); 1022 } 1023 1024 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr, 1025 unsigned int size, int sign) 1026 { 1027 int mem_index = cpu_mmu_index(&dc->cpu->env, false); 1028 1029 /* If we get a fault on a delayslot we must keep the jmp state in 1030 the cpu-state to be able to re-execute the jmp. */ 1031 if (dc->delayed_branch == 1) { 1032 cris_store_direct_jmp(dc); 1033 } 1034 1035 tcg_gen_qemu_ld_tl(dst, addr, mem_index, 1036 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0)); 1037 } 1038 1039 static void gen_store (DisasContext *dc, TCGv addr, TCGv val, 1040 unsigned int size) 1041 { 1042 int mem_index = cpu_mmu_index(&dc->cpu->env, false); 1043 1044 /* If we get a fault on a delayslot we must keep the jmp state in 1045 the cpu-state to be able to re-execute the jmp. */ 1046 if (dc->delayed_branch == 1) { 1047 cris_store_direct_jmp(dc); 1048 } 1049 1050 1051 /* Conditional writes. We only support the kind were X and P are known 1052 at translation time. */ 1053 if (dc->flags_x && (dc->tb_flags & P_FLAG)) { 1054 dc->postinc = 0; 1055 cris_evaluate_flags(dc); 1056 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG); 1057 return; 1058 } 1059 1060 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size)); 1061 1062 if (dc->flags_x) { 1063 cris_evaluate_flags(dc); 1064 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG); 1065 } 1066 } 1067 1068 static inline void t_gen_sext(TCGv d, TCGv s, int size) 1069 { 1070 if (size == 1) { 1071 tcg_gen_ext8s_i32(d, s); 1072 } else if (size == 2) { 1073 tcg_gen_ext16s_i32(d, s); 1074 } else { 1075 tcg_gen_mov_tl(d, s); 1076 } 1077 } 1078 1079 static inline void t_gen_zext(TCGv d, TCGv s, int size) 1080 { 1081 if (size == 1) { 1082 tcg_gen_ext8u_i32(d, s); 1083 } else if (size == 2) { 1084 tcg_gen_ext16u_i32(d, s); 1085 } else { 1086 tcg_gen_mov_tl(d, s); 1087 } 1088 } 1089 1090 #if DISAS_CRIS 1091 static char memsize_char(int size) 1092 { 1093 switch (size) { 1094 case 1: return 'b'; 1095 case 2: return 'w'; 1096 case 4: return 'd'; 1097 default: 1098 return 'x'; 1099 } 1100 } 1101 #endif 1102 1103 static inline unsigned int memsize_z(DisasContext *dc) 1104 { 1105 return dc->zsize + 1; 1106 } 1107 1108 static inline unsigned int memsize_zz(DisasContext *dc) 1109 { 1110 switch (dc->zzsize) { 1111 case 0: return 1; 1112 case 1: return 2; 1113 default: 1114 return 4; 1115 } 1116 } 1117 1118 static inline void do_postinc (DisasContext *dc, int size) 1119 { 1120 if (dc->postinc) { 1121 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size); 1122 } 1123 } 1124 1125 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd, 1126 int size, int s_ext, TCGv dst) 1127 { 1128 if (s_ext) { 1129 t_gen_sext(dst, cpu_R[rs], size); 1130 } else { 1131 t_gen_zext(dst, cpu_R[rs], size); 1132 } 1133 } 1134 1135 /* Prepare T0 and T1 for a register alu operation. 1136 s_ext decides if the operand1 should be sign-extended or zero-extended when 1137 needed. */ 1138 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd, 1139 int size, int s_ext, TCGv dst, TCGv src) 1140 { 1141 dec_prep_move_r(dc, rs, rd, size, s_ext, src); 1142 1143 if (s_ext) { 1144 t_gen_sext(dst, cpu_R[rd], size); 1145 } else { 1146 t_gen_zext(dst, cpu_R[rd], size); 1147 } 1148 } 1149 1150 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc, 1151 int s_ext, int memsize, TCGv dst) 1152 { 1153 unsigned int rs; 1154 uint32_t imm; 1155 int is_imm; 1156 int insn_len = 2; 1157 1158 rs = dc->op1; 1159 is_imm = rs == 15 && dc->postinc; 1160 1161 /* Load [$rs] onto T1. */ 1162 if (is_imm) { 1163 insn_len = 2 + memsize; 1164 if (memsize == 1) { 1165 insn_len++; 1166 } 1167 1168 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext); 1169 tcg_gen_movi_tl(dst, imm); 1170 dc->postinc = 0; 1171 } else { 1172 cris_flush_cc_state(dc); 1173 gen_load(dc, dst, cpu_R[rs], memsize, 0); 1174 if (s_ext) { 1175 t_gen_sext(dst, dst, memsize); 1176 } else { 1177 t_gen_zext(dst, dst, memsize); 1178 } 1179 } 1180 return insn_len; 1181 } 1182 1183 /* Prepare T0 and T1 for a memory + alu operation. 1184 s_ext decides if the operand1 should be sign-extended or zero-extended when 1185 needed. */ 1186 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc, 1187 int s_ext, int memsize, TCGv dst, TCGv src) 1188 { 1189 int insn_len; 1190 1191 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src); 1192 tcg_gen_mov_tl(dst, cpu_R[dc->op2]); 1193 return insn_len; 1194 } 1195 1196 #if DISAS_CRIS 1197 static const char *cc_name(int cc) 1198 { 1199 static const char * const cc_names[16] = { 1200 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi", 1201 "ls", "hi", "ge", "lt", "gt", "le", "a", "p" 1202 }; 1203 assert(cc < 16); 1204 return cc_names[cc]; 1205 } 1206 #endif 1207 1208 /* Start of insn decoders. */ 1209 1210 static int dec_bccq(CPUCRISState *env, DisasContext *dc) 1211 { 1212 int32_t offset; 1213 int sign; 1214 uint32_t cond = dc->op2; 1215 1216 offset = EXTRACT_FIELD(dc->ir, 1, 7); 1217 sign = EXTRACT_FIELD(dc->ir, 0, 0); 1218 1219 offset *= 2; 1220 offset |= sign << 8; 1221 offset = sign_extend(offset, 8); 1222 1223 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset); 1224 1225 /* op2 holds the condition-code. */ 1226 cris_cc_mask(dc, 0); 1227 cris_prepare_cc_branch(dc, offset, cond); 1228 return 2; 1229 } 1230 static int dec_addoq(CPUCRISState *env, DisasContext *dc) 1231 { 1232 int32_t imm; 1233 1234 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7); 1235 imm = sign_extend(dc->op1, 7); 1236 1237 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2); 1238 cris_cc_mask(dc, 0); 1239 /* Fetch register operand, */ 1240 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm); 1241 1242 return 2; 1243 } 1244 static int dec_addq(CPUCRISState *env, DisasContext *dc) 1245 { 1246 TCGv c; 1247 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2); 1248 1249 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1250 1251 cris_cc_mask(dc, CC_MASK_NZVC); 1252 1253 c = tcg_const_tl(dc->op1); 1254 cris_alu(dc, CC_OP_ADD, 1255 cpu_R[dc->op2], cpu_R[dc->op2], c, 4); 1256 return 2; 1257 } 1258 static int dec_moveq(CPUCRISState *env, DisasContext *dc) 1259 { 1260 uint32_t imm; 1261 1262 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1263 imm = sign_extend(dc->op1, 5); 1264 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2); 1265 1266 tcg_gen_movi_tl(cpu_R[dc->op2], imm); 1267 return 2; 1268 } 1269 static int dec_subq(CPUCRISState *env, DisasContext *dc) 1270 { 1271 TCGv c; 1272 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1273 1274 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2); 1275 1276 cris_cc_mask(dc, CC_MASK_NZVC); 1277 c = tcg_const_tl(dc->op1); 1278 cris_alu(dc, CC_OP_SUB, 1279 cpu_R[dc->op2], cpu_R[dc->op2], c, 4); 1280 return 2; 1281 } 1282 static int dec_cmpq(CPUCRISState *env, DisasContext *dc) 1283 { 1284 uint32_t imm; 1285 TCGv c; 1286 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1287 imm = sign_extend(dc->op1, 5); 1288 1289 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2); 1290 cris_cc_mask(dc, CC_MASK_NZVC); 1291 1292 c = tcg_const_tl(imm); 1293 cris_alu(dc, CC_OP_CMP, 1294 cpu_R[dc->op2], cpu_R[dc->op2], c, 4); 1295 return 2; 1296 } 1297 static int dec_andq(CPUCRISState *env, DisasContext *dc) 1298 { 1299 uint32_t imm; 1300 TCGv c; 1301 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1302 imm = sign_extend(dc->op1, 5); 1303 1304 LOG_DIS("andq %d, $r%d\n", imm, dc->op2); 1305 cris_cc_mask(dc, CC_MASK_NZ); 1306 1307 c = tcg_const_tl(imm); 1308 cris_alu(dc, CC_OP_AND, 1309 cpu_R[dc->op2], cpu_R[dc->op2], c, 4); 1310 return 2; 1311 } 1312 static int dec_orq(CPUCRISState *env, DisasContext *dc) 1313 { 1314 uint32_t imm; 1315 TCGv c; 1316 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); 1317 imm = sign_extend(dc->op1, 5); 1318 LOG_DIS("orq %d, $r%d\n", imm, dc->op2); 1319 cris_cc_mask(dc, CC_MASK_NZ); 1320 1321 c = tcg_const_tl(imm); 1322 cris_alu(dc, CC_OP_OR, 1323 cpu_R[dc->op2], cpu_R[dc->op2], c, 4); 1324 return 2; 1325 } 1326 static int dec_btstq(CPUCRISState *env, DisasContext *dc) 1327 { 1328 TCGv c; 1329 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1330 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2); 1331 1332 cris_cc_mask(dc, CC_MASK_NZ); 1333 c = tcg_const_tl(dc->op1); 1334 cris_evaluate_flags(dc); 1335 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], 1336 c, cpu_PR[PR_CCS]); 1337 cris_alu(dc, CC_OP_MOVE, 1338 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); 1339 cris_update_cc_op(dc, CC_OP_FLAGS, 4); 1340 dc->flags_uptodate = 1; 1341 return 2; 1342 } 1343 static int dec_asrq(CPUCRISState *env, DisasContext *dc) 1344 { 1345 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1346 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2); 1347 cris_cc_mask(dc, CC_MASK_NZ); 1348 1349 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); 1350 cris_alu(dc, CC_OP_MOVE, 1351 cpu_R[dc->op2], 1352 cpu_R[dc->op2], cpu_R[dc->op2], 4); 1353 return 2; 1354 } 1355 static int dec_lslq(CPUCRISState *env, DisasContext *dc) 1356 { 1357 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1358 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2); 1359 1360 cris_cc_mask(dc, CC_MASK_NZ); 1361 1362 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); 1363 1364 cris_alu(dc, CC_OP_MOVE, 1365 cpu_R[dc->op2], 1366 cpu_R[dc->op2], cpu_R[dc->op2], 4); 1367 return 2; 1368 } 1369 static int dec_lsrq(CPUCRISState *env, DisasContext *dc) 1370 { 1371 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); 1372 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2); 1373 1374 cris_cc_mask(dc, CC_MASK_NZ); 1375 1376 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); 1377 cris_alu(dc, CC_OP_MOVE, 1378 cpu_R[dc->op2], 1379 cpu_R[dc->op2], cpu_R[dc->op2], 4); 1380 return 2; 1381 } 1382 1383 static int dec_move_r(CPUCRISState *env, DisasContext *dc) 1384 { 1385 int size = memsize_zz(dc); 1386 1387 LOG_DIS("move.%c $r%u, $r%u\n", 1388 memsize_char(size), dc->op1, dc->op2); 1389 1390 cris_cc_mask(dc, CC_MASK_NZ); 1391 if (size == 4) { 1392 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]); 1393 cris_cc_mask(dc, CC_MASK_NZ); 1394 cris_update_cc_op(dc, CC_OP_MOVE, 4); 1395 cris_update_cc_x(dc); 1396 cris_update_result(dc, cpu_R[dc->op2]); 1397 } else { 1398 TCGv t0; 1399 1400 t0 = tcg_temp_new(); 1401 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); 1402 cris_alu(dc, CC_OP_MOVE, 1403 cpu_R[dc->op2], 1404 cpu_R[dc->op2], t0, size); 1405 } 1406 return 2; 1407 } 1408 1409 static int dec_scc_r(CPUCRISState *env, DisasContext *dc) 1410 { 1411 int cond = dc->op2; 1412 1413 LOG_DIS("s%s $r%u\n", 1414 cc_name(cond), dc->op1); 1415 1416 gen_tst_cc(dc, cpu_R[dc->op1], cond); 1417 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->op1], cpu_R[dc->op1], 0); 1418 1419 cris_cc_mask(dc, 0); 1420 return 2; 1421 } 1422 1423 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t) 1424 { 1425 if (size == 4) { 1426 t[0] = cpu_R[dc->op2]; 1427 t[1] = cpu_R[dc->op1]; 1428 } else { 1429 t[0] = tcg_temp_new(); 1430 t[1] = tcg_temp_new(); 1431 } 1432 } 1433 1434 static int dec_and_r(CPUCRISState *env, DisasContext *dc) 1435 { 1436 TCGv t[2]; 1437 int size = memsize_zz(dc); 1438 1439 LOG_DIS("and.%c $r%u, $r%u\n", 1440 memsize_char(size), dc->op1, dc->op2); 1441 1442 cris_cc_mask(dc, CC_MASK_NZ); 1443 1444 cris_alu_alloc_temps(dc, size, t); 1445 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1446 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size); 1447 return 2; 1448 } 1449 1450 static int dec_lz_r(CPUCRISState *env, DisasContext *dc) 1451 { 1452 TCGv t0; 1453 LOG_DIS("lz $r%u, $r%u\n", 1454 dc->op1, dc->op2); 1455 cris_cc_mask(dc, CC_MASK_NZ); 1456 t0 = tcg_temp_new(); 1457 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0); 1458 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1459 return 2; 1460 } 1461 1462 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc) 1463 { 1464 TCGv t[2]; 1465 int size = memsize_zz(dc); 1466 1467 LOG_DIS("lsl.%c $r%u, $r%u\n", 1468 memsize_char(size), dc->op1, dc->op2); 1469 1470 cris_cc_mask(dc, CC_MASK_NZ); 1471 cris_alu_alloc_temps(dc, size, t); 1472 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1473 tcg_gen_andi_tl(t[1], t[1], 63); 1474 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size); 1475 return 2; 1476 } 1477 1478 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc) 1479 { 1480 TCGv t[2]; 1481 int size = memsize_zz(dc); 1482 1483 LOG_DIS("lsr.%c $r%u, $r%u\n", 1484 memsize_char(size), dc->op1, dc->op2); 1485 1486 cris_cc_mask(dc, CC_MASK_NZ); 1487 cris_alu_alloc_temps(dc, size, t); 1488 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1489 tcg_gen_andi_tl(t[1], t[1], 63); 1490 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size); 1491 return 2; 1492 } 1493 1494 static int dec_asr_r(CPUCRISState *env, DisasContext *dc) 1495 { 1496 TCGv t[2]; 1497 int size = memsize_zz(dc); 1498 1499 LOG_DIS("asr.%c $r%u, $r%u\n", 1500 memsize_char(size), dc->op1, dc->op2); 1501 1502 cris_cc_mask(dc, CC_MASK_NZ); 1503 cris_alu_alloc_temps(dc, size, t); 1504 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); 1505 tcg_gen_andi_tl(t[1], t[1], 63); 1506 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size); 1507 return 2; 1508 } 1509 1510 static int dec_muls_r(CPUCRISState *env, DisasContext *dc) 1511 { 1512 TCGv t[2]; 1513 int size = memsize_zz(dc); 1514 1515 LOG_DIS("muls.%c $r%u, $r%u\n", 1516 memsize_char(size), dc->op1, dc->op2); 1517 cris_cc_mask(dc, CC_MASK_NZV); 1518 cris_alu_alloc_temps(dc, size, t); 1519 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); 1520 1521 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4); 1522 return 2; 1523 } 1524 1525 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc) 1526 { 1527 TCGv t[2]; 1528 int size = memsize_zz(dc); 1529 1530 LOG_DIS("mulu.%c $r%u, $r%u\n", 1531 memsize_char(size), dc->op1, dc->op2); 1532 cris_cc_mask(dc, CC_MASK_NZV); 1533 cris_alu_alloc_temps(dc, size, t); 1534 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1535 1536 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4); 1537 return 2; 1538 } 1539 1540 1541 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc) 1542 { 1543 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2); 1544 cris_cc_mask(dc, CC_MASK_NZ); 1545 cris_alu(dc, CC_OP_DSTEP, 1546 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); 1547 return 2; 1548 } 1549 1550 static int dec_xor_r(CPUCRISState *env, DisasContext *dc) 1551 { 1552 TCGv t[2]; 1553 int size = memsize_zz(dc); 1554 LOG_DIS("xor.%c $r%u, $r%u\n", 1555 memsize_char(size), dc->op1, dc->op2); 1556 BUG_ON(size != 4); /* xor is dword. */ 1557 cris_cc_mask(dc, CC_MASK_NZ); 1558 cris_alu_alloc_temps(dc, size, t); 1559 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1560 1561 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4); 1562 return 2; 1563 } 1564 1565 static int dec_bound_r(CPUCRISState *env, DisasContext *dc) 1566 { 1567 TCGv l0; 1568 int size = memsize_zz(dc); 1569 LOG_DIS("bound.%c $r%u, $r%u\n", 1570 memsize_char(size), dc->op1, dc->op2); 1571 cris_cc_mask(dc, CC_MASK_NZ); 1572 l0 = tcg_temp_new(); 1573 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0); 1574 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4); 1575 return 2; 1576 } 1577 1578 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc) 1579 { 1580 TCGv t[2]; 1581 int size = memsize_zz(dc); 1582 LOG_DIS("cmp.%c $r%u, $r%u\n", 1583 memsize_char(size), dc->op1, dc->op2); 1584 cris_cc_mask(dc, CC_MASK_NZVC); 1585 cris_alu_alloc_temps(dc, size, t); 1586 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1587 1588 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size); 1589 return 2; 1590 } 1591 1592 static int dec_abs_r(CPUCRISState *env, DisasContext *dc) 1593 { 1594 LOG_DIS("abs $r%u, $r%u\n", 1595 dc->op1, dc->op2); 1596 cris_cc_mask(dc, CC_MASK_NZ); 1597 1598 tcg_gen_abs_tl(cpu_R[dc->op2], cpu_R[dc->op1]); 1599 cris_alu(dc, CC_OP_MOVE, 1600 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); 1601 return 2; 1602 } 1603 1604 static int dec_add_r(CPUCRISState *env, DisasContext *dc) 1605 { 1606 TCGv t[2]; 1607 int size = memsize_zz(dc); 1608 LOG_DIS("add.%c $r%u, $r%u\n", 1609 memsize_char(size), dc->op1, dc->op2); 1610 cris_cc_mask(dc, CC_MASK_NZVC); 1611 cris_alu_alloc_temps(dc, size, t); 1612 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1613 1614 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size); 1615 return 2; 1616 } 1617 1618 static int dec_addc_r(CPUCRISState *env, DisasContext *dc) 1619 { 1620 LOG_DIS("addc $r%u, $r%u\n", 1621 dc->op1, dc->op2); 1622 cris_evaluate_flags(dc); 1623 1624 /* Set for this insn. */ 1625 dc->flags_x = X_FLAG; 1626 1627 cris_cc_mask(dc, CC_MASK_NZVC); 1628 cris_alu(dc, CC_OP_ADDC, 1629 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); 1630 return 2; 1631 } 1632 1633 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc) 1634 { 1635 LOG_DIS("mcp $p%u, $r%u\n", 1636 dc->op2, dc->op1); 1637 cris_evaluate_flags(dc); 1638 cris_cc_mask(dc, CC_MASK_RNZV); 1639 cris_alu(dc, CC_OP_MCP, 1640 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4); 1641 return 2; 1642 } 1643 1644 #if DISAS_CRIS 1645 static char * swapmode_name(int mode, char *modename) { 1646 int i = 0; 1647 if (mode & 8) { 1648 modename[i++] = 'n'; 1649 } 1650 if (mode & 4) { 1651 modename[i++] = 'w'; 1652 } 1653 if (mode & 2) { 1654 modename[i++] = 'b'; 1655 } 1656 if (mode & 1) { 1657 modename[i++] = 'r'; 1658 } 1659 modename[i++] = 0; 1660 return modename; 1661 } 1662 #endif 1663 1664 static int dec_swap_r(CPUCRISState *env, DisasContext *dc) 1665 { 1666 TCGv t0; 1667 #if DISAS_CRIS 1668 char modename[4]; 1669 #endif 1670 LOG_DIS("swap%s $r%u\n", 1671 swapmode_name(dc->op2, modename), dc->op1); 1672 1673 cris_cc_mask(dc, CC_MASK_NZ); 1674 t0 = tcg_temp_new(); 1675 tcg_gen_mov_tl(t0, cpu_R[dc->op1]); 1676 if (dc->op2 & 8) { 1677 tcg_gen_not_tl(t0, t0); 1678 } 1679 if (dc->op2 & 4) { 1680 t_gen_swapw(t0, t0); 1681 } 1682 if (dc->op2 & 2) { 1683 t_gen_swapb(t0, t0); 1684 } 1685 if (dc->op2 & 1) { 1686 t_gen_swapr(t0, t0); 1687 } 1688 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4); 1689 return 2; 1690 } 1691 1692 static int dec_or_r(CPUCRISState *env, DisasContext *dc) 1693 { 1694 TCGv t[2]; 1695 int size = memsize_zz(dc); 1696 LOG_DIS("or.%c $r%u, $r%u\n", 1697 memsize_char(size), dc->op1, dc->op2); 1698 cris_cc_mask(dc, CC_MASK_NZ); 1699 cris_alu_alloc_temps(dc, size, t); 1700 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1701 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size); 1702 return 2; 1703 } 1704 1705 static int dec_addi_r(CPUCRISState *env, DisasContext *dc) 1706 { 1707 TCGv t0; 1708 LOG_DIS("addi.%c $r%u, $r%u\n", 1709 memsize_char(memsize_zz(dc)), dc->op2, dc->op1); 1710 cris_cc_mask(dc, 0); 1711 t0 = tcg_temp_new(); 1712 tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize); 1713 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0); 1714 return 2; 1715 } 1716 1717 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc) 1718 { 1719 TCGv t0; 1720 LOG_DIS("addi.%c $r%u, $r%u, $acr\n", 1721 memsize_char(memsize_zz(dc)), dc->op2, dc->op1); 1722 cris_cc_mask(dc, 0); 1723 t0 = tcg_temp_new(); 1724 tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize); 1725 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0); 1726 return 2; 1727 } 1728 1729 static int dec_neg_r(CPUCRISState *env, DisasContext *dc) 1730 { 1731 TCGv t[2]; 1732 int size = memsize_zz(dc); 1733 LOG_DIS("neg.%c $r%u, $r%u\n", 1734 memsize_char(size), dc->op1, dc->op2); 1735 cris_cc_mask(dc, CC_MASK_NZVC); 1736 cris_alu_alloc_temps(dc, size, t); 1737 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1738 1739 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size); 1740 return 2; 1741 } 1742 1743 static int dec_btst_r(CPUCRISState *env, DisasContext *dc) 1744 { 1745 LOG_DIS("btst $r%u, $r%u\n", 1746 dc->op1, dc->op2); 1747 cris_cc_mask(dc, CC_MASK_NZ); 1748 cris_evaluate_flags(dc); 1749 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], 1750 cpu_R[dc->op1], cpu_PR[PR_CCS]); 1751 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], 1752 cpu_R[dc->op2], cpu_R[dc->op2], 4); 1753 cris_update_cc_op(dc, CC_OP_FLAGS, 4); 1754 dc->flags_uptodate = 1; 1755 return 2; 1756 } 1757 1758 static int dec_sub_r(CPUCRISState *env, DisasContext *dc) 1759 { 1760 TCGv t[2]; 1761 int size = memsize_zz(dc); 1762 LOG_DIS("sub.%c $r%u, $r%u\n", 1763 memsize_char(size), dc->op1, dc->op2); 1764 cris_cc_mask(dc, CC_MASK_NZVC); 1765 cris_alu_alloc_temps(dc, size, t); 1766 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); 1767 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size); 1768 return 2; 1769 } 1770 1771 /* Zero extension. From size to dword. */ 1772 static int dec_movu_r(CPUCRISState *env, DisasContext *dc) 1773 { 1774 TCGv t0; 1775 int size = memsize_z(dc); 1776 LOG_DIS("movu.%c $r%u, $r%u\n", 1777 memsize_char(size), 1778 dc->op1, dc->op2); 1779 1780 cris_cc_mask(dc, CC_MASK_NZ); 1781 t0 = tcg_temp_new(); 1782 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); 1783 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1784 return 2; 1785 } 1786 1787 /* Sign extension. From size to dword. */ 1788 static int dec_movs_r(CPUCRISState *env, DisasContext *dc) 1789 { 1790 TCGv t0; 1791 int size = memsize_z(dc); 1792 LOG_DIS("movs.%c $r%u, $r%u\n", 1793 memsize_char(size), 1794 dc->op1, dc->op2); 1795 1796 cris_cc_mask(dc, CC_MASK_NZ); 1797 t0 = tcg_temp_new(); 1798 /* Size can only be qi or hi. */ 1799 t_gen_sext(t0, cpu_R[dc->op1], size); 1800 cris_alu(dc, CC_OP_MOVE, 1801 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4); 1802 return 2; 1803 } 1804 1805 /* zero extension. From size to dword. */ 1806 static int dec_addu_r(CPUCRISState *env, DisasContext *dc) 1807 { 1808 TCGv t0; 1809 int size = memsize_z(dc); 1810 LOG_DIS("addu.%c $r%u, $r%u\n", 1811 memsize_char(size), 1812 dc->op1, dc->op2); 1813 1814 cris_cc_mask(dc, CC_MASK_NZVC); 1815 t0 = tcg_temp_new(); 1816 /* Size can only be qi or hi. */ 1817 t_gen_zext(t0, cpu_R[dc->op1], size); 1818 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1819 return 2; 1820 } 1821 1822 /* Sign extension. From size to dword. */ 1823 static int dec_adds_r(CPUCRISState *env, DisasContext *dc) 1824 { 1825 TCGv t0; 1826 int size = memsize_z(dc); 1827 LOG_DIS("adds.%c $r%u, $r%u\n", 1828 memsize_char(size), 1829 dc->op1, dc->op2); 1830 1831 cris_cc_mask(dc, CC_MASK_NZVC); 1832 t0 = tcg_temp_new(); 1833 /* Size can only be qi or hi. */ 1834 t_gen_sext(t0, cpu_R[dc->op1], size); 1835 cris_alu(dc, CC_OP_ADD, 1836 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1837 return 2; 1838 } 1839 1840 /* Zero extension. From size to dword. */ 1841 static int dec_subu_r(CPUCRISState *env, DisasContext *dc) 1842 { 1843 TCGv t0; 1844 int size = memsize_z(dc); 1845 LOG_DIS("subu.%c $r%u, $r%u\n", 1846 memsize_char(size), 1847 dc->op1, dc->op2); 1848 1849 cris_cc_mask(dc, CC_MASK_NZVC); 1850 t0 = tcg_temp_new(); 1851 /* Size can only be qi or hi. */ 1852 t_gen_zext(t0, cpu_R[dc->op1], size); 1853 cris_alu(dc, CC_OP_SUB, 1854 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1855 return 2; 1856 } 1857 1858 /* Sign extension. From size to dword. */ 1859 static int dec_subs_r(CPUCRISState *env, DisasContext *dc) 1860 { 1861 TCGv t0; 1862 int size = memsize_z(dc); 1863 LOG_DIS("subs.%c $r%u, $r%u\n", 1864 memsize_char(size), 1865 dc->op1, dc->op2); 1866 1867 cris_cc_mask(dc, CC_MASK_NZVC); 1868 t0 = tcg_temp_new(); 1869 /* Size can only be qi or hi. */ 1870 t_gen_sext(t0, cpu_R[dc->op1], size); 1871 cris_alu(dc, CC_OP_SUB, 1872 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); 1873 return 2; 1874 } 1875 1876 static int dec_setclrf(CPUCRISState *env, DisasContext *dc) 1877 { 1878 uint32_t flags; 1879 int set = (~dc->opcode >> 2) & 1; 1880 1881 1882 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4) 1883 | EXTRACT_FIELD(dc->ir, 0, 3); 1884 if (set && flags == 0) { 1885 LOG_DIS("nop\n"); 1886 return 2; 1887 } else if (!set && (flags & 0x20)) { 1888 LOG_DIS("di\n"); 1889 } else { 1890 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags); 1891 } 1892 1893 /* User space is not allowed to touch these. Silently ignore. */ 1894 if (dc->tb_flags & U_FLAG) { 1895 flags &= ~(S_FLAG | I_FLAG | U_FLAG); 1896 } 1897 1898 if (flags & X_FLAG) { 1899 if (set) { 1900 dc->flags_x = X_FLAG; 1901 } else { 1902 dc->flags_x = 0; 1903 } 1904 } 1905 1906 /* Break the TB if any of the SPI flag changes. */ 1907 if (flags & (P_FLAG | S_FLAG)) { 1908 tcg_gen_movi_tl(env_pc, dc->pc + 2); 1909 dc->base.is_jmp = DISAS_UPDATE; 1910 dc->cpustate_changed = 1; 1911 } 1912 1913 /* For the I flag, only act on posedge. */ 1914 if ((flags & I_FLAG)) { 1915 tcg_gen_movi_tl(env_pc, dc->pc + 2); 1916 dc->base.is_jmp = DISAS_UPDATE; 1917 dc->cpustate_changed = 1; 1918 } 1919 1920 1921 /* Simply decode the flags. */ 1922 cris_evaluate_flags(dc); 1923 cris_update_cc_op(dc, CC_OP_FLAGS, 4); 1924 cris_update_cc_x(dc); 1925 tcg_gen_movi_tl(cc_op, dc->cc_op); 1926 1927 if (set) { 1928 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) { 1929 /* Enter user mode. */ 1930 t_gen_mov_env_TN(ksp, cpu_R[R_SP]); 1931 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]); 1932 dc->cpustate_changed = 1; 1933 } 1934 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags); 1935 } else { 1936 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags); 1937 } 1938 1939 dc->flags_uptodate = 1; 1940 dc->clear_x = 0; 1941 return 2; 1942 } 1943 1944 static int dec_move_rs(CPUCRISState *env, DisasContext *dc) 1945 { 1946 TCGv c2, c1; 1947 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2); 1948 c1 = tcg_const_tl(dc->op1); 1949 c2 = tcg_const_tl(dc->op2); 1950 cris_cc_mask(dc, 0); 1951 gen_helper_movl_sreg_reg(cpu_env, c2, c1); 1952 return 2; 1953 } 1954 static int dec_move_sr(CPUCRISState *env, DisasContext *dc) 1955 { 1956 TCGv c2, c1; 1957 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1); 1958 c1 = tcg_const_tl(dc->op1); 1959 c2 = tcg_const_tl(dc->op2); 1960 cris_cc_mask(dc, 0); 1961 gen_helper_movl_reg_sreg(cpu_env, c1, c2); 1962 return 2; 1963 } 1964 1965 static int dec_move_rp(CPUCRISState *env, DisasContext *dc) 1966 { 1967 TCGv t[2]; 1968 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2); 1969 cris_cc_mask(dc, 0); 1970 1971 t[0] = tcg_temp_new(); 1972 if (dc->op2 == PR_CCS) { 1973 cris_evaluate_flags(dc); 1974 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]); 1975 if (dc->tb_flags & U_FLAG) { 1976 t[1] = tcg_temp_new(); 1977 /* User space is not allowed to touch all flags. */ 1978 tcg_gen_andi_tl(t[0], t[0], 0x39f); 1979 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f); 1980 tcg_gen_or_tl(t[0], t[1], t[0]); 1981 } 1982 } else { 1983 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]); 1984 } 1985 1986 t_gen_mov_preg_TN(dc, dc->op2, t[0]); 1987 if (dc->op2 == PR_CCS) { 1988 cris_update_cc_op(dc, CC_OP_FLAGS, 4); 1989 dc->flags_uptodate = 1; 1990 } 1991 return 2; 1992 } 1993 static int dec_move_pr(CPUCRISState *env, DisasContext *dc) 1994 { 1995 TCGv t0; 1996 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1); 1997 cris_cc_mask(dc, 0); 1998 1999 if (dc->op2 == PR_CCS) { 2000 cris_evaluate_flags(dc); 2001 } 2002 2003 if (dc->op2 == PR_DZ) { 2004 tcg_gen_movi_tl(cpu_R[dc->op1], 0); 2005 } else { 2006 t0 = tcg_temp_new(); 2007 t_gen_mov_TN_preg(t0, dc->op2); 2008 cris_alu(dc, CC_OP_MOVE, 2009 cpu_R[dc->op1], cpu_R[dc->op1], t0, 2010 preg_sizes[dc->op2]); 2011 } 2012 return 2; 2013 } 2014 2015 static int dec_move_mr(CPUCRISState *env, DisasContext *dc) 2016 { 2017 int memsize = memsize_zz(dc); 2018 int insn_len; 2019 LOG_DIS("move.%c [$r%u%s, $r%u\n", 2020 memsize_char(memsize), 2021 dc->op1, dc->postinc ? "+]" : "]", 2022 dc->op2); 2023 2024 if (memsize == 4) { 2025 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]); 2026 cris_cc_mask(dc, CC_MASK_NZ); 2027 cris_update_cc_op(dc, CC_OP_MOVE, 4); 2028 cris_update_cc_x(dc); 2029 cris_update_result(dc, cpu_R[dc->op2]); 2030 } else { 2031 TCGv t0; 2032 2033 t0 = tcg_temp_new(); 2034 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0); 2035 cris_cc_mask(dc, CC_MASK_NZ); 2036 cris_alu(dc, CC_OP_MOVE, 2037 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize); 2038 } 2039 do_postinc(dc, memsize); 2040 return insn_len; 2041 } 2042 2043 static inline void cris_alu_m_alloc_temps(TCGv *t) 2044 { 2045 t[0] = tcg_temp_new(); 2046 t[1] = tcg_temp_new(); 2047 } 2048 2049 static int dec_movs_m(CPUCRISState *env, DisasContext *dc) 2050 { 2051 TCGv t[2]; 2052 int memsize = memsize_z(dc); 2053 int insn_len; 2054 LOG_DIS("movs.%c [$r%u%s, $r%u\n", 2055 memsize_char(memsize), 2056 dc->op1, dc->postinc ? "+]" : "]", 2057 dc->op2); 2058 2059 cris_alu_m_alloc_temps(t); 2060 /* sign extend. */ 2061 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); 2062 cris_cc_mask(dc, CC_MASK_NZ); 2063 cris_alu(dc, CC_OP_MOVE, 2064 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2065 do_postinc(dc, memsize); 2066 return insn_len; 2067 } 2068 2069 static int dec_addu_m(CPUCRISState *env, DisasContext *dc) 2070 { 2071 TCGv t[2]; 2072 int memsize = memsize_z(dc); 2073 int insn_len; 2074 LOG_DIS("addu.%c [$r%u%s, $r%u\n", 2075 memsize_char(memsize), 2076 dc->op1, dc->postinc ? "+]" : "]", 2077 dc->op2); 2078 2079 cris_alu_m_alloc_temps(t); 2080 /* sign extend. */ 2081 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2082 cris_cc_mask(dc, CC_MASK_NZVC); 2083 cris_alu(dc, CC_OP_ADD, 2084 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2085 do_postinc(dc, memsize); 2086 return insn_len; 2087 } 2088 2089 static int dec_adds_m(CPUCRISState *env, DisasContext *dc) 2090 { 2091 TCGv t[2]; 2092 int memsize = memsize_z(dc); 2093 int insn_len; 2094 LOG_DIS("adds.%c [$r%u%s, $r%u\n", 2095 memsize_char(memsize), 2096 dc->op1, dc->postinc ? "+]" : "]", 2097 dc->op2); 2098 2099 cris_alu_m_alloc_temps(t); 2100 /* sign extend. */ 2101 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); 2102 cris_cc_mask(dc, CC_MASK_NZVC); 2103 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2104 do_postinc(dc, memsize); 2105 return insn_len; 2106 } 2107 2108 static int dec_subu_m(CPUCRISState *env, DisasContext *dc) 2109 { 2110 TCGv t[2]; 2111 int memsize = memsize_z(dc); 2112 int insn_len; 2113 LOG_DIS("subu.%c [$r%u%s, $r%u\n", 2114 memsize_char(memsize), 2115 dc->op1, dc->postinc ? "+]" : "]", 2116 dc->op2); 2117 2118 cris_alu_m_alloc_temps(t); 2119 /* sign extend. */ 2120 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2121 cris_cc_mask(dc, CC_MASK_NZVC); 2122 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2123 do_postinc(dc, memsize); 2124 return insn_len; 2125 } 2126 2127 static int dec_subs_m(CPUCRISState *env, DisasContext *dc) 2128 { 2129 TCGv t[2]; 2130 int memsize = memsize_z(dc); 2131 int insn_len; 2132 LOG_DIS("subs.%c [$r%u%s, $r%u\n", 2133 memsize_char(memsize), 2134 dc->op1, dc->postinc ? "+]" : "]", 2135 dc->op2); 2136 2137 cris_alu_m_alloc_temps(t); 2138 /* sign extend. */ 2139 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); 2140 cris_cc_mask(dc, CC_MASK_NZVC); 2141 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2142 do_postinc(dc, memsize); 2143 return insn_len; 2144 } 2145 2146 static int dec_movu_m(CPUCRISState *env, DisasContext *dc) 2147 { 2148 TCGv t[2]; 2149 int memsize = memsize_z(dc); 2150 int insn_len; 2151 2152 LOG_DIS("movu.%c [$r%u%s, $r%u\n", 2153 memsize_char(memsize), 2154 dc->op1, dc->postinc ? "+]" : "]", 2155 dc->op2); 2156 2157 cris_alu_m_alloc_temps(t); 2158 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2159 cris_cc_mask(dc, CC_MASK_NZ); 2160 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2161 do_postinc(dc, memsize); 2162 return insn_len; 2163 } 2164 2165 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc) 2166 { 2167 TCGv t[2]; 2168 int memsize = memsize_z(dc); 2169 int insn_len; 2170 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n", 2171 memsize_char(memsize), 2172 dc->op1, dc->postinc ? "+]" : "]", 2173 dc->op2); 2174 2175 cris_alu_m_alloc_temps(t); 2176 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2177 cris_cc_mask(dc, CC_MASK_NZVC); 2178 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); 2179 do_postinc(dc, memsize); 2180 return insn_len; 2181 } 2182 2183 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc) 2184 { 2185 TCGv t[2]; 2186 int memsize = memsize_z(dc); 2187 int insn_len; 2188 LOG_DIS("cmps.%c [$r%u%s, $r%u\n", 2189 memsize_char(memsize), 2190 dc->op1, dc->postinc ? "+]" : "]", 2191 dc->op2); 2192 2193 cris_alu_m_alloc_temps(t); 2194 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); 2195 cris_cc_mask(dc, CC_MASK_NZVC); 2196 cris_alu(dc, CC_OP_CMP, 2197 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 2198 memsize_zz(dc)); 2199 do_postinc(dc, memsize); 2200 return insn_len; 2201 } 2202 2203 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc) 2204 { 2205 TCGv t[2]; 2206 int memsize = memsize_zz(dc); 2207 int insn_len; 2208 LOG_DIS("cmp.%c [$r%u%s, $r%u\n", 2209 memsize_char(memsize), 2210 dc->op1, dc->postinc ? "+]" : "]", 2211 dc->op2); 2212 2213 cris_alu_m_alloc_temps(t); 2214 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2215 cris_cc_mask(dc, CC_MASK_NZVC); 2216 cris_alu(dc, CC_OP_CMP, 2217 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 2218 memsize_zz(dc)); 2219 do_postinc(dc, memsize); 2220 return insn_len; 2221 } 2222 2223 static int dec_test_m(CPUCRISState *env, DisasContext *dc) 2224 { 2225 TCGv t[2], c; 2226 int memsize = memsize_zz(dc); 2227 int insn_len; 2228 LOG_DIS("test.%c [$r%u%s] op2=%x\n", 2229 memsize_char(memsize), 2230 dc->op1, dc->postinc ? "+]" : "]", 2231 dc->op2); 2232 2233 cris_evaluate_flags(dc); 2234 2235 cris_alu_m_alloc_temps(t); 2236 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2237 cris_cc_mask(dc, CC_MASK_NZ); 2238 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); 2239 2240 c = tcg_const_tl(0); 2241 cris_alu(dc, CC_OP_CMP, 2242 cpu_R[dc->op2], t[1], c, memsize_zz(dc)); 2243 do_postinc(dc, memsize); 2244 return insn_len; 2245 } 2246 2247 static int dec_and_m(CPUCRISState *env, DisasContext *dc) 2248 { 2249 TCGv t[2]; 2250 int memsize = memsize_zz(dc); 2251 int insn_len; 2252 LOG_DIS("and.%c [$r%u%s, $r%u\n", 2253 memsize_char(memsize), 2254 dc->op1, dc->postinc ? "+]" : "]", 2255 dc->op2); 2256 2257 cris_alu_m_alloc_temps(t); 2258 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2259 cris_cc_mask(dc, CC_MASK_NZ); 2260 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); 2261 do_postinc(dc, memsize); 2262 return insn_len; 2263 } 2264 2265 static int dec_add_m(CPUCRISState *env, DisasContext *dc) 2266 { 2267 TCGv t[2]; 2268 int memsize = memsize_zz(dc); 2269 int insn_len; 2270 LOG_DIS("add.%c [$r%u%s, $r%u\n", 2271 memsize_char(memsize), 2272 dc->op1, dc->postinc ? "+]" : "]", 2273 dc->op2); 2274 2275 cris_alu_m_alloc_temps(t); 2276 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2277 cris_cc_mask(dc, CC_MASK_NZVC); 2278 cris_alu(dc, CC_OP_ADD, 2279 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); 2280 do_postinc(dc, memsize); 2281 return insn_len; 2282 } 2283 2284 static int dec_addo_m(CPUCRISState *env, DisasContext *dc) 2285 { 2286 TCGv t[2]; 2287 int memsize = memsize_zz(dc); 2288 int insn_len; 2289 LOG_DIS("add.%c [$r%u%s, $r%u\n", 2290 memsize_char(memsize), 2291 dc->op1, dc->postinc ? "+]" : "]", 2292 dc->op2); 2293 2294 cris_alu_m_alloc_temps(t); 2295 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); 2296 cris_cc_mask(dc, 0); 2297 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4); 2298 do_postinc(dc, memsize); 2299 return insn_len; 2300 } 2301 2302 static int dec_bound_m(CPUCRISState *env, DisasContext *dc) 2303 { 2304 TCGv l[2]; 2305 int memsize = memsize_zz(dc); 2306 int insn_len; 2307 LOG_DIS("bound.%c [$r%u%s, $r%u\n", 2308 memsize_char(memsize), 2309 dc->op1, dc->postinc ? "+]" : "]", 2310 dc->op2); 2311 2312 l[0] = tcg_temp_new(); 2313 l[1] = tcg_temp_new(); 2314 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]); 2315 cris_cc_mask(dc, CC_MASK_NZ); 2316 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4); 2317 do_postinc(dc, memsize); 2318 return insn_len; 2319 } 2320 2321 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc) 2322 { 2323 TCGv t[2]; 2324 int insn_len = 2; 2325 LOG_DIS("addc [$r%u%s, $r%u\n", 2326 dc->op1, dc->postinc ? "+]" : "]", 2327 dc->op2); 2328 2329 cris_evaluate_flags(dc); 2330 2331 /* Set for this insn. */ 2332 dc->flags_x = X_FLAG; 2333 2334 cris_alu_m_alloc_temps(t); 2335 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]); 2336 cris_cc_mask(dc, CC_MASK_NZVC); 2337 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4); 2338 do_postinc(dc, 4); 2339 return insn_len; 2340 } 2341 2342 static int dec_sub_m(CPUCRISState *env, DisasContext *dc) 2343 { 2344 TCGv t[2]; 2345 int memsize = memsize_zz(dc); 2346 int insn_len; 2347 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n", 2348 memsize_char(memsize), 2349 dc->op1, dc->postinc ? "+]" : "]", 2350 dc->op2, dc->ir, dc->zzsize); 2351 2352 cris_alu_m_alloc_temps(t); 2353 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2354 cris_cc_mask(dc, CC_MASK_NZVC); 2355 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize); 2356 do_postinc(dc, memsize); 2357 return insn_len; 2358 } 2359 2360 static int dec_or_m(CPUCRISState *env, DisasContext *dc) 2361 { 2362 TCGv t[2]; 2363 int memsize = memsize_zz(dc); 2364 int insn_len; 2365 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n", 2366 memsize_char(memsize), 2367 dc->op1, dc->postinc ? "+]" : "]", 2368 dc->op2, dc->pc); 2369 2370 cris_alu_m_alloc_temps(t); 2371 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2372 cris_cc_mask(dc, CC_MASK_NZ); 2373 cris_alu(dc, CC_OP_OR, 2374 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); 2375 do_postinc(dc, memsize); 2376 return insn_len; 2377 } 2378 2379 static int dec_move_mp(CPUCRISState *env, DisasContext *dc) 2380 { 2381 TCGv t[2]; 2382 int memsize = memsize_zz(dc); 2383 int insn_len = 2; 2384 2385 LOG_DIS("move.%c [$r%u%s, $p%u\n", 2386 memsize_char(memsize), 2387 dc->op1, 2388 dc->postinc ? "+]" : "]", 2389 dc->op2); 2390 2391 cris_alu_m_alloc_temps(t); 2392 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); 2393 cris_cc_mask(dc, 0); 2394 if (dc->op2 == PR_CCS) { 2395 cris_evaluate_flags(dc); 2396 if (dc->tb_flags & U_FLAG) { 2397 /* User space is not allowed to touch all flags. */ 2398 tcg_gen_andi_tl(t[1], t[1], 0x39f); 2399 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f); 2400 tcg_gen_or_tl(t[1], t[0], t[1]); 2401 } 2402 } 2403 2404 t_gen_mov_preg_TN(dc, dc->op2, t[1]); 2405 2406 do_postinc(dc, memsize); 2407 return insn_len; 2408 } 2409 2410 static int dec_move_pm(CPUCRISState *env, DisasContext *dc) 2411 { 2412 TCGv t0; 2413 int memsize; 2414 2415 memsize = preg_sizes[dc->op2]; 2416 2417 LOG_DIS("move.%c $p%u, [$r%u%s\n", 2418 memsize_char(memsize), 2419 dc->op2, dc->op1, dc->postinc ? "+]" : "]"); 2420 2421 /* prepare store. Address in T0, value in T1. */ 2422 if (dc->op2 == PR_CCS) { 2423 cris_evaluate_flags(dc); 2424 } 2425 t0 = tcg_temp_new(); 2426 t_gen_mov_TN_preg(t0, dc->op2); 2427 cris_flush_cc_state(dc); 2428 gen_store(dc, cpu_R[dc->op1], t0, memsize); 2429 2430 cris_cc_mask(dc, 0); 2431 if (dc->postinc) { 2432 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize); 2433 } 2434 return 2; 2435 } 2436 2437 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc) 2438 { 2439 TCGv_i64 tmp[16]; 2440 TCGv tmp32; 2441 TCGv addr; 2442 int i; 2443 int nr = dc->op2 + 1; 2444 2445 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1, 2446 dc->postinc ? "+]" : "]", dc->op2); 2447 2448 addr = tcg_temp_new(); 2449 /* There are probably better ways of doing this. */ 2450 cris_flush_cc_state(dc); 2451 for (i = 0; i < (nr >> 1); i++) { 2452 tmp[i] = tcg_temp_new_i64(); 2453 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); 2454 gen_load64(dc, tmp[i], addr); 2455 } 2456 if (nr & 1) { 2457 tmp32 = tcg_temp_new_i32(); 2458 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); 2459 gen_load(dc, tmp32, addr, 4, 0); 2460 } else { 2461 tmp32 = NULL; 2462 } 2463 2464 for (i = 0; i < (nr >> 1); i++) { 2465 tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]); 2466 tcg_gen_shri_i64(tmp[i], tmp[i], 32); 2467 tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]); 2468 } 2469 if (nr & 1) { 2470 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32); 2471 } 2472 2473 /* writeback the updated pointer value. */ 2474 if (dc->postinc) { 2475 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4); 2476 } 2477 2478 /* gen_load might want to evaluate the previous insns flags. */ 2479 cris_cc_mask(dc, 0); 2480 return 2; 2481 } 2482 2483 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc) 2484 { 2485 TCGv tmp; 2486 TCGv addr; 2487 int i; 2488 2489 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1, 2490 dc->postinc ? "+]" : "]"); 2491 2492 cris_flush_cc_state(dc); 2493 2494 tmp = tcg_temp_new(); 2495 addr = tcg_temp_new(); 2496 tcg_gen_movi_tl(tmp, 4); 2497 tcg_gen_mov_tl(addr, cpu_R[dc->op1]); 2498 for (i = 0; i <= dc->op2; i++) { 2499 /* Displace addr. */ 2500 /* Perform the store. */ 2501 gen_store(dc, addr, cpu_R[i], 4); 2502 tcg_gen_add_tl(addr, addr, tmp); 2503 } 2504 if (dc->postinc) { 2505 tcg_gen_mov_tl(cpu_R[dc->op1], addr); 2506 } 2507 cris_cc_mask(dc, 0); 2508 return 2; 2509 } 2510 2511 static int dec_move_rm(CPUCRISState *env, DisasContext *dc) 2512 { 2513 int memsize; 2514 2515 memsize = memsize_zz(dc); 2516 2517 LOG_DIS("move.%c $r%u, [$r%u]\n", 2518 memsize_char(memsize), dc->op2, dc->op1); 2519 2520 /* prepare store. */ 2521 cris_flush_cc_state(dc); 2522 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize); 2523 2524 if (dc->postinc) { 2525 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize); 2526 } 2527 cris_cc_mask(dc, 0); 2528 return 2; 2529 } 2530 2531 static int dec_lapcq(CPUCRISState *env, DisasContext *dc) 2532 { 2533 LOG_DIS("lapcq %x, $r%u\n", 2534 dc->pc + dc->op1*2, dc->op2); 2535 cris_cc_mask(dc, 0); 2536 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2); 2537 return 2; 2538 } 2539 2540 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc) 2541 { 2542 unsigned int rd; 2543 int32_t imm; 2544 int32_t pc; 2545 2546 rd = dc->op2; 2547 2548 cris_cc_mask(dc, 0); 2549 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); 2550 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2); 2551 2552 pc = dc->pc; 2553 pc += imm; 2554 tcg_gen_movi_tl(cpu_R[rd], pc); 2555 return 6; 2556 } 2557 2558 /* Jump to special reg. */ 2559 static int dec_jump_p(CPUCRISState *env, DisasContext *dc) 2560 { 2561 LOG_DIS("jump $p%u\n", dc->op2); 2562 2563 if (dc->op2 == PR_CCS) { 2564 cris_evaluate_flags(dc); 2565 } 2566 t_gen_mov_TN_preg(env_btarget, dc->op2); 2567 /* rete will often have low bit set to indicate delayslot. */ 2568 tcg_gen_andi_tl(env_btarget, env_btarget, ~1); 2569 cris_cc_mask(dc, 0); 2570 cris_prepare_jmp(dc, JMP_INDIRECT); 2571 return 2; 2572 } 2573 2574 /* Jump and save. */ 2575 static int dec_jas_r(CPUCRISState *env, DisasContext *dc) 2576 { 2577 TCGv c; 2578 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2); 2579 cris_cc_mask(dc, 0); 2580 /* Store the return address in Pd. */ 2581 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); 2582 if (dc->op2 > 15) { 2583 abort(); 2584 } 2585 c = tcg_const_tl(dc->pc + 4); 2586 t_gen_mov_preg_TN(dc, dc->op2, c); 2587 2588 cris_prepare_jmp(dc, JMP_INDIRECT); 2589 return 2; 2590 } 2591 2592 static int dec_jas_im(CPUCRISState *env, DisasContext *dc) 2593 { 2594 uint32_t imm; 2595 TCGv c; 2596 2597 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); 2598 2599 LOG_DIS("jas 0x%x\n", imm); 2600 cris_cc_mask(dc, 0); 2601 c = tcg_const_tl(dc->pc + 8); 2602 /* Store the return address in Pd. */ 2603 t_gen_mov_preg_TN(dc, dc->op2, c); 2604 2605 dc->jmp_pc = imm; 2606 cris_prepare_jmp(dc, JMP_DIRECT); 2607 return 6; 2608 } 2609 2610 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc) 2611 { 2612 uint32_t imm; 2613 TCGv c; 2614 2615 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); 2616 2617 LOG_DIS("jasc 0x%x\n", imm); 2618 cris_cc_mask(dc, 0); 2619 c = tcg_const_tl(dc->pc + 8 + 4); 2620 /* Store the return address in Pd. */ 2621 t_gen_mov_preg_TN(dc, dc->op2, c); 2622 2623 dc->jmp_pc = imm; 2624 cris_prepare_jmp(dc, JMP_DIRECT); 2625 return 6; 2626 } 2627 2628 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc) 2629 { 2630 TCGv c; 2631 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2); 2632 cris_cc_mask(dc, 0); 2633 /* Store the return address in Pd. */ 2634 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); 2635 c = tcg_const_tl(dc->pc + 4 + 4); 2636 t_gen_mov_preg_TN(dc, dc->op2, c); 2637 cris_prepare_jmp(dc, JMP_INDIRECT); 2638 return 2; 2639 } 2640 2641 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc) 2642 { 2643 int32_t offset; 2644 uint32_t cond = dc->op2; 2645 2646 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1); 2647 2648 LOG_DIS("b%s %d pc=%x dst=%x\n", 2649 cc_name(cond), offset, 2650 dc->pc, dc->pc + offset); 2651 2652 cris_cc_mask(dc, 0); 2653 /* op2 holds the condition-code. */ 2654 cris_prepare_cc_branch(dc, offset, cond); 2655 return 4; 2656 } 2657 2658 static int dec_bas_im(CPUCRISState *env, DisasContext *dc) 2659 { 2660 int32_t simm; 2661 TCGv c; 2662 2663 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); 2664 2665 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2); 2666 cris_cc_mask(dc, 0); 2667 c = tcg_const_tl(dc->pc + 8); 2668 /* Store the return address in Pd. */ 2669 t_gen_mov_preg_TN(dc, dc->op2, c); 2670 2671 dc->jmp_pc = dc->pc + simm; 2672 cris_prepare_jmp(dc, JMP_DIRECT); 2673 return 6; 2674 } 2675 2676 static int dec_basc_im(CPUCRISState *env, DisasContext *dc) 2677 { 2678 int32_t simm; 2679 TCGv c; 2680 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); 2681 2682 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2); 2683 cris_cc_mask(dc, 0); 2684 c = tcg_const_tl(dc->pc + 12); 2685 /* Store the return address in Pd. */ 2686 t_gen_mov_preg_TN(dc, dc->op2, c); 2687 2688 dc->jmp_pc = dc->pc + simm; 2689 cris_prepare_jmp(dc, JMP_DIRECT); 2690 return 6; 2691 } 2692 2693 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc) 2694 { 2695 cris_cc_mask(dc, 0); 2696 2697 if (dc->op2 == 15) { 2698 tcg_gen_st_i32(tcg_const_i32(1), cpu_env, 2699 -offsetof(CRISCPU, env) + offsetof(CPUState, halted)); 2700 tcg_gen_movi_tl(env_pc, dc->pc + 2); 2701 t_gen_raise_exception(EXCP_HLT); 2702 dc->base.is_jmp = DISAS_NORETURN; 2703 return 2; 2704 } 2705 2706 switch (dc->op2 & 7) { 2707 case 2: 2708 /* rfe. */ 2709 LOG_DIS("rfe\n"); 2710 cris_evaluate_flags(dc); 2711 gen_helper_rfe(cpu_env); 2712 dc->base.is_jmp = DISAS_UPDATE; 2713 dc->cpustate_changed = true; 2714 break; 2715 case 5: 2716 /* rfn. */ 2717 LOG_DIS("rfn\n"); 2718 cris_evaluate_flags(dc); 2719 gen_helper_rfn(cpu_env); 2720 dc->base.is_jmp = DISAS_UPDATE; 2721 dc->cpustate_changed = true; 2722 break; 2723 case 6: 2724 LOG_DIS("break %d\n", dc->op1); 2725 cris_evaluate_flags(dc); 2726 /* break. */ 2727 tcg_gen_movi_tl(env_pc, dc->pc + 2); 2728 2729 /* Breaks start at 16 in the exception vector. */ 2730 t_gen_movi_env_TN(trap_vector, dc->op1 + 16); 2731 t_gen_raise_exception(EXCP_BREAK); 2732 dc->base.is_jmp = DISAS_NORETURN; 2733 break; 2734 default: 2735 printf("op2=%x\n", dc->op2); 2736 BUG(); 2737 break; 2738 2739 } 2740 return 2; 2741 } 2742 2743 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc) 2744 { 2745 return 2; 2746 } 2747 2748 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc) 2749 { 2750 return 2; 2751 } 2752 2753 static int dec_null(CPUCRISState *env, DisasContext *dc) 2754 { 2755 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n", 2756 dc->pc, dc->opcode, dc->op1, dc->op2); 2757 fflush(NULL); 2758 BUG(); 2759 return 2; 2760 } 2761 2762 static const struct decoder_info { 2763 struct { 2764 uint32_t bits; 2765 uint32_t mask; 2766 }; 2767 int (*dec)(CPUCRISState *env, DisasContext *dc); 2768 } decinfo[] = { 2769 /* Order matters here. */ 2770 {DEC_MOVEQ, dec_moveq}, 2771 {DEC_BTSTQ, dec_btstq}, 2772 {DEC_CMPQ, dec_cmpq}, 2773 {DEC_ADDOQ, dec_addoq}, 2774 {DEC_ADDQ, dec_addq}, 2775 {DEC_SUBQ, dec_subq}, 2776 {DEC_ANDQ, dec_andq}, 2777 {DEC_ORQ, dec_orq}, 2778 {DEC_ASRQ, dec_asrq}, 2779 {DEC_LSLQ, dec_lslq}, 2780 {DEC_LSRQ, dec_lsrq}, 2781 {DEC_BCCQ, dec_bccq}, 2782 2783 {DEC_BCC_IM, dec_bcc_im}, 2784 {DEC_JAS_IM, dec_jas_im}, 2785 {DEC_JAS_R, dec_jas_r}, 2786 {DEC_JASC_IM, dec_jasc_im}, 2787 {DEC_JASC_R, dec_jasc_r}, 2788 {DEC_BAS_IM, dec_bas_im}, 2789 {DEC_BASC_IM, dec_basc_im}, 2790 {DEC_JUMP_P, dec_jump_p}, 2791 {DEC_LAPC_IM, dec_lapc_im}, 2792 {DEC_LAPCQ, dec_lapcq}, 2793 2794 {DEC_RFE_ETC, dec_rfe_etc}, 2795 {DEC_ADDC_MR, dec_addc_mr}, 2796 2797 {DEC_MOVE_MP, dec_move_mp}, 2798 {DEC_MOVE_PM, dec_move_pm}, 2799 {DEC_MOVEM_MR, dec_movem_mr}, 2800 {DEC_MOVEM_RM, dec_movem_rm}, 2801 {DEC_MOVE_PR, dec_move_pr}, 2802 {DEC_SCC_R, dec_scc_r}, 2803 {DEC_SETF, dec_setclrf}, 2804 {DEC_CLEARF, dec_setclrf}, 2805 2806 {DEC_MOVE_SR, dec_move_sr}, 2807 {DEC_MOVE_RP, dec_move_rp}, 2808 {DEC_SWAP_R, dec_swap_r}, 2809 {DEC_ABS_R, dec_abs_r}, 2810 {DEC_LZ_R, dec_lz_r}, 2811 {DEC_MOVE_RS, dec_move_rs}, 2812 {DEC_BTST_R, dec_btst_r}, 2813 {DEC_ADDC_R, dec_addc_r}, 2814 2815 {DEC_DSTEP_R, dec_dstep_r}, 2816 {DEC_XOR_R, dec_xor_r}, 2817 {DEC_MCP_R, dec_mcp_r}, 2818 {DEC_CMP_R, dec_cmp_r}, 2819 2820 {DEC_ADDI_R, dec_addi_r}, 2821 {DEC_ADDI_ACR, dec_addi_acr}, 2822 2823 {DEC_ADD_R, dec_add_r}, 2824 {DEC_SUB_R, dec_sub_r}, 2825 2826 {DEC_ADDU_R, dec_addu_r}, 2827 {DEC_ADDS_R, dec_adds_r}, 2828 {DEC_SUBU_R, dec_subu_r}, 2829 {DEC_SUBS_R, dec_subs_r}, 2830 {DEC_LSL_R, dec_lsl_r}, 2831 2832 {DEC_AND_R, dec_and_r}, 2833 {DEC_OR_R, dec_or_r}, 2834 {DEC_BOUND_R, dec_bound_r}, 2835 {DEC_ASR_R, dec_asr_r}, 2836 {DEC_LSR_R, dec_lsr_r}, 2837 2838 {DEC_MOVU_R, dec_movu_r}, 2839 {DEC_MOVS_R, dec_movs_r}, 2840 {DEC_NEG_R, dec_neg_r}, 2841 {DEC_MOVE_R, dec_move_r}, 2842 2843 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m}, 2844 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m}, 2845 2846 {DEC_MULS_R, dec_muls_r}, 2847 {DEC_MULU_R, dec_mulu_r}, 2848 2849 {DEC_ADDU_M, dec_addu_m}, 2850 {DEC_ADDS_M, dec_adds_m}, 2851 {DEC_SUBU_M, dec_subu_m}, 2852 {DEC_SUBS_M, dec_subs_m}, 2853 2854 {DEC_CMPU_M, dec_cmpu_m}, 2855 {DEC_CMPS_M, dec_cmps_m}, 2856 {DEC_MOVU_M, dec_movu_m}, 2857 {DEC_MOVS_M, dec_movs_m}, 2858 2859 {DEC_CMP_M, dec_cmp_m}, 2860 {DEC_ADDO_M, dec_addo_m}, 2861 {DEC_BOUND_M, dec_bound_m}, 2862 {DEC_ADD_M, dec_add_m}, 2863 {DEC_SUB_M, dec_sub_m}, 2864 {DEC_AND_M, dec_and_m}, 2865 {DEC_OR_M, dec_or_m}, 2866 {DEC_MOVE_RM, dec_move_rm}, 2867 {DEC_TEST_M, dec_test_m}, 2868 {DEC_MOVE_MR, dec_move_mr}, 2869 2870 {{0, 0}, dec_null} 2871 }; 2872 2873 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) 2874 { 2875 int insn_len = 2; 2876 int i; 2877 2878 /* Load a halfword onto the instruction register. */ 2879 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0); 2880 2881 /* Now decode it. */ 2882 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11); 2883 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3); 2884 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15); 2885 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4); 2886 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5); 2887 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10); 2888 2889 /* Large switch for all insns. */ 2890 for (i = 0; i < ARRAY_SIZE(decinfo); i++) { 2891 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { 2892 insn_len = decinfo[i].dec(env, dc); 2893 break; 2894 } 2895 } 2896 2897 #if !defined(CONFIG_USER_ONLY) 2898 /* Single-stepping ? */ 2899 if (dc->tb_flags & S_FLAG) { 2900 TCGLabel *l1 = gen_new_label(); 2901 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1); 2902 /* We treat SPC as a break with an odd trap vector. */ 2903 cris_evaluate_flags(dc); 2904 t_gen_movi_env_TN(trap_vector, 3); 2905 tcg_gen_movi_tl(env_pc, dc->pc + insn_len); 2906 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len); 2907 t_gen_raise_exception(EXCP_BREAK); 2908 gen_set_label(l1); 2909 } 2910 #endif 2911 return insn_len; 2912 } 2913 2914 #include "translate_v10.c.inc" 2915 2916 /* 2917 * Delay slots on QEMU/CRIS. 2918 * 2919 * If an exception hits on a delayslot, the core will let ERP (the Exception 2920 * Return Pointer) point to the branch (the previous) insn and set the lsb to 2921 * to give SW a hint that the exception actually hit on the dslot. 2922 * 2923 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by 2924 * the core and any jmp to an odd addresses will mask off that lsb. It is 2925 * simply there to let sw know there was an exception on a dslot. 2926 * 2927 * When the software returns from an exception, the branch will re-execute. 2928 * On QEMU care needs to be taken when a branch+delayslot sequence is broken 2929 * and the branch and delayslot don't share pages. 2930 * 2931 * The TB contaning the branch insn will set up env->btarget and evaluate 2932 * env->btaken. When the translation loop exits we will note that the branch 2933 * sequence is broken and let env->dslot be the size of the branch insn (those 2934 * vary in length). 2935 * 2936 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb 2937 * set). It will also expect to have env->dslot setup with the size of the 2938 * delay slot so that env->pc - env->dslot point to the branch insn. This TB 2939 * will execute the dslot and take the branch, either to btarget or just one 2940 * insn ahead. 2941 * 2942 * When exceptions occur, we check for env->dslot in do_interrupt to detect 2943 * broken branch sequences and setup $erp accordingly (i.e let it point to the 2944 * branch and set lsb). Then env->dslot gets cleared so that the exception 2945 * handler can enter. When returning from exceptions (jump $erp) the lsb gets 2946 * masked off and we will reexecute the branch insn. 2947 * 2948 */ 2949 2950 static void cris_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 2951 { 2952 DisasContext *dc = container_of(dcbase, DisasContext, base); 2953 CPUCRISState *env = cs->env_ptr; 2954 uint32_t tb_flags = dc->base.tb->flags; 2955 uint32_t pc_start; 2956 2957 if (env->pregs[PR_VR] == 32) { 2958 dc->decoder = crisv32_decoder; 2959 dc->clear_locked_irq = 0; 2960 } else { 2961 dc->decoder = crisv10_decoder; 2962 dc->clear_locked_irq = 1; 2963 } 2964 2965 /* 2966 * Odd PC indicates that branch is rexecuting due to exception in the 2967 * delayslot, like in real hw. 2968 */ 2969 pc_start = dc->base.pc_first & ~1; 2970 dc->base.pc_first = pc_start; 2971 dc->base.pc_next = pc_start; 2972 2973 dc->cpu = env_archcpu(env); 2974 dc->ppc = pc_start; 2975 dc->pc = pc_start; 2976 dc->flags_uptodate = 1; 2977 dc->flags_x = tb_flags & X_FLAG; 2978 dc->cc_x_uptodate = 0; 2979 dc->cc_mask = 0; 2980 dc->update_cc = 0; 2981 dc->clear_prefix = 0; 2982 dc->cpustate_changed = 0; 2983 2984 cris_update_cc_op(dc, CC_OP_FLAGS, 4); 2985 dc->cc_size_uptodate = -1; 2986 2987 /* Decode TB flags. */ 2988 dc->tb_flags = tb_flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG | PFIX_FLAG); 2989 dc->delayed_branch = !!(tb_flags & 7); 2990 if (dc->delayed_branch) { 2991 dc->jmp = JMP_INDIRECT; 2992 } else { 2993 dc->jmp = JMP_NOJMP; 2994 } 2995 } 2996 2997 static void cris_tr_tb_start(DisasContextBase *db, CPUState *cpu) 2998 { 2999 } 3000 3001 static void cris_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 3002 { 3003 DisasContext *dc = container_of(dcbase, DisasContext, base); 3004 3005 tcg_gen_insn_start(dc->delayed_branch == 1 ? dc->ppc | 1 : dc->pc); 3006 } 3007 3008 static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 3009 { 3010 DisasContext *dc = container_of(dcbase, DisasContext, base); 3011 CPUCRISState *env = cs->env_ptr; 3012 unsigned int insn_len; 3013 3014 /* Pretty disas. */ 3015 LOG_DIS("%8.8x:\t", dc->pc); 3016 3017 dc->clear_x = 1; 3018 3019 insn_len = dc->decoder(env, dc); 3020 dc->ppc = dc->pc; 3021 dc->pc += insn_len; 3022 dc->base.pc_next += insn_len; 3023 3024 if (dc->base.is_jmp == DISAS_NORETURN) { 3025 return; 3026 } 3027 3028 if (dc->clear_x) { 3029 cris_clear_x_flag(dc); 3030 } 3031 3032 /* 3033 * All branches are delayed branches, handled immediately below. 3034 * We don't expect to see odd combinations of exit conditions. 3035 */ 3036 assert(dc->base.is_jmp == DISAS_NEXT || dc->cpustate_changed); 3037 3038 if (dc->delayed_branch && --dc->delayed_branch == 0) { 3039 dc->base.is_jmp = DISAS_DBRANCH; 3040 return; 3041 } 3042 3043 if (dc->base.is_jmp != DISAS_NEXT) { 3044 return; 3045 } 3046 3047 /* Force an update if the per-tb cpu state has changed. */ 3048 if (dc->cpustate_changed) { 3049 dc->base.is_jmp = DISAS_UPDATE_NEXT; 3050 return; 3051 } 3052 3053 /* 3054 * FIXME: Only the first insn in the TB should cross a page boundary. 3055 * If we can detect the length of the next insn easily, we should. 3056 * In the meantime, simply stop when we do cross. 3057 */ 3058 if ((dc->pc ^ dc->base.pc_first) & TARGET_PAGE_MASK) { 3059 dc->base.is_jmp = DISAS_TOO_MANY; 3060 } 3061 } 3062 3063 static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 3064 { 3065 DisasContext *dc = container_of(dcbase, DisasContext, base); 3066 DisasJumpType is_jmp = dc->base.is_jmp; 3067 target_ulong npc = dc->pc; 3068 3069 if (is_jmp == DISAS_NORETURN) { 3070 /* If we have a broken branch+delayslot sequence, it's too late. */ 3071 assert(dc->delayed_branch != 1); 3072 return; 3073 } 3074 3075 if (dc->clear_locked_irq) { 3076 t_gen_movi_env_TN(locked_irq, 0); 3077 } 3078 3079 /* Broken branch+delayslot sequence. */ 3080 if (dc->delayed_branch == 1) { 3081 /* Set env->dslot to the size of the branch insn. */ 3082 t_gen_movi_env_TN(dslot, dc->pc - dc->ppc); 3083 cris_store_direct_jmp(dc); 3084 } 3085 3086 cris_evaluate_flags(dc); 3087 3088 /* Evaluate delayed branch destination and fold to another is_jmp case. */ 3089 if (is_jmp == DISAS_DBRANCH) { 3090 if (dc->base.tb->flags & 7) { 3091 t_gen_movi_env_TN(dslot, 0); 3092 } 3093 3094 switch (dc->jmp) { 3095 case JMP_DIRECT: 3096 npc = dc->jmp_pc; 3097 is_jmp = dc->cpustate_changed ? DISAS_UPDATE_NEXT : DISAS_TOO_MANY; 3098 break; 3099 3100 case JMP_DIRECT_CC: 3101 /* 3102 * Use a conditional branch if either taken or not-taken path 3103 * can use goto_tb. If neither can, then treat it as indirect. 3104 */ 3105 if (likely(!dc->cpustate_changed) 3106 && (use_goto_tb(dc, dc->jmp_pc) || use_goto_tb(dc, npc))) { 3107 TCGLabel *not_taken = gen_new_label(); 3108 3109 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, not_taken); 3110 gen_goto_tb(dc, 1, dc->jmp_pc); 3111 gen_set_label(not_taken); 3112 3113 /* not-taken case handled below. */ 3114 is_jmp = DISAS_TOO_MANY; 3115 break; 3116 } 3117 tcg_gen_movi_tl(env_btarget, dc->jmp_pc); 3118 /* fall through */ 3119 3120 case JMP_INDIRECT: 3121 tcg_gen_movcond_tl(TCG_COND_NE, env_pc, 3122 env_btaken, tcg_constant_tl(0), 3123 env_btarget, tcg_constant_tl(npc)); 3124 is_jmp = dc->cpustate_changed ? DISAS_UPDATE : DISAS_JUMP; 3125 3126 /* 3127 * We have now consumed btaken and btarget. Hint to the 3128 * tcg compiler that the writeback to env may be dropped. 3129 */ 3130 tcg_gen_discard_tl(env_btaken); 3131 tcg_gen_discard_tl(env_btarget); 3132 break; 3133 3134 default: 3135 g_assert_not_reached(); 3136 } 3137 } 3138 3139 switch (is_jmp) { 3140 case DISAS_TOO_MANY: 3141 gen_goto_tb(dc, 0, npc); 3142 break; 3143 case DISAS_UPDATE_NEXT: 3144 tcg_gen_movi_tl(env_pc, npc); 3145 /* fall through */ 3146 case DISAS_JUMP: 3147 tcg_gen_lookup_and_goto_ptr(); 3148 break; 3149 case DISAS_UPDATE: 3150 /* Indicate that interupts must be re-evaluated before the next TB. */ 3151 tcg_gen_exit_tb(NULL, 0); 3152 break; 3153 default: 3154 g_assert_not_reached(); 3155 } 3156 } 3157 3158 static void cris_tr_disas_log(const DisasContextBase *dcbase, 3159 CPUState *cpu, FILE *logfile) 3160 { 3161 if (!DISAS_CRIS) { 3162 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 3163 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 3164 } 3165 } 3166 3167 static const TranslatorOps cris_tr_ops = { 3168 .init_disas_context = cris_tr_init_disas_context, 3169 .tb_start = cris_tr_tb_start, 3170 .insn_start = cris_tr_insn_start, 3171 .translate_insn = cris_tr_translate_insn, 3172 .tb_stop = cris_tr_tb_stop, 3173 .disas_log = cris_tr_disas_log, 3174 }; 3175 3176 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 3177 target_ulong pc, void *host_pc) 3178 { 3179 DisasContext dc; 3180 translator_loop(cs, tb, max_insns, pc, host_pc, &cris_tr_ops, &dc.base); 3181 } 3182 3183 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags) 3184 { 3185 CRISCPU *cpu = CRIS_CPU(cs); 3186 CPUCRISState *env = &cpu->env; 3187 const char * const *regnames; 3188 const char * const *pregnames; 3189 int i; 3190 3191 if (!env) { 3192 return; 3193 } 3194 if (env->pregs[PR_VR] < 32) { 3195 pregnames = pregnames_v10; 3196 regnames = regnames_v10; 3197 } else { 3198 pregnames = pregnames_v32; 3199 regnames = regnames_v32; 3200 } 3201 3202 qemu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n" 3203 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n", 3204 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget, 3205 env->cc_op, 3206 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask); 3207 3208 3209 for (i = 0; i < 16; i++) { 3210 qemu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]); 3211 if ((i + 1) % 4 == 0) { 3212 qemu_fprintf(f, "\n"); 3213 } 3214 } 3215 qemu_fprintf(f, "\nspecial regs:\n"); 3216 for (i = 0; i < 16; i++) { 3217 qemu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]); 3218 if ((i + 1) % 4 == 0) { 3219 qemu_fprintf(f, "\n"); 3220 } 3221 } 3222 if (env->pregs[PR_VR] >= 32) { 3223 uint32_t srs = env->pregs[PR_SRS]; 3224 qemu_fprintf(f, "\nsupport function regs bank %x:\n", srs); 3225 if (srs < ARRAY_SIZE(env->sregs)) { 3226 for (i = 0; i < 16; i++) { 3227 qemu_fprintf(f, "s%2.2d=%8.8x ", 3228 i, env->sregs[srs][i]); 3229 if ((i + 1) % 4 == 0) { 3230 qemu_fprintf(f, "\n"); 3231 } 3232 } 3233 } 3234 } 3235 qemu_fprintf(f, "\n\n"); 3236 3237 } 3238 3239 void cris_initialize_tcg(void) 3240 { 3241 int i; 3242 3243 cc_x = tcg_global_mem_new(cpu_env, 3244 offsetof(CPUCRISState, cc_x), "cc_x"); 3245 cc_src = tcg_global_mem_new(cpu_env, 3246 offsetof(CPUCRISState, cc_src), "cc_src"); 3247 cc_dest = tcg_global_mem_new(cpu_env, 3248 offsetof(CPUCRISState, cc_dest), 3249 "cc_dest"); 3250 cc_result = tcg_global_mem_new(cpu_env, 3251 offsetof(CPUCRISState, cc_result), 3252 "cc_result"); 3253 cc_op = tcg_global_mem_new(cpu_env, 3254 offsetof(CPUCRISState, cc_op), "cc_op"); 3255 cc_size = tcg_global_mem_new(cpu_env, 3256 offsetof(CPUCRISState, cc_size), 3257 "cc_size"); 3258 cc_mask = tcg_global_mem_new(cpu_env, 3259 offsetof(CPUCRISState, cc_mask), 3260 "cc_mask"); 3261 3262 env_pc = tcg_global_mem_new(cpu_env, 3263 offsetof(CPUCRISState, pc), 3264 "pc"); 3265 env_btarget = tcg_global_mem_new(cpu_env, 3266 offsetof(CPUCRISState, btarget), 3267 "btarget"); 3268 env_btaken = tcg_global_mem_new(cpu_env, 3269 offsetof(CPUCRISState, btaken), 3270 "btaken"); 3271 for (i = 0; i < 16; i++) { 3272 cpu_R[i] = tcg_global_mem_new(cpu_env, 3273 offsetof(CPUCRISState, regs[i]), 3274 regnames_v32[i]); 3275 } 3276 for (i = 0; i < 16; i++) { 3277 cpu_PR[i] = tcg_global_mem_new(cpu_env, 3278 offsetof(CPUCRISState, pregs[i]), 3279 pregnames_v32[i]); 3280 } 3281 } 3282