xref: /openbmc/qemu/target/cris/machine.c (revision f6a51c84)
1 /*
2  *  CRIS virtual CPU state save/load support
3  *
4  *  Copyright (c) 2012 Red Hat, Inc.
5  *  Written by Juan Quintela <quintela@redhat.com>
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qemu-common.h"
23 #include "cpu.h"
24 #include "hw/hw.h"
25 #include "migration/cpu.h"
26 
27 static const VMStateDescription vmstate_tlbset = {
28     .name = "cpu/tlbset",
29     .version_id = 1,
30     .minimum_version_id = 1,
31     .fields = (VMStateField[]) {
32         VMSTATE_UINT32(lo, TLBSet),
33         VMSTATE_UINT32(hi, TLBSet),
34         VMSTATE_END_OF_LIST()
35     }
36 };
37 
38 static const VMStateDescription vmstate_cris_env = {
39     .name = "env",
40     .version_id = 2,
41     .minimum_version_id = 2,
42     .fields = (VMStateField[]) {
43         VMSTATE_UINT32_ARRAY(regs, CPUCRISState, 16),
44         VMSTATE_UINT32_ARRAY(pregs, CPUCRISState, 16),
45         VMSTATE_UINT32(pc, CPUCRISState),
46         VMSTATE_UINT32(ksp, CPUCRISState),
47         VMSTATE_INT32(dslot, CPUCRISState),
48         VMSTATE_INT32(btaken, CPUCRISState),
49         VMSTATE_UINT32(btarget, CPUCRISState),
50         VMSTATE_UINT32(cc_op, CPUCRISState),
51         VMSTATE_UINT32(cc_mask, CPUCRISState),
52         VMSTATE_UINT32(cc_dest, CPUCRISState),
53         VMSTATE_UINT32(cc_src, CPUCRISState),
54         VMSTATE_UINT32(cc_result, CPUCRISState),
55         VMSTATE_INT32(cc_size, CPUCRISState),
56         VMSTATE_INT32(cc_x, CPUCRISState),
57         VMSTATE_INT32(locked_irq, CPUCRISState),
58         VMSTATE_INT32(interrupt_vector, CPUCRISState),
59         VMSTATE_INT32(fault_vector, CPUCRISState),
60         VMSTATE_INT32(trap_vector, CPUCRISState),
61         VMSTATE_UINT32_ARRAY(sregs[0], CPUCRISState, 16),
62         VMSTATE_UINT32_ARRAY(sregs[1], CPUCRISState, 16),
63         VMSTATE_UINT32_ARRAY(sregs[2], CPUCRISState, 16),
64         VMSTATE_UINT32_ARRAY(sregs[3], CPUCRISState, 16),
65         VMSTATE_UINT32(mmu_rand_lfsr, CPUCRISState),
66         VMSTATE_STRUCT_ARRAY(tlbsets[0][0], CPUCRISState, 16, 0,
67                              vmstate_tlbset, TLBSet),
68         VMSTATE_STRUCT_ARRAY(tlbsets[0][1], CPUCRISState, 16, 0,
69                              vmstate_tlbset, TLBSet),
70         VMSTATE_STRUCT_ARRAY(tlbsets[0][2], CPUCRISState, 16, 0,
71                              vmstate_tlbset, TLBSet),
72         VMSTATE_STRUCT_ARRAY(tlbsets[0][3], CPUCRISState, 16, 0,
73                              vmstate_tlbset, TLBSet),
74         VMSTATE_STRUCT_ARRAY(tlbsets[1][0], CPUCRISState, 16, 0,
75                              vmstate_tlbset, TLBSet),
76         VMSTATE_STRUCT_ARRAY(tlbsets[1][1], CPUCRISState, 16, 0,
77                              vmstate_tlbset, TLBSet),
78         VMSTATE_STRUCT_ARRAY(tlbsets[1][2], CPUCRISState, 16, 0,
79                              vmstate_tlbset, TLBSet),
80         VMSTATE_STRUCT_ARRAY(tlbsets[1][3], CPUCRISState, 16, 0,
81                              vmstate_tlbset, TLBSet),
82         VMSTATE_END_OF_LIST()
83     }
84 };
85 
86 const VMStateDescription vmstate_cris_cpu = {
87     .name = "cpu",
88     .version_id = 1,
89     .minimum_version_id = 1,
90     .fields = (VMStateField[]) {
91         VMSTATE_CPU(),
92         VMSTATE_STRUCT(env, CRISCPU, 1, vmstate_cris_env, CPUCRISState),
93         VMSTATE_END_OF_LIST()
94     }
95 };
96