1 /* 2 * QEMU CRIS CPU 3 * 4 * Copyright (c) 2008 AXIS Communications AB 5 * Written by Edgar E. Iglesias. 6 * 7 * Copyright (c) 2012 SUSE LINUX Products GmbH 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu/qemu-print.h" 27 #include "cpu.h" 28 #include "mmu.h" 29 30 31 static void cris_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 CRISCPU *cpu = CRIS_CPU(cs); 34 35 cpu->env.pc = value; 36 } 37 38 static bool cris_cpu_has_work(CPUState *cs) 39 { 40 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 41 } 42 43 /* CPUClass::reset() */ 44 static void cris_cpu_reset(CPUState *s) 45 { 46 CRISCPU *cpu = CRIS_CPU(s); 47 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); 48 CPUCRISState *env = &cpu->env; 49 uint32_t vr; 50 51 ccc->parent_reset(s); 52 53 vr = env->pregs[PR_VR]; 54 memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); 55 env->pregs[PR_VR] = vr; 56 57 #if defined(CONFIG_USER_ONLY) 58 /* start in user mode with interrupts enabled. */ 59 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; 60 #else 61 cris_mmu_init(env); 62 env->pregs[PR_CCS] = 0; 63 #endif 64 } 65 66 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) 67 { 68 ObjectClass *oc; 69 char *typename; 70 71 #if defined(CONFIG_USER_ONLY) 72 if (strcasecmp(cpu_model, "any") == 0) { 73 return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32")); 74 } 75 #endif 76 77 typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model); 78 oc = object_class_by_name(typename); 79 g_free(typename); 80 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) || 81 object_class_is_abstract(oc))) { 82 oc = NULL; 83 } 84 return oc; 85 } 86 87 /* Sort alphabetically by VR. */ 88 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b) 89 { 90 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a); 91 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b); 92 93 /* */ 94 if (ccc_a->vr > ccc_b->vr) { 95 return 1; 96 } else if (ccc_a->vr < ccc_b->vr) { 97 return -1; 98 } else { 99 return 0; 100 } 101 } 102 103 static void cris_cpu_list_entry(gpointer data, gpointer user_data) 104 { 105 ObjectClass *oc = data; 106 const char *typename = object_class_get_name(oc); 107 char *name; 108 109 name = g_strndup(typename, strlen(typename) - strlen(CRIS_CPU_TYPE_SUFFIX)); 110 qemu_printf(" %s\n", name); 111 g_free(name); 112 } 113 114 void cris_cpu_list(void) 115 { 116 GSList *list; 117 118 list = object_class_get_list(TYPE_CRIS_CPU, false); 119 list = g_slist_sort(list, cris_cpu_list_compare); 120 qemu_printf("Available CPUs:\n"); 121 g_slist_foreach(list, cris_cpu_list_entry, NULL); 122 g_slist_free(list); 123 } 124 125 static void cris_cpu_realizefn(DeviceState *dev, Error **errp) 126 { 127 CPUState *cs = CPU(dev); 128 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); 129 Error *local_err = NULL; 130 131 cpu_exec_realizefn(cs, &local_err); 132 if (local_err != NULL) { 133 error_propagate(errp, local_err); 134 return; 135 } 136 137 cpu_reset(cs); 138 qemu_init_vcpu(cs); 139 140 ccc->parent_realize(dev, errp); 141 } 142 143 #ifndef CONFIG_USER_ONLY 144 static void cris_cpu_set_irq(void *opaque, int irq, int level) 145 { 146 CRISCPU *cpu = opaque; 147 CPUState *cs = CPU(cpu); 148 int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI; 149 150 if (level) { 151 cpu_interrupt(cs, type); 152 } else { 153 cpu_reset_interrupt(cs, type); 154 } 155 } 156 #endif 157 158 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) 159 { 160 CRISCPU *cc = CRIS_CPU(cpu); 161 CPUCRISState *env = &cc->env; 162 163 if (env->pregs[PR_VR] != 32) { 164 info->mach = bfd_mach_cris_v0_v10; 165 info->print_insn = print_insn_crisv10; 166 } else { 167 info->mach = bfd_mach_cris_v32; 168 info->print_insn = print_insn_crisv32; 169 } 170 } 171 172 static void cris_cpu_initfn(Object *obj) 173 { 174 CRISCPU *cpu = CRIS_CPU(obj); 175 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); 176 CPUCRISState *env = &cpu->env; 177 178 cpu_set_cpustate_pointers(cpu); 179 180 env->pregs[PR_VR] = ccc->vr; 181 182 #ifndef CONFIG_USER_ONLY 183 /* IRQ and NMI lines. */ 184 qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2); 185 #endif 186 } 187 188 static void crisv8_cpu_class_init(ObjectClass *oc, void *data) 189 { 190 CPUClass *cc = CPU_CLASS(oc); 191 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 192 193 ccc->vr = 8; 194 cc->do_interrupt = crisv10_cpu_do_interrupt; 195 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 196 cc->tcg_initialize = cris_initialize_crisv10_tcg; 197 } 198 199 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) 200 { 201 CPUClass *cc = CPU_CLASS(oc); 202 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 203 204 ccc->vr = 9; 205 cc->do_interrupt = crisv10_cpu_do_interrupt; 206 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 207 cc->tcg_initialize = cris_initialize_crisv10_tcg; 208 } 209 210 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) 211 { 212 CPUClass *cc = CPU_CLASS(oc); 213 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 214 215 ccc->vr = 10; 216 cc->do_interrupt = crisv10_cpu_do_interrupt; 217 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 218 cc->tcg_initialize = cris_initialize_crisv10_tcg; 219 } 220 221 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) 222 { 223 CPUClass *cc = CPU_CLASS(oc); 224 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 225 226 ccc->vr = 11; 227 cc->do_interrupt = crisv10_cpu_do_interrupt; 228 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 229 cc->tcg_initialize = cris_initialize_crisv10_tcg; 230 } 231 232 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) 233 { 234 CPUClass *cc = CPU_CLASS(oc); 235 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 236 237 ccc->vr = 17; 238 cc->do_interrupt = crisv10_cpu_do_interrupt; 239 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 240 cc->tcg_initialize = cris_initialize_crisv10_tcg; 241 } 242 243 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) 244 { 245 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 246 247 ccc->vr = 32; 248 } 249 250 static void cris_cpu_class_init(ObjectClass *oc, void *data) 251 { 252 DeviceClass *dc = DEVICE_CLASS(oc); 253 CPUClass *cc = CPU_CLASS(oc); 254 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 255 256 device_class_set_parent_realize(dc, cris_cpu_realizefn, 257 &ccc->parent_realize); 258 259 ccc->parent_reset = cc->reset; 260 cc->reset = cris_cpu_reset; 261 262 cc->class_by_name = cris_cpu_class_by_name; 263 cc->has_work = cris_cpu_has_work; 264 cc->do_interrupt = cris_cpu_do_interrupt; 265 cc->cpu_exec_interrupt = cris_cpu_exec_interrupt; 266 cc->dump_state = cris_cpu_dump_state; 267 cc->set_pc = cris_cpu_set_pc; 268 cc->gdb_read_register = cris_cpu_gdb_read_register; 269 cc->gdb_write_register = cris_cpu_gdb_write_register; 270 cc->tlb_fill = cris_cpu_tlb_fill; 271 #ifndef CONFIG_USER_ONLY 272 cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; 273 dc->vmsd = &vmstate_cris_cpu; 274 #endif 275 276 cc->gdb_num_core_regs = 49; 277 cc->gdb_stop_before_watchpoint = true; 278 279 cc->disas_set_info = cris_disas_set_info; 280 cc->tcg_initialize = cris_initialize_tcg; 281 } 282 283 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \ 284 { \ 285 .parent = TYPE_CRIS_CPU, \ 286 .class_init = initfn, \ 287 .name = CRIS_CPU_TYPE_NAME(cpu_model), \ 288 } 289 290 static const TypeInfo cris_cpu_model_type_infos[] = { 291 { 292 .name = TYPE_CRIS_CPU, 293 .parent = TYPE_CPU, 294 .instance_size = sizeof(CRISCPU), 295 .instance_init = cris_cpu_initfn, 296 .abstract = true, 297 .class_size = sizeof(CRISCPUClass), 298 .class_init = cris_cpu_class_init, 299 }, 300 DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init), 301 DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init), 302 DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init), 303 DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init), 304 DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init), 305 DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init), 306 }; 307 308 DEFINE_TYPES(cris_cpu_model_type_infos) 309