1 /* 2 * QEMU CRIS CPU 3 * 4 * Copyright (c) 2008 AXIS Communications AB 5 * Written by Edgar E. Iglesias. 6 * 7 * Copyright (c) 2012 SUSE LINUX Products GmbH 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu/qemu-print.h" 27 #include "cpu.h" 28 #include "mmu.h" 29 30 31 static void cris_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 CRISCPU *cpu = CRIS_CPU(cs); 34 35 cpu->env.pc = value; 36 } 37 38 static vaddr cris_cpu_get_pc(CPUState *cs) 39 { 40 CRISCPU *cpu = CRIS_CPU(cs); 41 42 return cpu->env.pc; 43 } 44 45 static void cris_restore_state_to_opc(CPUState *cs, 46 const TranslationBlock *tb, 47 const uint64_t *data) 48 { 49 CRISCPU *cpu = CRIS_CPU(cs); 50 51 cpu->env.pc = data[0]; 52 } 53 54 static bool cris_cpu_has_work(CPUState *cs) 55 { 56 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 57 } 58 59 static void cris_cpu_reset_hold(Object *obj) 60 { 61 CPUState *s = CPU(obj); 62 CRISCPU *cpu = CRIS_CPU(s); 63 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); 64 CPUCRISState *env = &cpu->env; 65 uint32_t vr; 66 67 if (ccc->parent_phases.hold) { 68 ccc->parent_phases.hold(obj); 69 } 70 71 vr = env->pregs[PR_VR]; 72 memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); 73 env->pregs[PR_VR] = vr; 74 75 #if defined(CONFIG_USER_ONLY) 76 /* start in user mode with interrupts enabled. */ 77 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; 78 #else 79 cris_mmu_init(env); 80 env->pregs[PR_CCS] = 0; 81 #endif 82 } 83 84 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) 85 { 86 ObjectClass *oc; 87 char *typename; 88 89 #if defined(CONFIG_USER_ONLY) 90 if (strcasecmp(cpu_model, "any") == 0) { 91 return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32")); 92 } 93 #endif 94 95 typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model); 96 oc = object_class_by_name(typename); 97 g_free(typename); 98 99 return oc; 100 } 101 102 static void cris_cpu_realizefn(DeviceState *dev, Error **errp) 103 { 104 CPUState *cs = CPU(dev); 105 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); 106 Error *local_err = NULL; 107 108 cpu_exec_realizefn(cs, &local_err); 109 if (local_err != NULL) { 110 error_propagate(errp, local_err); 111 return; 112 } 113 114 cpu_reset(cs); 115 qemu_init_vcpu(cs); 116 117 ccc->parent_realize(dev, errp); 118 } 119 120 #ifndef CONFIG_USER_ONLY 121 static void cris_cpu_set_irq(void *opaque, int irq, int level) 122 { 123 CRISCPU *cpu = opaque; 124 CPUState *cs = CPU(cpu); 125 int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI; 126 127 if (irq == CRIS_CPU_IRQ) { 128 /* 129 * The PIC passes us the vector for the IRQ as the value it sends 130 * over the qemu_irq line 131 */ 132 cpu->env.interrupt_vector = level; 133 } 134 135 if (level) { 136 cpu_interrupt(cs, type); 137 } else { 138 cpu_reset_interrupt(cs, type); 139 } 140 } 141 #endif 142 143 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) 144 { 145 CRISCPU *cc = CRIS_CPU(cpu); 146 CPUCRISState *env = &cc->env; 147 148 if (env->pregs[PR_VR] != 32) { 149 info->mach = bfd_mach_cris_v0_v10; 150 info->print_insn = print_insn_crisv10; 151 } else { 152 info->mach = bfd_mach_cris_v32; 153 info->print_insn = print_insn_crisv32; 154 } 155 } 156 157 static void cris_cpu_initfn(Object *obj) 158 { 159 CRISCPU *cpu = CRIS_CPU(obj); 160 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); 161 CPUCRISState *env = &cpu->env; 162 163 env->pregs[PR_VR] = ccc->vr; 164 165 #ifndef CONFIG_USER_ONLY 166 /* IRQ and NMI lines. */ 167 qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2); 168 #endif 169 } 170 171 #ifndef CONFIG_USER_ONLY 172 #include "hw/core/sysemu-cpu-ops.h" 173 174 static const struct SysemuCPUOps cris_sysemu_ops = { 175 .get_phys_page_debug = cris_cpu_get_phys_page_debug, 176 }; 177 #endif 178 179 #include "hw/core/tcg-cpu-ops.h" 180 181 static const struct TCGCPUOps crisv10_tcg_ops = { 182 .initialize = cris_initialize_crisv10_tcg, 183 .restore_state_to_opc = cris_restore_state_to_opc, 184 185 #ifndef CONFIG_USER_ONLY 186 .tlb_fill = cris_cpu_tlb_fill, 187 .cpu_exec_interrupt = cris_cpu_exec_interrupt, 188 .do_interrupt = crisv10_cpu_do_interrupt, 189 #endif /* !CONFIG_USER_ONLY */ 190 }; 191 192 static const struct TCGCPUOps crisv32_tcg_ops = { 193 .initialize = cris_initialize_tcg, 194 .restore_state_to_opc = cris_restore_state_to_opc, 195 196 #ifndef CONFIG_USER_ONLY 197 .tlb_fill = cris_cpu_tlb_fill, 198 .cpu_exec_interrupt = cris_cpu_exec_interrupt, 199 .do_interrupt = cris_cpu_do_interrupt, 200 #endif /* !CONFIG_USER_ONLY */ 201 }; 202 203 static void crisv8_cpu_class_init(ObjectClass *oc, void *data) 204 { 205 CPUClass *cc = CPU_CLASS(oc); 206 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 207 208 ccc->vr = 8; 209 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 210 cc->tcg_ops = &crisv10_tcg_ops; 211 } 212 213 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) 214 { 215 CPUClass *cc = CPU_CLASS(oc); 216 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 217 218 ccc->vr = 9; 219 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 220 cc->tcg_ops = &crisv10_tcg_ops; 221 } 222 223 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) 224 { 225 CPUClass *cc = CPU_CLASS(oc); 226 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 227 228 ccc->vr = 10; 229 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 230 cc->tcg_ops = &crisv10_tcg_ops; 231 } 232 233 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) 234 { 235 CPUClass *cc = CPU_CLASS(oc); 236 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 237 238 ccc->vr = 11; 239 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 240 cc->tcg_ops = &crisv10_tcg_ops; 241 } 242 243 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) 244 { 245 CPUClass *cc = CPU_CLASS(oc); 246 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 247 248 ccc->vr = 17; 249 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 250 cc->tcg_ops = &crisv10_tcg_ops; 251 } 252 253 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) 254 { 255 CPUClass *cc = CPU_CLASS(oc); 256 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 257 258 ccc->vr = 32; 259 cc->tcg_ops = &crisv32_tcg_ops; 260 } 261 262 static void cris_cpu_class_init(ObjectClass *oc, void *data) 263 { 264 DeviceClass *dc = DEVICE_CLASS(oc); 265 CPUClass *cc = CPU_CLASS(oc); 266 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 267 ResettableClass *rc = RESETTABLE_CLASS(oc); 268 269 device_class_set_parent_realize(dc, cris_cpu_realizefn, 270 &ccc->parent_realize); 271 272 resettable_class_set_parent_phases(rc, NULL, cris_cpu_reset_hold, NULL, 273 &ccc->parent_phases); 274 275 cc->class_by_name = cris_cpu_class_by_name; 276 cc->has_work = cris_cpu_has_work; 277 cc->dump_state = cris_cpu_dump_state; 278 cc->set_pc = cris_cpu_set_pc; 279 cc->get_pc = cris_cpu_get_pc; 280 cc->gdb_read_register = cris_cpu_gdb_read_register; 281 cc->gdb_write_register = cris_cpu_gdb_write_register; 282 #ifndef CONFIG_USER_ONLY 283 dc->vmsd = &vmstate_cris_cpu; 284 cc->sysemu_ops = &cris_sysemu_ops; 285 #endif 286 287 cc->gdb_num_core_regs = 49; 288 cc->gdb_stop_before_watchpoint = true; 289 290 cc->disas_set_info = cris_disas_set_info; 291 } 292 293 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \ 294 { \ 295 .parent = TYPE_CRIS_CPU, \ 296 .class_init = initfn, \ 297 .name = CRIS_CPU_TYPE_NAME(cpu_model), \ 298 } 299 300 static const TypeInfo cris_cpu_model_type_infos[] = { 301 { 302 .name = TYPE_CRIS_CPU, 303 .parent = TYPE_CPU, 304 .instance_size = sizeof(CRISCPU), 305 .instance_align = __alignof(CRISCPU), 306 .instance_init = cris_cpu_initfn, 307 .abstract = true, 308 .class_size = sizeof(CRISCPUClass), 309 .class_init = cris_cpu_class_init, 310 }, 311 DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init), 312 DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init), 313 DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init), 314 DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init), 315 DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init), 316 DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init), 317 }; 318 319 DEFINE_TYPES(cris_cpu_model_type_infos) 320