1 /* 2 * QEMU CRIS CPU 3 * 4 * Copyright (c) 2008 AXIS Communications AB 5 * Written by Edgar E. Iglesias. 6 * 7 * Copyright (c) 2012 SUSE LINUX Products GmbH 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "qemu-common.h" 28 #include "mmu.h" 29 #include "exec/exec-all.h" 30 31 32 static void cris_cpu_set_pc(CPUState *cs, vaddr value) 33 { 34 CRISCPU *cpu = CRIS_CPU(cs); 35 36 cpu->env.pc = value; 37 } 38 39 static bool cris_cpu_has_work(CPUState *cs) 40 { 41 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 42 } 43 44 /* CPUClass::reset() */ 45 static void cris_cpu_reset(CPUState *s) 46 { 47 CRISCPU *cpu = CRIS_CPU(s); 48 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); 49 CPUCRISState *env = &cpu->env; 50 uint32_t vr; 51 52 ccc->parent_reset(s); 53 54 vr = env->pregs[PR_VR]; 55 memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); 56 env->pregs[PR_VR] = vr; 57 58 #if defined(CONFIG_USER_ONLY) 59 /* start in user mode with interrupts enabled. */ 60 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; 61 #else 62 cris_mmu_init(env); 63 env->pregs[PR_CCS] = 0; 64 #endif 65 } 66 67 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) 68 { 69 ObjectClass *oc; 70 char *typename; 71 72 if (cpu_model == NULL) { 73 return NULL; 74 } 75 76 #if defined(CONFIG_USER_ONLY) 77 if (strcasecmp(cpu_model, "any") == 0) { 78 return object_class_by_name("crisv32-" TYPE_CRIS_CPU); 79 } 80 #endif 81 82 typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model); 83 oc = object_class_by_name(typename); 84 g_free(typename); 85 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) || 86 object_class_is_abstract(oc))) { 87 oc = NULL; 88 } 89 return oc; 90 } 91 92 CRISCPU *cpu_cris_init(const char *cpu_model) 93 { 94 return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model)); 95 } 96 97 /* Sort alphabetically by VR. */ 98 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b) 99 { 100 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a); 101 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b); 102 103 /* */ 104 if (ccc_a->vr > ccc_b->vr) { 105 return 1; 106 } else if (ccc_a->vr < ccc_b->vr) { 107 return -1; 108 } else { 109 return 0; 110 } 111 } 112 113 static void cris_cpu_list_entry(gpointer data, gpointer user_data) 114 { 115 ObjectClass *oc = data; 116 CPUListState *s = user_data; 117 const char *typename = object_class_get_name(oc); 118 char *name; 119 120 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU)); 121 (*s->cpu_fprintf)(s->file, " %s\n", name); 122 g_free(name); 123 } 124 125 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf) 126 { 127 CPUListState s = { 128 .file = f, 129 .cpu_fprintf = cpu_fprintf, 130 }; 131 GSList *list; 132 133 list = object_class_get_list(TYPE_CRIS_CPU, false); 134 list = g_slist_sort(list, cris_cpu_list_compare); 135 (*cpu_fprintf)(f, "Available CPUs:\n"); 136 g_slist_foreach(list, cris_cpu_list_entry, &s); 137 g_slist_free(list); 138 } 139 140 static void cris_cpu_realizefn(DeviceState *dev, Error **errp) 141 { 142 CPUState *cs = CPU(dev); 143 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); 144 Error *local_err = NULL; 145 146 cpu_exec_realizefn(cs, &local_err); 147 if (local_err != NULL) { 148 error_propagate(errp, local_err); 149 return; 150 } 151 152 cpu_reset(cs); 153 qemu_init_vcpu(cs); 154 155 ccc->parent_realize(dev, errp); 156 } 157 158 #ifndef CONFIG_USER_ONLY 159 static void cris_cpu_set_irq(void *opaque, int irq, int level) 160 { 161 CRISCPU *cpu = opaque; 162 CPUState *cs = CPU(cpu); 163 int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI; 164 165 if (level) { 166 cpu_interrupt(cs, type); 167 } else { 168 cpu_reset_interrupt(cs, type); 169 } 170 } 171 #endif 172 173 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) 174 { 175 CRISCPU *cc = CRIS_CPU(cpu); 176 CPUCRISState *env = &cc->env; 177 178 if (env->pregs[PR_VR] != 32) { 179 info->mach = bfd_mach_cris_v0_v10; 180 info->print_insn = print_insn_crisv10; 181 } else { 182 info->mach = bfd_mach_cris_v32; 183 info->print_insn = print_insn_crisv32; 184 } 185 } 186 187 static void cris_cpu_initfn(Object *obj) 188 { 189 CPUState *cs = CPU(obj); 190 CRISCPU *cpu = CRIS_CPU(obj); 191 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); 192 CPUCRISState *env = &cpu->env; 193 static bool tcg_initialized; 194 195 cs->env_ptr = env; 196 197 env->pregs[PR_VR] = ccc->vr; 198 199 #ifndef CONFIG_USER_ONLY 200 /* IRQ and NMI lines. */ 201 qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2); 202 #endif 203 204 if (tcg_enabled() && !tcg_initialized) { 205 tcg_initialized = true; 206 if (env->pregs[PR_VR] < 32) { 207 cris_initialize_crisv10_tcg(); 208 } else { 209 cris_initialize_tcg(); 210 } 211 } 212 } 213 214 static void crisv8_cpu_class_init(ObjectClass *oc, void *data) 215 { 216 CPUClass *cc = CPU_CLASS(oc); 217 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 218 219 ccc->vr = 8; 220 cc->do_interrupt = crisv10_cpu_do_interrupt; 221 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 222 } 223 224 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) 225 { 226 CPUClass *cc = CPU_CLASS(oc); 227 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 228 229 ccc->vr = 9; 230 cc->do_interrupt = crisv10_cpu_do_interrupt; 231 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 232 } 233 234 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) 235 { 236 CPUClass *cc = CPU_CLASS(oc); 237 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 238 239 ccc->vr = 10; 240 cc->do_interrupt = crisv10_cpu_do_interrupt; 241 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 242 } 243 244 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) 245 { 246 CPUClass *cc = CPU_CLASS(oc); 247 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 248 249 ccc->vr = 11; 250 cc->do_interrupt = crisv10_cpu_do_interrupt; 251 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 252 } 253 254 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) 255 { 256 CPUClass *cc = CPU_CLASS(oc); 257 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 258 259 ccc->vr = 17; 260 cc->do_interrupt = crisv10_cpu_do_interrupt; 261 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 262 } 263 264 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) 265 { 266 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 267 268 ccc->vr = 32; 269 } 270 271 #define TYPE(model) model "-" TYPE_CRIS_CPU 272 273 static const TypeInfo cris_cpu_model_type_infos[] = { 274 { 275 .name = TYPE("crisv8"), 276 .parent = TYPE_CRIS_CPU, 277 .class_init = crisv8_cpu_class_init, 278 }, { 279 .name = TYPE("crisv9"), 280 .parent = TYPE_CRIS_CPU, 281 .class_init = crisv9_cpu_class_init, 282 }, { 283 .name = TYPE("crisv10"), 284 .parent = TYPE_CRIS_CPU, 285 .class_init = crisv10_cpu_class_init, 286 }, { 287 .name = TYPE("crisv11"), 288 .parent = TYPE_CRIS_CPU, 289 .class_init = crisv11_cpu_class_init, 290 }, { 291 .name = TYPE("crisv17"), 292 .parent = TYPE_CRIS_CPU, 293 .class_init = crisv17_cpu_class_init, 294 }, { 295 .name = TYPE("crisv32"), 296 .parent = TYPE_CRIS_CPU, 297 .class_init = crisv32_cpu_class_init, 298 } 299 }; 300 301 #undef TYPE 302 303 static void cris_cpu_class_init(ObjectClass *oc, void *data) 304 { 305 DeviceClass *dc = DEVICE_CLASS(oc); 306 CPUClass *cc = CPU_CLASS(oc); 307 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 308 309 ccc->parent_realize = dc->realize; 310 dc->realize = cris_cpu_realizefn; 311 312 ccc->parent_reset = cc->reset; 313 cc->reset = cris_cpu_reset; 314 315 cc->class_by_name = cris_cpu_class_by_name; 316 cc->has_work = cris_cpu_has_work; 317 cc->do_interrupt = cris_cpu_do_interrupt; 318 cc->cpu_exec_interrupt = cris_cpu_exec_interrupt; 319 cc->dump_state = cris_cpu_dump_state; 320 cc->set_pc = cris_cpu_set_pc; 321 cc->gdb_read_register = cris_cpu_gdb_read_register; 322 cc->gdb_write_register = cris_cpu_gdb_write_register; 323 #ifdef CONFIG_USER_ONLY 324 cc->handle_mmu_fault = cris_cpu_handle_mmu_fault; 325 #else 326 cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; 327 dc->vmsd = &vmstate_cris_cpu; 328 #endif 329 330 cc->gdb_num_core_regs = 49; 331 cc->gdb_stop_before_watchpoint = true; 332 333 cc->disas_set_info = cris_disas_set_info; 334 } 335 336 static const TypeInfo cris_cpu_type_info = { 337 .name = TYPE_CRIS_CPU, 338 .parent = TYPE_CPU, 339 .instance_size = sizeof(CRISCPU), 340 .instance_init = cris_cpu_initfn, 341 .abstract = true, 342 .class_size = sizeof(CRISCPUClass), 343 .class_init = cris_cpu_class_init, 344 }; 345 346 static void cris_cpu_register_types(void) 347 { 348 int i; 349 350 type_register_static(&cris_cpu_type_info); 351 for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) { 352 type_register_static(&cris_cpu_model_type_infos[i]); 353 } 354 } 355 356 type_init(cris_cpu_register_types) 357