1 /* 2 * QEMU CRIS CPU 3 * 4 * Copyright (c) 2008 AXIS Communications AB 5 * Written by Edgar E. Iglesias. 6 * 7 * Copyright (c) 2012 SUSE LINUX Products GmbH 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu/qemu-print.h" 27 #include "cpu.h" 28 #include "qemu-common.h" 29 #include "mmu.h" 30 31 32 static void cris_cpu_set_pc(CPUState *cs, vaddr value) 33 { 34 CRISCPU *cpu = CRIS_CPU(cs); 35 36 cpu->env.pc = value; 37 } 38 39 static bool cris_cpu_has_work(CPUState *cs) 40 { 41 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 42 } 43 44 /* CPUClass::reset() */ 45 static void cris_cpu_reset(CPUState *s) 46 { 47 CRISCPU *cpu = CRIS_CPU(s); 48 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); 49 CPUCRISState *env = &cpu->env; 50 uint32_t vr; 51 52 ccc->parent_reset(s); 53 54 vr = env->pregs[PR_VR]; 55 memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); 56 env->pregs[PR_VR] = vr; 57 58 #if defined(CONFIG_USER_ONLY) 59 /* start in user mode with interrupts enabled. */ 60 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; 61 #else 62 cris_mmu_init(env); 63 env->pregs[PR_CCS] = 0; 64 #endif 65 } 66 67 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) 68 { 69 ObjectClass *oc; 70 char *typename; 71 72 #if defined(CONFIG_USER_ONLY) 73 if (strcasecmp(cpu_model, "any") == 0) { 74 return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32")); 75 } 76 #endif 77 78 typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model); 79 oc = object_class_by_name(typename); 80 g_free(typename); 81 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) || 82 object_class_is_abstract(oc))) { 83 oc = NULL; 84 } 85 return oc; 86 } 87 88 /* Sort alphabetically by VR. */ 89 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b) 90 { 91 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a); 92 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b); 93 94 /* */ 95 if (ccc_a->vr > ccc_b->vr) { 96 return 1; 97 } else if (ccc_a->vr < ccc_b->vr) { 98 return -1; 99 } else { 100 return 0; 101 } 102 } 103 104 static void cris_cpu_list_entry(gpointer data, gpointer user_data) 105 { 106 ObjectClass *oc = data; 107 const char *typename = object_class_get_name(oc); 108 char *name; 109 110 name = g_strndup(typename, strlen(typename) - strlen(CRIS_CPU_TYPE_SUFFIX)); 111 qemu_printf(" %s\n", name); 112 g_free(name); 113 } 114 115 void cris_cpu_list(void) 116 { 117 GSList *list; 118 119 list = object_class_get_list(TYPE_CRIS_CPU, false); 120 list = g_slist_sort(list, cris_cpu_list_compare); 121 qemu_printf("Available CPUs:\n"); 122 g_slist_foreach(list, cris_cpu_list_entry, NULL); 123 g_slist_free(list); 124 } 125 126 static void cris_cpu_realizefn(DeviceState *dev, Error **errp) 127 { 128 CPUState *cs = CPU(dev); 129 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); 130 Error *local_err = NULL; 131 132 cpu_exec_realizefn(cs, &local_err); 133 if (local_err != NULL) { 134 error_propagate(errp, local_err); 135 return; 136 } 137 138 cpu_reset(cs); 139 qemu_init_vcpu(cs); 140 141 ccc->parent_realize(dev, errp); 142 } 143 144 #ifndef CONFIG_USER_ONLY 145 static void cris_cpu_set_irq(void *opaque, int irq, int level) 146 { 147 CRISCPU *cpu = opaque; 148 CPUState *cs = CPU(cpu); 149 int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI; 150 151 if (level) { 152 cpu_interrupt(cs, type); 153 } else { 154 cpu_reset_interrupt(cs, type); 155 } 156 } 157 #endif 158 159 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) 160 { 161 CRISCPU *cc = CRIS_CPU(cpu); 162 CPUCRISState *env = &cc->env; 163 164 if (env->pregs[PR_VR] != 32) { 165 info->mach = bfd_mach_cris_v0_v10; 166 info->print_insn = print_insn_crisv10; 167 } else { 168 info->mach = bfd_mach_cris_v32; 169 info->print_insn = print_insn_crisv32; 170 } 171 } 172 173 static void cris_cpu_initfn(Object *obj) 174 { 175 CPUState *cs = CPU(obj); 176 CRISCPU *cpu = CRIS_CPU(obj); 177 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); 178 CPUCRISState *env = &cpu->env; 179 180 cs->env_ptr = env; 181 182 env->pregs[PR_VR] = ccc->vr; 183 184 #ifndef CONFIG_USER_ONLY 185 /* IRQ and NMI lines. */ 186 qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2); 187 #endif 188 } 189 190 static void crisv8_cpu_class_init(ObjectClass *oc, void *data) 191 { 192 CPUClass *cc = CPU_CLASS(oc); 193 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 194 195 ccc->vr = 8; 196 cc->do_interrupt = crisv10_cpu_do_interrupt; 197 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 198 cc->tcg_initialize = cris_initialize_crisv10_tcg; 199 } 200 201 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) 202 { 203 CPUClass *cc = CPU_CLASS(oc); 204 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 205 206 ccc->vr = 9; 207 cc->do_interrupt = crisv10_cpu_do_interrupt; 208 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 209 cc->tcg_initialize = cris_initialize_crisv10_tcg; 210 } 211 212 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) 213 { 214 CPUClass *cc = CPU_CLASS(oc); 215 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 216 217 ccc->vr = 10; 218 cc->do_interrupt = crisv10_cpu_do_interrupt; 219 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 220 cc->tcg_initialize = cris_initialize_crisv10_tcg; 221 } 222 223 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) 224 { 225 CPUClass *cc = CPU_CLASS(oc); 226 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 227 228 ccc->vr = 11; 229 cc->do_interrupt = crisv10_cpu_do_interrupt; 230 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 231 cc->tcg_initialize = cris_initialize_crisv10_tcg; 232 } 233 234 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) 235 { 236 CPUClass *cc = CPU_CLASS(oc); 237 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 238 239 ccc->vr = 17; 240 cc->do_interrupt = crisv10_cpu_do_interrupt; 241 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 242 cc->tcg_initialize = cris_initialize_crisv10_tcg; 243 } 244 245 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) 246 { 247 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 248 249 ccc->vr = 32; 250 } 251 252 static void cris_cpu_class_init(ObjectClass *oc, void *data) 253 { 254 DeviceClass *dc = DEVICE_CLASS(oc); 255 CPUClass *cc = CPU_CLASS(oc); 256 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 257 258 device_class_set_parent_realize(dc, cris_cpu_realizefn, 259 &ccc->parent_realize); 260 261 ccc->parent_reset = cc->reset; 262 cc->reset = cris_cpu_reset; 263 264 cc->class_by_name = cris_cpu_class_by_name; 265 cc->has_work = cris_cpu_has_work; 266 cc->do_interrupt = cris_cpu_do_interrupt; 267 cc->cpu_exec_interrupt = cris_cpu_exec_interrupt; 268 cc->dump_state = cris_cpu_dump_state; 269 cc->set_pc = cris_cpu_set_pc; 270 cc->gdb_read_register = cris_cpu_gdb_read_register; 271 cc->gdb_write_register = cris_cpu_gdb_write_register; 272 cc->tlb_fill = cris_cpu_tlb_fill; 273 #ifndef CONFIG_USER_ONLY 274 cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; 275 dc->vmsd = &vmstate_cris_cpu; 276 #endif 277 278 cc->gdb_num_core_regs = 49; 279 cc->gdb_stop_before_watchpoint = true; 280 281 cc->disas_set_info = cris_disas_set_info; 282 cc->tcg_initialize = cris_initialize_tcg; 283 } 284 285 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \ 286 { \ 287 .parent = TYPE_CRIS_CPU, \ 288 .class_init = initfn, \ 289 .name = CRIS_CPU_TYPE_NAME(cpu_model), \ 290 } 291 292 static const TypeInfo cris_cpu_model_type_infos[] = { 293 { 294 .name = TYPE_CRIS_CPU, 295 .parent = TYPE_CPU, 296 .instance_size = sizeof(CRISCPU), 297 .instance_init = cris_cpu_initfn, 298 .abstract = true, 299 .class_size = sizeof(CRISCPUClass), 300 .class_init = cris_cpu_class_init, 301 }, 302 DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init), 303 DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init), 304 DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init), 305 DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init), 306 DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init), 307 DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init), 308 }; 309 310 DEFINE_TYPES(cris_cpu_model_type_infos) 311