1 /* 2 * QEMU CRIS CPU 3 * 4 * Copyright (c) 2008 AXIS Communications AB 5 * Written by Edgar E. Iglesias. 6 * 7 * Copyright (c) 2012 SUSE LINUX Products GmbH 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "qemu-common.h" 28 #include "mmu.h" 29 30 31 static void cris_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 CRISCPU *cpu = CRIS_CPU(cs); 34 35 cpu->env.pc = value; 36 } 37 38 static bool cris_cpu_has_work(CPUState *cs) 39 { 40 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 41 } 42 43 /* CPUClass::reset() */ 44 static void cris_cpu_reset(CPUState *s) 45 { 46 CRISCPU *cpu = CRIS_CPU(s); 47 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); 48 CPUCRISState *env = &cpu->env; 49 uint32_t vr; 50 51 ccc->parent_reset(s); 52 53 vr = env->pregs[PR_VR]; 54 memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); 55 env->pregs[PR_VR] = vr; 56 57 #if defined(CONFIG_USER_ONLY) 58 /* start in user mode with interrupts enabled. */ 59 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; 60 #else 61 cris_mmu_init(env); 62 env->pregs[PR_CCS] = 0; 63 #endif 64 } 65 66 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) 67 { 68 ObjectClass *oc; 69 char *typename; 70 71 #if defined(CONFIG_USER_ONLY) 72 if (strcasecmp(cpu_model, "any") == 0) { 73 return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32")); 74 } 75 #endif 76 77 typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model); 78 oc = object_class_by_name(typename); 79 g_free(typename); 80 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) || 81 object_class_is_abstract(oc))) { 82 oc = NULL; 83 } 84 return oc; 85 } 86 87 /* Sort alphabetically by VR. */ 88 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b) 89 { 90 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a); 91 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b); 92 93 /* */ 94 if (ccc_a->vr > ccc_b->vr) { 95 return 1; 96 } else if (ccc_a->vr < ccc_b->vr) { 97 return -1; 98 } else { 99 return 0; 100 } 101 } 102 103 static void cris_cpu_list_entry(gpointer data, gpointer user_data) 104 { 105 ObjectClass *oc = data; 106 CPUListState *s = user_data; 107 const char *typename = object_class_get_name(oc); 108 char *name; 109 110 name = g_strndup(typename, strlen(typename) - strlen(CRIS_CPU_TYPE_SUFFIX)); 111 (*s->cpu_fprintf)(s->file, " %s\n", name); 112 g_free(name); 113 } 114 115 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf) 116 { 117 CPUListState s = { 118 .file = f, 119 .cpu_fprintf = cpu_fprintf, 120 }; 121 GSList *list; 122 123 list = object_class_get_list(TYPE_CRIS_CPU, false); 124 list = g_slist_sort(list, cris_cpu_list_compare); 125 (*cpu_fprintf)(f, "Available CPUs:\n"); 126 g_slist_foreach(list, cris_cpu_list_entry, &s); 127 g_slist_free(list); 128 } 129 130 static void cris_cpu_realizefn(DeviceState *dev, Error **errp) 131 { 132 CPUState *cs = CPU(dev); 133 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); 134 Error *local_err = NULL; 135 136 cpu_exec_realizefn(cs, &local_err); 137 if (local_err != NULL) { 138 error_propagate(errp, local_err); 139 return; 140 } 141 142 cpu_reset(cs); 143 qemu_init_vcpu(cs); 144 145 ccc->parent_realize(dev, errp); 146 } 147 148 #ifndef CONFIG_USER_ONLY 149 static void cris_cpu_set_irq(void *opaque, int irq, int level) 150 { 151 CRISCPU *cpu = opaque; 152 CPUState *cs = CPU(cpu); 153 int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI; 154 155 if (level) { 156 cpu_interrupt(cs, type); 157 } else { 158 cpu_reset_interrupt(cs, type); 159 } 160 } 161 #endif 162 163 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) 164 { 165 CRISCPU *cc = CRIS_CPU(cpu); 166 CPUCRISState *env = &cc->env; 167 168 if (env->pregs[PR_VR] != 32) { 169 info->mach = bfd_mach_cris_v0_v10; 170 info->print_insn = print_insn_crisv10; 171 } else { 172 info->mach = bfd_mach_cris_v32; 173 info->print_insn = print_insn_crisv32; 174 } 175 } 176 177 static void cris_cpu_initfn(Object *obj) 178 { 179 CPUState *cs = CPU(obj); 180 CRISCPU *cpu = CRIS_CPU(obj); 181 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); 182 CPUCRISState *env = &cpu->env; 183 184 cs->env_ptr = env; 185 186 env->pregs[PR_VR] = ccc->vr; 187 188 #ifndef CONFIG_USER_ONLY 189 /* IRQ and NMI lines. */ 190 qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2); 191 #endif 192 } 193 194 static void crisv8_cpu_class_init(ObjectClass *oc, void *data) 195 { 196 CPUClass *cc = CPU_CLASS(oc); 197 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 198 199 ccc->vr = 8; 200 cc->do_interrupt = crisv10_cpu_do_interrupt; 201 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 202 cc->tcg_initialize = cris_initialize_crisv10_tcg; 203 } 204 205 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) 206 { 207 CPUClass *cc = CPU_CLASS(oc); 208 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 209 210 ccc->vr = 9; 211 cc->do_interrupt = crisv10_cpu_do_interrupt; 212 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 213 cc->tcg_initialize = cris_initialize_crisv10_tcg; 214 } 215 216 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) 217 { 218 CPUClass *cc = CPU_CLASS(oc); 219 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 220 221 ccc->vr = 10; 222 cc->do_interrupt = crisv10_cpu_do_interrupt; 223 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 224 cc->tcg_initialize = cris_initialize_crisv10_tcg; 225 } 226 227 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) 228 { 229 CPUClass *cc = CPU_CLASS(oc); 230 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 231 232 ccc->vr = 11; 233 cc->do_interrupt = crisv10_cpu_do_interrupt; 234 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 235 cc->tcg_initialize = cris_initialize_crisv10_tcg; 236 } 237 238 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) 239 { 240 CPUClass *cc = CPU_CLASS(oc); 241 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 242 243 ccc->vr = 17; 244 cc->do_interrupt = crisv10_cpu_do_interrupt; 245 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 246 cc->tcg_initialize = cris_initialize_crisv10_tcg; 247 } 248 249 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) 250 { 251 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 252 253 ccc->vr = 32; 254 } 255 256 static void cris_cpu_class_init(ObjectClass *oc, void *data) 257 { 258 DeviceClass *dc = DEVICE_CLASS(oc); 259 CPUClass *cc = CPU_CLASS(oc); 260 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 261 262 device_class_set_parent_realize(dc, cris_cpu_realizefn, 263 &ccc->parent_realize); 264 265 ccc->parent_reset = cc->reset; 266 cc->reset = cris_cpu_reset; 267 268 cc->class_by_name = cris_cpu_class_by_name; 269 cc->has_work = cris_cpu_has_work; 270 cc->do_interrupt = cris_cpu_do_interrupt; 271 cc->cpu_exec_interrupt = cris_cpu_exec_interrupt; 272 cc->dump_state = cris_cpu_dump_state; 273 cc->set_pc = cris_cpu_set_pc; 274 cc->gdb_read_register = cris_cpu_gdb_read_register; 275 cc->gdb_write_register = cris_cpu_gdb_write_register; 276 #ifdef CONFIG_USER_ONLY 277 cc->handle_mmu_fault = cris_cpu_handle_mmu_fault; 278 #else 279 cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; 280 dc->vmsd = &vmstate_cris_cpu; 281 #endif 282 283 cc->gdb_num_core_regs = 49; 284 cc->gdb_stop_before_watchpoint = true; 285 286 cc->disas_set_info = cris_disas_set_info; 287 cc->tcg_initialize = cris_initialize_tcg; 288 } 289 290 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \ 291 { \ 292 .parent = TYPE_CRIS_CPU, \ 293 .class_init = initfn, \ 294 .name = CRIS_CPU_TYPE_NAME(cpu_model), \ 295 } 296 297 static const TypeInfo cris_cpu_model_type_infos[] = { 298 { 299 .name = TYPE_CRIS_CPU, 300 .parent = TYPE_CPU, 301 .instance_size = sizeof(CRISCPU), 302 .instance_init = cris_cpu_initfn, 303 .abstract = true, 304 .class_size = sizeof(CRISCPUClass), 305 .class_init = cris_cpu_class_init, 306 }, 307 DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init), 308 DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init), 309 DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init), 310 DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init), 311 DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init), 312 DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init), 313 }; 314 315 DEFINE_TYPES(cris_cpu_model_type_infos) 316