1 /* 2 * QEMU CRIS CPU 3 * 4 * Copyright (c) 2008 AXIS Communications AB 5 * Written by Edgar E. Iglesias. 6 * 7 * Copyright (c) 2012 SUSE LINUX Products GmbH 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu/qemu-print.h" 27 #include "cpu.h" 28 #include "mmu.h" 29 30 31 static void cris_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 CRISCPU *cpu = CRIS_CPU(cs); 34 35 cpu->env.pc = value; 36 } 37 38 static bool cris_cpu_has_work(CPUState *cs) 39 { 40 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 41 } 42 43 static void cris_cpu_reset(DeviceState *dev) 44 { 45 CPUState *s = CPU(dev); 46 CRISCPU *cpu = CRIS_CPU(s); 47 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); 48 CPUCRISState *env = &cpu->env; 49 uint32_t vr; 50 51 ccc->parent_reset(dev); 52 53 vr = env->pregs[PR_VR]; 54 memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); 55 env->pregs[PR_VR] = vr; 56 57 #if defined(CONFIG_USER_ONLY) 58 /* start in user mode with interrupts enabled. */ 59 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; 60 #else 61 cris_mmu_init(env); 62 env->pregs[PR_CCS] = 0; 63 #endif 64 } 65 66 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) 67 { 68 ObjectClass *oc; 69 char *typename; 70 71 #if defined(CONFIG_USER_ONLY) 72 if (strcasecmp(cpu_model, "any") == 0) { 73 return object_class_by_name(CRIS_CPU_TYPE_NAME("crisv32")); 74 } 75 #endif 76 77 typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model); 78 oc = object_class_by_name(typename); 79 g_free(typename); 80 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) || 81 object_class_is_abstract(oc))) { 82 oc = NULL; 83 } 84 return oc; 85 } 86 87 /* Sort alphabetically by VR. */ 88 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b) 89 { 90 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a); 91 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b); 92 93 /* */ 94 if (ccc_a->vr > ccc_b->vr) { 95 return 1; 96 } else if (ccc_a->vr < ccc_b->vr) { 97 return -1; 98 } else { 99 return 0; 100 } 101 } 102 103 static void cris_cpu_list_entry(gpointer data, gpointer user_data) 104 { 105 ObjectClass *oc = data; 106 const char *typename = object_class_get_name(oc); 107 char *name; 108 109 name = g_strndup(typename, strlen(typename) - strlen(CRIS_CPU_TYPE_SUFFIX)); 110 qemu_printf(" %s\n", name); 111 g_free(name); 112 } 113 114 void cris_cpu_list(void) 115 { 116 GSList *list; 117 118 list = object_class_get_list(TYPE_CRIS_CPU, false); 119 list = g_slist_sort(list, cris_cpu_list_compare); 120 qemu_printf("Available CPUs:\n"); 121 g_slist_foreach(list, cris_cpu_list_entry, NULL); 122 g_slist_free(list); 123 } 124 125 static void cris_cpu_realizefn(DeviceState *dev, Error **errp) 126 { 127 CPUState *cs = CPU(dev); 128 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); 129 Error *local_err = NULL; 130 131 cpu_exec_realizefn(cs, &local_err); 132 if (local_err != NULL) { 133 error_propagate(errp, local_err); 134 return; 135 } 136 137 cpu_reset(cs); 138 qemu_init_vcpu(cs); 139 140 ccc->parent_realize(dev, errp); 141 } 142 143 #ifndef CONFIG_USER_ONLY 144 static void cris_cpu_set_irq(void *opaque, int irq, int level) 145 { 146 CRISCPU *cpu = opaque; 147 CPUState *cs = CPU(cpu); 148 int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI; 149 150 if (irq == CRIS_CPU_IRQ) { 151 /* 152 * The PIC passes us the vector for the IRQ as the value it sends 153 * over the qemu_irq line 154 */ 155 cpu->env.interrupt_vector = level; 156 } 157 158 if (level) { 159 cpu_interrupt(cs, type); 160 } else { 161 cpu_reset_interrupt(cs, type); 162 } 163 } 164 #endif 165 166 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) 167 { 168 CRISCPU *cc = CRIS_CPU(cpu); 169 CPUCRISState *env = &cc->env; 170 171 if (env->pregs[PR_VR] != 32) { 172 info->mach = bfd_mach_cris_v0_v10; 173 info->print_insn = print_insn_crisv10; 174 } else { 175 info->mach = bfd_mach_cris_v32; 176 info->print_insn = print_insn_crisv32; 177 } 178 } 179 180 static void cris_cpu_initfn(Object *obj) 181 { 182 CRISCPU *cpu = CRIS_CPU(obj); 183 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); 184 CPUCRISState *env = &cpu->env; 185 186 cpu_set_cpustate_pointers(cpu); 187 188 env->pregs[PR_VR] = ccc->vr; 189 190 #ifndef CONFIG_USER_ONLY 191 /* IRQ and NMI lines. */ 192 qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2); 193 #endif 194 } 195 196 static void crisv8_cpu_class_init(ObjectClass *oc, void *data) 197 { 198 CPUClass *cc = CPU_CLASS(oc); 199 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 200 201 ccc->vr = 8; 202 cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt; 203 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 204 cc->tcg_ops.initialize = cris_initialize_crisv10_tcg; 205 } 206 207 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) 208 { 209 CPUClass *cc = CPU_CLASS(oc); 210 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 211 212 ccc->vr = 9; 213 cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt; 214 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 215 cc->tcg_ops.initialize = cris_initialize_crisv10_tcg; 216 } 217 218 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) 219 { 220 CPUClass *cc = CPU_CLASS(oc); 221 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 222 223 ccc->vr = 10; 224 cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt; 225 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 226 cc->tcg_ops.initialize = cris_initialize_crisv10_tcg; 227 } 228 229 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) 230 { 231 CPUClass *cc = CPU_CLASS(oc); 232 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 233 234 ccc->vr = 11; 235 cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt; 236 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 237 cc->tcg_ops.initialize = cris_initialize_crisv10_tcg; 238 } 239 240 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) 241 { 242 CPUClass *cc = CPU_CLASS(oc); 243 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 244 245 ccc->vr = 17; 246 cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt; 247 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 248 cc->tcg_ops.initialize = cris_initialize_crisv10_tcg; 249 } 250 251 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) 252 { 253 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 254 255 ccc->vr = 32; 256 } 257 258 static void cris_cpu_class_init(ObjectClass *oc, void *data) 259 { 260 DeviceClass *dc = DEVICE_CLASS(oc); 261 CPUClass *cc = CPU_CLASS(oc); 262 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 263 264 device_class_set_parent_realize(dc, cris_cpu_realizefn, 265 &ccc->parent_realize); 266 267 device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); 268 269 cc->class_by_name = cris_cpu_class_by_name; 270 cc->has_work = cris_cpu_has_work; 271 cc->tcg_ops.do_interrupt = cris_cpu_do_interrupt; 272 cc->tcg_ops.cpu_exec_interrupt = cris_cpu_exec_interrupt; 273 cc->dump_state = cris_cpu_dump_state; 274 cc->set_pc = cris_cpu_set_pc; 275 cc->gdb_read_register = cris_cpu_gdb_read_register; 276 cc->gdb_write_register = cris_cpu_gdb_write_register; 277 cc->tcg_ops.tlb_fill = cris_cpu_tlb_fill; 278 #ifndef CONFIG_USER_ONLY 279 cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; 280 dc->vmsd = &vmstate_cris_cpu; 281 #endif 282 283 cc->gdb_num_core_regs = 49; 284 cc->gdb_stop_before_watchpoint = true; 285 286 cc->disas_set_info = cris_disas_set_info; 287 cc->tcg_ops.initialize = cris_initialize_tcg; 288 } 289 290 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \ 291 { \ 292 .parent = TYPE_CRIS_CPU, \ 293 .class_init = initfn, \ 294 .name = CRIS_CPU_TYPE_NAME(cpu_model), \ 295 } 296 297 static const TypeInfo cris_cpu_model_type_infos[] = { 298 { 299 .name = TYPE_CRIS_CPU, 300 .parent = TYPE_CPU, 301 .instance_size = sizeof(CRISCPU), 302 .instance_init = cris_cpu_initfn, 303 .abstract = true, 304 .class_size = sizeof(CRISCPUClass), 305 .class_init = cris_cpu_class_init, 306 }, 307 DEFINE_CRIS_CPU_TYPE("crisv8", crisv8_cpu_class_init), 308 DEFINE_CRIS_CPU_TYPE("crisv9", crisv9_cpu_class_init), 309 DEFINE_CRIS_CPU_TYPE("crisv10", crisv10_cpu_class_init), 310 DEFINE_CRIS_CPU_TYPE("crisv11", crisv11_cpu_class_init), 311 DEFINE_CRIS_CPU_TYPE("crisv17", crisv17_cpu_class_init), 312 DEFINE_CRIS_CPU_TYPE("crisv32", crisv32_cpu_class_init), 313 }; 314 315 DEFINE_TYPES(cris_cpu_model_type_infos) 316