1 /* 2 * QEMU CRIS CPU 3 * 4 * Copyright (c) 2008 AXIS Communications AB 5 * Written by Edgar E. Iglesias. 6 * 7 * Copyright (c) 2012 SUSE LINUX Products GmbH 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "qemu-common.h" 28 #include "mmu.h" 29 #include "exec/exec-all.h" 30 31 32 static void cris_cpu_set_pc(CPUState *cs, vaddr value) 33 { 34 CRISCPU *cpu = CRIS_CPU(cs); 35 36 cpu->env.pc = value; 37 } 38 39 static bool cris_cpu_has_work(CPUState *cs) 40 { 41 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 42 } 43 44 /* CPUClass::reset() */ 45 static void cris_cpu_reset(CPUState *s) 46 { 47 CRISCPU *cpu = CRIS_CPU(s); 48 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); 49 CPUCRISState *env = &cpu->env; 50 uint32_t vr; 51 52 ccc->parent_reset(s); 53 54 vr = env->pregs[PR_VR]; 55 memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); 56 env->pregs[PR_VR] = vr; 57 58 #if defined(CONFIG_USER_ONLY) 59 /* start in user mode with interrupts enabled. */ 60 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; 61 #else 62 cris_mmu_init(env); 63 env->pregs[PR_CCS] = 0; 64 #endif 65 } 66 67 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) 68 { 69 ObjectClass *oc; 70 char *typename; 71 72 if (cpu_model == NULL) { 73 return NULL; 74 } 75 76 #if defined(CONFIG_USER_ONLY) 77 if (strcasecmp(cpu_model, "any") == 0) { 78 return object_class_by_name("crisv32-" TYPE_CRIS_CPU); 79 } 80 #endif 81 82 typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model); 83 oc = object_class_by_name(typename); 84 g_free(typename); 85 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) || 86 object_class_is_abstract(oc))) { 87 oc = NULL; 88 } 89 return oc; 90 } 91 92 /* Sort alphabetically by VR. */ 93 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b) 94 { 95 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a); 96 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b); 97 98 /* */ 99 if (ccc_a->vr > ccc_b->vr) { 100 return 1; 101 } else if (ccc_a->vr < ccc_b->vr) { 102 return -1; 103 } else { 104 return 0; 105 } 106 } 107 108 static void cris_cpu_list_entry(gpointer data, gpointer user_data) 109 { 110 ObjectClass *oc = data; 111 CPUListState *s = user_data; 112 const char *typename = object_class_get_name(oc); 113 char *name; 114 115 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU)); 116 (*s->cpu_fprintf)(s->file, " %s\n", name); 117 g_free(name); 118 } 119 120 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf) 121 { 122 CPUListState s = { 123 .file = f, 124 .cpu_fprintf = cpu_fprintf, 125 }; 126 GSList *list; 127 128 list = object_class_get_list(TYPE_CRIS_CPU, false); 129 list = g_slist_sort(list, cris_cpu_list_compare); 130 (*cpu_fprintf)(f, "Available CPUs:\n"); 131 g_slist_foreach(list, cris_cpu_list_entry, &s); 132 g_slist_free(list); 133 } 134 135 static void cris_cpu_realizefn(DeviceState *dev, Error **errp) 136 { 137 CPUState *cs = CPU(dev); 138 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); 139 Error *local_err = NULL; 140 141 cpu_exec_realizefn(cs, &local_err); 142 if (local_err != NULL) { 143 error_propagate(errp, local_err); 144 return; 145 } 146 147 cpu_reset(cs); 148 qemu_init_vcpu(cs); 149 150 ccc->parent_realize(dev, errp); 151 } 152 153 #ifndef CONFIG_USER_ONLY 154 static void cris_cpu_set_irq(void *opaque, int irq, int level) 155 { 156 CRISCPU *cpu = opaque; 157 CPUState *cs = CPU(cpu); 158 int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI; 159 160 if (level) { 161 cpu_interrupt(cs, type); 162 } else { 163 cpu_reset_interrupt(cs, type); 164 } 165 } 166 #endif 167 168 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) 169 { 170 CRISCPU *cc = CRIS_CPU(cpu); 171 CPUCRISState *env = &cc->env; 172 173 if (env->pregs[PR_VR] != 32) { 174 info->mach = bfd_mach_cris_v0_v10; 175 info->print_insn = print_insn_crisv10; 176 } else { 177 info->mach = bfd_mach_cris_v32; 178 info->print_insn = print_insn_crisv32; 179 } 180 } 181 182 static void cris_cpu_initfn(Object *obj) 183 { 184 CPUState *cs = CPU(obj); 185 CRISCPU *cpu = CRIS_CPU(obj); 186 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); 187 CPUCRISState *env = &cpu->env; 188 static bool tcg_initialized; 189 190 cs->env_ptr = env; 191 192 env->pregs[PR_VR] = ccc->vr; 193 194 #ifndef CONFIG_USER_ONLY 195 /* IRQ and NMI lines. */ 196 qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2); 197 #endif 198 199 if (tcg_enabled() && !tcg_initialized) { 200 tcg_initialized = true; 201 if (env->pregs[PR_VR] < 32) { 202 cris_initialize_crisv10_tcg(); 203 } else { 204 cris_initialize_tcg(); 205 } 206 } 207 } 208 209 static void crisv8_cpu_class_init(ObjectClass *oc, void *data) 210 { 211 CPUClass *cc = CPU_CLASS(oc); 212 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 213 214 ccc->vr = 8; 215 cc->do_interrupt = crisv10_cpu_do_interrupt; 216 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 217 } 218 219 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) 220 { 221 CPUClass *cc = CPU_CLASS(oc); 222 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 223 224 ccc->vr = 9; 225 cc->do_interrupt = crisv10_cpu_do_interrupt; 226 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 227 } 228 229 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) 230 { 231 CPUClass *cc = CPU_CLASS(oc); 232 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 233 234 ccc->vr = 10; 235 cc->do_interrupt = crisv10_cpu_do_interrupt; 236 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 237 } 238 239 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) 240 { 241 CPUClass *cc = CPU_CLASS(oc); 242 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 243 244 ccc->vr = 11; 245 cc->do_interrupt = crisv10_cpu_do_interrupt; 246 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 247 } 248 249 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) 250 { 251 CPUClass *cc = CPU_CLASS(oc); 252 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 253 254 ccc->vr = 17; 255 cc->do_interrupt = crisv10_cpu_do_interrupt; 256 cc->gdb_read_register = crisv10_cpu_gdb_read_register; 257 } 258 259 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) 260 { 261 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 262 263 ccc->vr = 32; 264 } 265 266 #define TYPE(model) model "-" TYPE_CRIS_CPU 267 268 static const TypeInfo cris_cpu_model_type_infos[] = { 269 { 270 .name = TYPE("crisv8"), 271 .parent = TYPE_CRIS_CPU, 272 .class_init = crisv8_cpu_class_init, 273 }, { 274 .name = TYPE("crisv9"), 275 .parent = TYPE_CRIS_CPU, 276 .class_init = crisv9_cpu_class_init, 277 }, { 278 .name = TYPE("crisv10"), 279 .parent = TYPE_CRIS_CPU, 280 .class_init = crisv10_cpu_class_init, 281 }, { 282 .name = TYPE("crisv11"), 283 .parent = TYPE_CRIS_CPU, 284 .class_init = crisv11_cpu_class_init, 285 }, { 286 .name = TYPE("crisv17"), 287 .parent = TYPE_CRIS_CPU, 288 .class_init = crisv17_cpu_class_init, 289 }, { 290 .name = TYPE("crisv32"), 291 .parent = TYPE_CRIS_CPU, 292 .class_init = crisv32_cpu_class_init, 293 } 294 }; 295 296 #undef TYPE 297 298 static void cris_cpu_class_init(ObjectClass *oc, void *data) 299 { 300 DeviceClass *dc = DEVICE_CLASS(oc); 301 CPUClass *cc = CPU_CLASS(oc); 302 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); 303 304 ccc->parent_realize = dc->realize; 305 dc->realize = cris_cpu_realizefn; 306 307 ccc->parent_reset = cc->reset; 308 cc->reset = cris_cpu_reset; 309 310 cc->class_by_name = cris_cpu_class_by_name; 311 cc->has_work = cris_cpu_has_work; 312 cc->do_interrupt = cris_cpu_do_interrupt; 313 cc->cpu_exec_interrupt = cris_cpu_exec_interrupt; 314 cc->dump_state = cris_cpu_dump_state; 315 cc->set_pc = cris_cpu_set_pc; 316 cc->gdb_read_register = cris_cpu_gdb_read_register; 317 cc->gdb_write_register = cris_cpu_gdb_write_register; 318 #ifdef CONFIG_USER_ONLY 319 cc->handle_mmu_fault = cris_cpu_handle_mmu_fault; 320 #else 321 cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; 322 dc->vmsd = &vmstate_cris_cpu; 323 #endif 324 325 cc->gdb_num_core_regs = 49; 326 cc->gdb_stop_before_watchpoint = true; 327 328 cc->disas_set_info = cris_disas_set_info; 329 } 330 331 static const TypeInfo cris_cpu_type_info = { 332 .name = TYPE_CRIS_CPU, 333 .parent = TYPE_CPU, 334 .instance_size = sizeof(CRISCPU), 335 .instance_init = cris_cpu_initfn, 336 .abstract = true, 337 .class_size = sizeof(CRISCPUClass), 338 .class_init = cris_cpu_class_init, 339 }; 340 341 static void cris_cpu_register_types(void) 342 { 343 int i; 344 345 type_register_static(&cris_cpu_type_info); 346 for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) { 347 type_register_static(&cris_cpu_model_type_infos[i]); 348 } 349 } 350 351 type_init(cris_cpu_register_types) 352