1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2019-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "tcg/tcg.h" 24 #include "cpu.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "exec/cpu_ldst.h" 28 #include "exec/helper-proto.h" 29 #include "exec/helper-gen.h" 30 #include "exec/log.h" 31 #include "exec/translator.h" 32 #include "exec/gen-icount.h" 33 34 /* 35 * Define if you want a BREAK instruction translated to a breakpoint 36 * Active debugging connection is assumed 37 * This is for 38 * https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests 39 * tests 40 */ 41 #undef BREAKPOINT_ON_BREAK 42 43 static TCGv cpu_pc; 44 45 static TCGv cpu_Cf; 46 static TCGv cpu_Zf; 47 static TCGv cpu_Nf; 48 static TCGv cpu_Vf; 49 static TCGv cpu_Sf; 50 static TCGv cpu_Hf; 51 static TCGv cpu_Tf; 52 static TCGv cpu_If; 53 54 static TCGv cpu_rampD; 55 static TCGv cpu_rampX; 56 static TCGv cpu_rampY; 57 static TCGv cpu_rampZ; 58 59 static TCGv cpu_r[NUMBER_OF_CPU_REGISTERS]; 60 static TCGv cpu_eind; 61 static TCGv cpu_sp; 62 63 static TCGv cpu_skip; 64 65 static const char reg_names[NUMBER_OF_CPU_REGISTERS][8] = { 66 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 67 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 68 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 69 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 70 }; 71 #define REG(x) (cpu_r[x]) 72 73 #define DISAS_EXIT DISAS_TARGET_0 /* We want return to the cpu main loop. */ 74 #define DISAS_LOOKUP DISAS_TARGET_1 /* We have a variable condition exit. */ 75 #define DISAS_CHAIN DISAS_TARGET_2 /* We have a single condition exit. */ 76 77 typedef struct DisasContext DisasContext; 78 79 /* This is the state at translation time. */ 80 struct DisasContext { 81 DisasContextBase base; 82 83 CPUAVRState *env; 84 CPUState *cs; 85 86 target_long npc; 87 uint32_t opcode; 88 89 /* Routine used to access memory */ 90 int memidx; 91 92 /* 93 * some AVR instructions can make the following instruction to be skipped 94 * Let's name those instructions 95 * A - instruction that can skip the next one 96 * B - instruction that can be skipped. this depends on execution of A 97 * there are two scenarios 98 * 1. A and B belong to the same translation block 99 * 2. A is the last instruction in the translation block and B is the last 100 * 101 * following variables are used to simplify the skipping logic, they are 102 * used in the following manner (sketch) 103 * 104 * TCGLabel *skip_label = NULL; 105 * if (ctx->skip_cond != TCG_COND_NEVER) { 106 * skip_label = gen_new_label(); 107 * tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label); 108 * } 109 * 110 * translate(ctx); 111 * 112 * if (skip_label) { 113 * gen_set_label(skip_label); 114 * } 115 */ 116 TCGv skip_var0; 117 TCGv skip_var1; 118 TCGCond skip_cond; 119 }; 120 121 void avr_cpu_tcg_init(void) 122 { 123 int i; 124 125 #define AVR_REG_OFFS(x) offsetof(CPUAVRState, x) 126 cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc"); 127 cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf"); 128 cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf"); 129 cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf"); 130 cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf"); 131 cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf"); 132 cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf"); 133 cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf"); 134 cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If"); 135 cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD"); 136 cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX"); 137 cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY"); 138 cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ"); 139 cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind"); 140 cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp"); 141 cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip"); 142 143 for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) { 144 cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]), 145 reg_names[i]); 146 } 147 #undef AVR_REG_OFFS 148 } 149 150 static int to_regs_16_31_by_one(DisasContext *ctx, int indx) 151 { 152 return 16 + (indx % 16); 153 } 154 155 static int to_regs_16_23_by_one(DisasContext *ctx, int indx) 156 { 157 return 16 + (indx % 8); 158 } 159 160 static int to_regs_24_30_by_two(DisasContext *ctx, int indx) 161 { 162 return 24 + (indx % 4) * 2; 163 } 164 165 static int to_regs_00_30_by_two(DisasContext *ctx, int indx) 166 { 167 return (indx % 16) * 2; 168 } 169 170 static uint16_t next_word(DisasContext *ctx) 171 { 172 return cpu_lduw_code(ctx->env, ctx->npc++ * 2); 173 } 174 175 static int append_16(DisasContext *ctx, int x) 176 { 177 return x << 16 | next_word(ctx); 178 } 179 180 static bool avr_have_feature(DisasContext *ctx, int feature) 181 { 182 if (!avr_feature(ctx->env, feature)) { 183 gen_helper_unsupported(cpu_env); 184 ctx->base.is_jmp = DISAS_NORETURN; 185 return false; 186 } 187 return true; 188 } 189 190 static bool decode_insn(DisasContext *ctx, uint16_t insn); 191 #include "decode-insn.c.inc" 192 193 /* 194 * Arithmetic Instructions 195 */ 196 197 /* 198 * Utility functions for updating status registers: 199 * 200 * - gen_add_CHf() 201 * - gen_add_Vf() 202 * - gen_sub_CHf() 203 * - gen_sub_Vf() 204 * - gen_NSf() 205 * - gen_ZNSf() 206 * 207 */ 208 209 static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr) 210 { 211 TCGv t1 = tcg_temp_new_i32(); 212 TCGv t2 = tcg_temp_new_i32(); 213 TCGv t3 = tcg_temp_new_i32(); 214 215 tcg_gen_and_tl(t1, Rd, Rr); /* t1 = Rd & Rr */ 216 tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd & ~R */ 217 tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr & ~R */ 218 tcg_gen_or_tl(t1, t1, t2); /* t1 = t1 | t2 | t3 */ 219 tcg_gen_or_tl(t1, t1, t3); 220 221 tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */ 222 tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */ 223 tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1); 224 225 tcg_temp_free_i32(t3); 226 tcg_temp_free_i32(t2); 227 tcg_temp_free_i32(t1); 228 } 229 230 static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr) 231 { 232 TCGv t1 = tcg_temp_new_i32(); 233 TCGv t2 = tcg_temp_new_i32(); 234 235 /* t1 = Rd & Rr & ~R | ~Rd & ~Rr & R */ 236 /* = (Rd ^ R) & ~(Rd ^ Rr) */ 237 tcg_gen_xor_tl(t1, Rd, R); 238 tcg_gen_xor_tl(t2, Rd, Rr); 239 tcg_gen_andc_tl(t1, t1, t2); 240 241 tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */ 242 243 tcg_temp_free_i32(t2); 244 tcg_temp_free_i32(t1); 245 } 246 247 static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr) 248 { 249 TCGv t1 = tcg_temp_new_i32(); 250 TCGv t2 = tcg_temp_new_i32(); 251 TCGv t3 = tcg_temp_new_i32(); 252 253 tcg_gen_not_tl(t1, Rd); /* t1 = ~Rd */ 254 tcg_gen_and_tl(t2, t1, Rr); /* t2 = ~Rd & Rr */ 255 tcg_gen_or_tl(t3, t1, Rr); /* t3 = (~Rd | Rr) & R */ 256 tcg_gen_and_tl(t3, t3, R); 257 tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */ 258 259 tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */ 260 tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */ 261 tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1); 262 263 tcg_temp_free_i32(t3); 264 tcg_temp_free_i32(t2); 265 tcg_temp_free_i32(t1); 266 } 267 268 static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr) 269 { 270 TCGv t1 = tcg_temp_new_i32(); 271 TCGv t2 = tcg_temp_new_i32(); 272 273 /* t1 = Rd & ~Rr & ~R | ~Rd & Rr & R */ 274 /* = (Rd ^ R) & (Rd ^ R) */ 275 tcg_gen_xor_tl(t1, Rd, R); 276 tcg_gen_xor_tl(t2, Rd, Rr); 277 tcg_gen_and_tl(t1, t1, t2); 278 279 tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */ 280 281 tcg_temp_free_i32(t2); 282 tcg_temp_free_i32(t1); 283 } 284 285 static void gen_NSf(TCGv R) 286 { 287 tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 288 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 289 } 290 291 static void gen_ZNSf(TCGv R) 292 { 293 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 294 295 /* update status register */ 296 tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 297 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 298 } 299 300 /* 301 * Adds two registers without the C Flag and places the result in the 302 * destination register Rd. 303 */ 304 static bool trans_ADD(DisasContext *ctx, arg_ADD *a) 305 { 306 TCGv Rd = cpu_r[a->rd]; 307 TCGv Rr = cpu_r[a->rr]; 308 TCGv R = tcg_temp_new_i32(); 309 310 tcg_gen_add_tl(R, Rd, Rr); /* Rd = Rd + Rr */ 311 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 312 313 /* update status register */ 314 gen_add_CHf(R, Rd, Rr); 315 gen_add_Vf(R, Rd, Rr); 316 gen_ZNSf(R); 317 318 /* update output registers */ 319 tcg_gen_mov_tl(Rd, R); 320 321 tcg_temp_free_i32(R); 322 323 return true; 324 } 325 326 /* 327 * Adds two registers and the contents of the C Flag and places the result in 328 * the destination register Rd. 329 */ 330 static bool trans_ADC(DisasContext *ctx, arg_ADC *a) 331 { 332 TCGv Rd = cpu_r[a->rd]; 333 TCGv Rr = cpu_r[a->rr]; 334 TCGv R = tcg_temp_new_i32(); 335 336 tcg_gen_add_tl(R, Rd, Rr); /* R = Rd + Rr + Cf */ 337 tcg_gen_add_tl(R, R, cpu_Cf); 338 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 339 340 /* update status register */ 341 gen_add_CHf(R, Rd, Rr); 342 gen_add_Vf(R, Rd, Rr); 343 gen_ZNSf(R); 344 345 /* update output registers */ 346 tcg_gen_mov_tl(Rd, R); 347 348 tcg_temp_free_i32(R); 349 350 return true; 351 } 352 353 /* 354 * Adds an immediate value (0 - 63) to a register pair and places the result 355 * in the register pair. This instruction operates on the upper four register 356 * pairs, and is well suited for operations on the pointer registers. This 357 * instruction is not available in all devices. Refer to the device specific 358 * instruction set summary. 359 */ 360 static bool trans_ADIW(DisasContext *ctx, arg_ADIW *a) 361 { 362 if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) { 363 return true; 364 } 365 366 TCGv RdL = cpu_r[a->rd]; 367 TCGv RdH = cpu_r[a->rd + 1]; 368 int Imm = (a->imm); 369 TCGv R = tcg_temp_new_i32(); 370 TCGv Rd = tcg_temp_new_i32(); 371 372 tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */ 373 tcg_gen_addi_tl(R, Rd, Imm); /* R = Rd + Imm */ 374 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 375 376 /* update status register */ 377 tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */ 378 tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15); 379 tcg_gen_andc_tl(cpu_Vf, R, Rd); /* Vf = R & ~Rd */ 380 tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15); 381 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 382 tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */ 383 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf);/* Sf = Nf ^ Vf */ 384 385 /* update output registers */ 386 tcg_gen_andi_tl(RdL, R, 0xff); 387 tcg_gen_shri_tl(RdH, R, 8); 388 389 tcg_temp_free_i32(Rd); 390 tcg_temp_free_i32(R); 391 392 return true; 393 } 394 395 /* 396 * Subtracts two registers and places the result in the destination 397 * register Rd. 398 */ 399 static bool trans_SUB(DisasContext *ctx, arg_SUB *a) 400 { 401 TCGv Rd = cpu_r[a->rd]; 402 TCGv Rr = cpu_r[a->rr]; 403 TCGv R = tcg_temp_new_i32(); 404 405 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 406 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 407 408 /* update status register */ 409 tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */ 410 gen_sub_CHf(R, Rd, Rr); 411 gen_sub_Vf(R, Rd, Rr); 412 gen_ZNSf(R); 413 414 /* update output registers */ 415 tcg_gen_mov_tl(Rd, R); 416 417 tcg_temp_free_i32(R); 418 419 return true; 420 } 421 422 /* 423 * Subtracts a register and a constant and places the result in the 424 * destination register Rd. This instruction is working on Register R16 to R31 425 * and is very well suited for operations on the X, Y, and Z-pointers. 426 */ 427 static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a) 428 { 429 TCGv Rd = cpu_r[a->rd]; 430 TCGv Rr = tcg_const_i32(a->imm); 431 TCGv R = tcg_temp_new_i32(); 432 433 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */ 434 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 435 436 /* update status register */ 437 gen_sub_CHf(R, Rd, Rr); 438 gen_sub_Vf(R, Rd, Rr); 439 gen_ZNSf(R); 440 441 /* update output registers */ 442 tcg_gen_mov_tl(Rd, R); 443 444 tcg_temp_free_i32(R); 445 tcg_temp_free_i32(Rr); 446 447 return true; 448 } 449 450 /* 451 * Subtracts two registers and subtracts with the C Flag and places the 452 * result in the destination register Rd. 453 */ 454 static bool trans_SBC(DisasContext *ctx, arg_SBC *a) 455 { 456 TCGv Rd = cpu_r[a->rd]; 457 TCGv Rr = cpu_r[a->rr]; 458 TCGv R = tcg_temp_new_i32(); 459 TCGv zero = tcg_const_i32(0); 460 461 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 462 tcg_gen_sub_tl(R, R, cpu_Cf); 463 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 464 465 /* update status register */ 466 gen_sub_CHf(R, Rd, Rr); 467 gen_sub_Vf(R, Rd, Rr); 468 gen_NSf(R); 469 470 /* 471 * Previous value remains unchanged when the result is zero; 472 * cleared otherwise. 473 */ 474 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 475 476 /* update output registers */ 477 tcg_gen_mov_tl(Rd, R); 478 479 tcg_temp_free_i32(zero); 480 tcg_temp_free_i32(R); 481 482 return true; 483 } 484 485 /* 486 * SBCI -- Subtract Immediate with Carry 487 */ 488 static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a) 489 { 490 TCGv Rd = cpu_r[a->rd]; 491 TCGv Rr = tcg_const_i32(a->imm); 492 TCGv R = tcg_temp_new_i32(); 493 TCGv zero = tcg_const_i32(0); 494 495 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 496 tcg_gen_sub_tl(R, R, cpu_Cf); 497 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 498 499 /* update status register */ 500 gen_sub_CHf(R, Rd, Rr); 501 gen_sub_Vf(R, Rd, Rr); 502 gen_NSf(R); 503 504 /* 505 * Previous value remains unchanged when the result is zero; 506 * cleared otherwise. 507 */ 508 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 509 510 /* update output registers */ 511 tcg_gen_mov_tl(Rd, R); 512 513 tcg_temp_free_i32(zero); 514 tcg_temp_free_i32(R); 515 tcg_temp_free_i32(Rr); 516 517 return true; 518 } 519 520 /* 521 * Subtracts an immediate value (0-63) from a register pair and places the 522 * result in the register pair. This instruction operates on the upper four 523 * register pairs, and is well suited for operations on the Pointer Registers. 524 * This instruction is not available in all devices. Refer to the device 525 * specific instruction set summary. 526 */ 527 static bool trans_SBIW(DisasContext *ctx, arg_SBIW *a) 528 { 529 if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) { 530 return true; 531 } 532 533 TCGv RdL = cpu_r[a->rd]; 534 TCGv RdH = cpu_r[a->rd + 1]; 535 int Imm = (a->imm); 536 TCGv R = tcg_temp_new_i32(); 537 TCGv Rd = tcg_temp_new_i32(); 538 539 tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */ 540 tcg_gen_subi_tl(R, Rd, Imm); /* R = Rd - Imm */ 541 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 542 543 /* update status register */ 544 tcg_gen_andc_tl(cpu_Cf, R, Rd); 545 tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15); /* Cf = R & ~Rd */ 546 tcg_gen_andc_tl(cpu_Vf, Rd, R); 547 tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15); /* Vf = Rd & ~R */ 548 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 549 tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */ 550 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 551 552 /* update output registers */ 553 tcg_gen_andi_tl(RdL, R, 0xff); 554 tcg_gen_shri_tl(RdH, R, 8); 555 556 tcg_temp_free_i32(Rd); 557 tcg_temp_free_i32(R); 558 559 return true; 560 } 561 562 /* 563 * Performs the logical AND between the contents of register Rd and register 564 * Rr and places the result in the destination register Rd. 565 */ 566 static bool trans_AND(DisasContext *ctx, arg_AND *a) 567 { 568 TCGv Rd = cpu_r[a->rd]; 569 TCGv Rr = cpu_r[a->rr]; 570 TCGv R = tcg_temp_new_i32(); 571 572 tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */ 573 574 /* update status register */ 575 tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */ 576 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 577 gen_ZNSf(R); 578 579 /* update output registers */ 580 tcg_gen_mov_tl(Rd, R); 581 582 tcg_temp_free_i32(R); 583 584 return true; 585 } 586 587 /* 588 * Performs the logical AND between the contents of register Rd and a constant 589 * and places the result in the destination register Rd. 590 */ 591 static bool trans_ANDI(DisasContext *ctx, arg_ANDI *a) 592 { 593 TCGv Rd = cpu_r[a->rd]; 594 int Imm = (a->imm); 595 596 tcg_gen_andi_tl(Rd, Rd, Imm); /* Rd = Rd & Imm */ 597 598 /* update status register */ 599 tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */ 600 gen_ZNSf(Rd); 601 602 return true; 603 } 604 605 /* 606 * Performs the logical OR between the contents of register Rd and register 607 * Rr and places the result in the destination register Rd. 608 */ 609 static bool trans_OR(DisasContext *ctx, arg_OR *a) 610 { 611 TCGv Rd = cpu_r[a->rd]; 612 TCGv Rr = cpu_r[a->rr]; 613 TCGv R = tcg_temp_new_i32(); 614 615 tcg_gen_or_tl(R, Rd, Rr); 616 617 /* update status register */ 618 tcg_gen_movi_tl(cpu_Vf, 0); 619 gen_ZNSf(R); 620 621 /* update output registers */ 622 tcg_gen_mov_tl(Rd, R); 623 624 tcg_temp_free_i32(R); 625 626 return true; 627 } 628 629 /* 630 * Performs the logical OR between the contents of register Rd and a 631 * constant and places the result in the destination register Rd. 632 */ 633 static bool trans_ORI(DisasContext *ctx, arg_ORI *a) 634 { 635 TCGv Rd = cpu_r[a->rd]; 636 int Imm = (a->imm); 637 638 tcg_gen_ori_tl(Rd, Rd, Imm); /* Rd = Rd | Imm */ 639 640 /* update status register */ 641 tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */ 642 gen_ZNSf(Rd); 643 644 return true; 645 } 646 647 /* 648 * Performs the logical EOR between the contents of register Rd and 649 * register Rr and places the result in the destination register Rd. 650 */ 651 static bool trans_EOR(DisasContext *ctx, arg_EOR *a) 652 { 653 TCGv Rd = cpu_r[a->rd]; 654 TCGv Rr = cpu_r[a->rr]; 655 656 tcg_gen_xor_tl(Rd, Rd, Rr); 657 658 /* update status register */ 659 tcg_gen_movi_tl(cpu_Vf, 0); 660 gen_ZNSf(Rd); 661 662 return true; 663 } 664 665 /* 666 * Clears the specified bits in register Rd. Performs the logical AND 667 * between the contents of register Rd and the complement of the constant mask 668 * K. The result will be placed in register Rd. 669 */ 670 static bool trans_COM(DisasContext *ctx, arg_COM *a) 671 { 672 TCGv Rd = cpu_r[a->rd]; 673 TCGv R = tcg_temp_new_i32(); 674 675 tcg_gen_xori_tl(Rd, Rd, 0xff); 676 677 /* update status register */ 678 tcg_gen_movi_tl(cpu_Cf, 1); /* Cf = 1 */ 679 tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */ 680 gen_ZNSf(Rd); 681 682 tcg_temp_free_i32(R); 683 684 return true; 685 } 686 687 /* 688 * Replaces the contents of register Rd with its two's complement; the 689 * value $80 is left unchanged. 690 */ 691 static bool trans_NEG(DisasContext *ctx, arg_NEG *a) 692 { 693 TCGv Rd = cpu_r[a->rd]; 694 TCGv t0 = tcg_const_i32(0); 695 TCGv R = tcg_temp_new_i32(); 696 697 tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */ 698 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 699 700 /* update status register */ 701 gen_sub_CHf(R, t0, Rd); 702 gen_sub_Vf(R, t0, Rd); 703 gen_ZNSf(R); 704 705 /* update output registers */ 706 tcg_gen_mov_tl(Rd, R); 707 708 tcg_temp_free_i32(t0); 709 tcg_temp_free_i32(R); 710 711 return true; 712 } 713 714 /* 715 * Adds one -1- to the contents of register Rd and places the result in the 716 * destination register Rd. The C Flag in SREG is not affected by the 717 * operation, thus allowing the INC instruction to be used on a loop counter in 718 * multiple-precision computations. When operating on unsigned numbers, only 719 * BREQ and BRNE branches can be expected to perform consistently. When 720 * operating on two's complement values, all signed branches are available. 721 */ 722 static bool trans_INC(DisasContext *ctx, arg_INC *a) 723 { 724 TCGv Rd = cpu_r[a->rd]; 725 726 tcg_gen_addi_tl(Rd, Rd, 1); 727 tcg_gen_andi_tl(Rd, Rd, 0xff); 728 729 /* update status register */ 730 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x80); /* Vf = Rd == 0x80 */ 731 gen_ZNSf(Rd); 732 733 return true; 734 } 735 736 /* 737 * Subtracts one -1- from the contents of register Rd and places the result 738 * in the destination register Rd. The C Flag in SREG is not affected by the 739 * operation, thus allowing the DEC instruction to be used on a loop counter in 740 * multiple-precision computations. When operating on unsigned values, only 741 * BREQ and BRNE branches can be expected to perform consistently. When 742 * operating on two's complement values, all signed branches are available. 743 */ 744 static bool trans_DEC(DisasContext *ctx, arg_DEC *a) 745 { 746 TCGv Rd = cpu_r[a->rd]; 747 748 tcg_gen_subi_tl(Rd, Rd, 1); /* Rd = Rd - 1 */ 749 tcg_gen_andi_tl(Rd, Rd, 0xff); /* make it 8 bits */ 750 751 /* update status register */ 752 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x7f); /* Vf = Rd == 0x7f */ 753 gen_ZNSf(Rd); 754 755 return true; 756 } 757 758 /* 759 * This instruction performs 8-bit x 8-bit -> 16-bit unsigned multiplication. 760 */ 761 static bool trans_MUL(DisasContext *ctx, arg_MUL *a) 762 { 763 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 764 return true; 765 } 766 767 TCGv R0 = cpu_r[0]; 768 TCGv R1 = cpu_r[1]; 769 TCGv Rd = cpu_r[a->rd]; 770 TCGv Rr = cpu_r[a->rr]; 771 TCGv R = tcg_temp_new_i32(); 772 773 tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd * Rr */ 774 tcg_gen_andi_tl(R0, R, 0xff); 775 tcg_gen_shri_tl(R1, R, 8); 776 777 /* update status register */ 778 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 779 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 780 781 tcg_temp_free_i32(R); 782 783 return true; 784 } 785 786 /* 787 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication. 788 */ 789 static bool trans_MULS(DisasContext *ctx, arg_MULS *a) 790 { 791 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 792 return true; 793 } 794 795 TCGv R0 = cpu_r[0]; 796 TCGv R1 = cpu_r[1]; 797 TCGv Rd = cpu_r[a->rd]; 798 TCGv Rr = cpu_r[a->rr]; 799 TCGv R = tcg_temp_new_i32(); 800 TCGv t0 = tcg_temp_new_i32(); 801 TCGv t1 = tcg_temp_new_i32(); 802 803 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 804 tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */ 805 tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */ 806 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 807 tcg_gen_andi_tl(R0, R, 0xff); 808 tcg_gen_shri_tl(R1, R, 8); 809 810 /* update status register */ 811 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 812 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 813 814 tcg_temp_free_i32(t1); 815 tcg_temp_free_i32(t0); 816 tcg_temp_free_i32(R); 817 818 return true; 819 } 820 821 /* 822 * This instruction performs 8-bit x 8-bit -> 16-bit multiplication of a 823 * signed and an unsigned number. 824 */ 825 static bool trans_MULSU(DisasContext *ctx, arg_MULSU *a) 826 { 827 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 828 return true; 829 } 830 831 TCGv R0 = cpu_r[0]; 832 TCGv R1 = cpu_r[1]; 833 TCGv Rd = cpu_r[a->rd]; 834 TCGv Rr = cpu_r[a->rr]; 835 TCGv R = tcg_temp_new_i32(); 836 TCGv t0 = tcg_temp_new_i32(); 837 838 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 839 tcg_gen_mul_tl(R, t0, Rr); /* R = Rd * Rr */ 840 tcg_gen_andi_tl(R, R, 0xffff); /* make R 16 bits */ 841 tcg_gen_andi_tl(R0, R, 0xff); 842 tcg_gen_shri_tl(R1, R, 8); 843 844 /* update status register */ 845 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 846 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 847 848 tcg_temp_free_i32(t0); 849 tcg_temp_free_i32(R); 850 851 return true; 852 } 853 854 /* 855 * This instruction performs 8-bit x 8-bit -> 16-bit unsigned 856 * multiplication and shifts the result one bit left. 857 */ 858 static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a) 859 { 860 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 861 return true; 862 } 863 864 TCGv R0 = cpu_r[0]; 865 TCGv R1 = cpu_r[1]; 866 TCGv Rd = cpu_r[a->rd]; 867 TCGv Rr = cpu_r[a->rr]; 868 TCGv R = tcg_temp_new_i32(); 869 870 tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd * Rr */ 871 872 /* update status register */ 873 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 874 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 875 876 /* update output registers */ 877 tcg_gen_shli_tl(R, R, 1); 878 tcg_gen_andi_tl(R0, R, 0xff); 879 tcg_gen_shri_tl(R1, R, 8); 880 tcg_gen_andi_tl(R1, R1, 0xff); 881 882 883 tcg_temp_free_i32(R); 884 885 return true; 886 } 887 888 /* 889 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication 890 * and shifts the result one bit left. 891 */ 892 static bool trans_FMULS(DisasContext *ctx, arg_FMULS *a) 893 { 894 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 895 return true; 896 } 897 898 TCGv R0 = cpu_r[0]; 899 TCGv R1 = cpu_r[1]; 900 TCGv Rd = cpu_r[a->rd]; 901 TCGv Rr = cpu_r[a->rr]; 902 TCGv R = tcg_temp_new_i32(); 903 TCGv t0 = tcg_temp_new_i32(); 904 TCGv t1 = tcg_temp_new_i32(); 905 906 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 907 tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */ 908 tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */ 909 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 910 911 /* update status register */ 912 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 913 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 914 915 /* update output registers */ 916 tcg_gen_shli_tl(R, R, 1); 917 tcg_gen_andi_tl(R0, R, 0xff); 918 tcg_gen_shri_tl(R1, R, 8); 919 tcg_gen_andi_tl(R1, R1, 0xff); 920 921 tcg_temp_free_i32(t1); 922 tcg_temp_free_i32(t0); 923 tcg_temp_free_i32(R); 924 925 return true; 926 } 927 928 /* 929 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication 930 * and shifts the result one bit left. 931 */ 932 static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU *a) 933 { 934 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 935 return true; 936 } 937 938 TCGv R0 = cpu_r[0]; 939 TCGv R1 = cpu_r[1]; 940 TCGv Rd = cpu_r[a->rd]; 941 TCGv Rr = cpu_r[a->rr]; 942 TCGv R = tcg_temp_new_i32(); 943 TCGv t0 = tcg_temp_new_i32(); 944 945 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 946 tcg_gen_mul_tl(R, t0, Rr); /* R = Rd * Rr */ 947 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 948 949 /* update status register */ 950 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 951 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 952 953 /* update output registers */ 954 tcg_gen_shli_tl(R, R, 1); 955 tcg_gen_andi_tl(R0, R, 0xff); 956 tcg_gen_shri_tl(R1, R, 8); 957 tcg_gen_andi_tl(R1, R1, 0xff); 958 959 tcg_temp_free_i32(t0); 960 tcg_temp_free_i32(R); 961 962 return true; 963 } 964 965 /* 966 * The module is an instruction set extension to the AVR CPU, performing 967 * DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in 968 * the CPU register file, registers R0-R7, where LSB of data is placed in LSB 969 * of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (including 970 * parity bits) is placed in registers R8- R15, organized in the register file 971 * with LSB of key in LSB of R8 and MSB of key in MSB of R15. Executing one DES 972 * instruction performs one round in the DES algorithm. Sixteen rounds must be 973 * executed in increasing order to form the correct DES ciphertext or 974 * plaintext. Intermediate results are stored in the register file (R0-R15) 975 * after each DES instruction. The instruction's operand (K) determines which 976 * round is executed, and the half carry flag (H) determines whether encryption 977 * or decryption is performed. The DES algorithm is described in 978 * "Specifications for the Data Encryption Standard" (Federal Information 979 * Processing Standards Publication 46). Intermediate results in this 980 * implementation differ from the standard because the initial permutation and 981 * the inverse initial permutation are performed each iteration. This does not 982 * affect the result in the final ciphertext or plaintext, but reduces 983 * execution time. 984 */ 985 static bool trans_DES(DisasContext *ctx, arg_DES *a) 986 { 987 /* TODO */ 988 if (!avr_have_feature(ctx, AVR_FEATURE_DES)) { 989 return true; 990 } 991 992 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); 993 994 return true; 995 } 996 997 /* 998 * Branch Instructions 999 */ 1000 static void gen_jmp_ez(DisasContext *ctx) 1001 { 1002 tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8); 1003 tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind); 1004 ctx->base.is_jmp = DISAS_LOOKUP; 1005 } 1006 1007 static void gen_jmp_z(DisasContext *ctx) 1008 { 1009 tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8); 1010 ctx->base.is_jmp = DISAS_LOOKUP; 1011 } 1012 1013 static void gen_push_ret(DisasContext *ctx, int ret) 1014 { 1015 if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { 1016 1017 TCGv t0 = tcg_const_i32((ret & 0x0000ff)); 1018 1019 tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB); 1020 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1021 1022 tcg_temp_free_i32(t0); 1023 } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { 1024 1025 TCGv t0 = tcg_const_i32((ret & 0x00ffff)); 1026 1027 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1028 tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1029 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1030 1031 tcg_temp_free_i32(t0); 1032 1033 } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { 1034 1035 TCGv lo = tcg_const_i32((ret & 0x0000ff)); 1036 TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8); 1037 1038 tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); 1039 tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); 1040 tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1041 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1042 1043 tcg_temp_free_i32(lo); 1044 tcg_temp_free_i32(hi); 1045 } 1046 } 1047 1048 static void gen_pop_ret(DisasContext *ctx, TCGv ret) 1049 { 1050 if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { 1051 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1052 tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB); 1053 } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { 1054 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1055 tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1056 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1057 } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { 1058 TCGv lo = tcg_temp_new_i32(); 1059 TCGv hi = tcg_temp_new_i32(); 1060 1061 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1062 tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1063 1064 tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); 1065 tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); 1066 1067 tcg_gen_deposit_tl(ret, lo, hi, 8, 16); 1068 1069 tcg_temp_free_i32(lo); 1070 tcg_temp_free_i32(hi); 1071 } 1072 } 1073 1074 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 1075 { 1076 const TranslationBlock *tb = ctx->base.tb; 1077 1078 if (translator_use_goto_tb(&ctx->base, dest)) { 1079 tcg_gen_goto_tb(n); 1080 tcg_gen_movi_i32(cpu_pc, dest); 1081 tcg_gen_exit_tb(tb, n); 1082 } else { 1083 tcg_gen_movi_i32(cpu_pc, dest); 1084 tcg_gen_lookup_and_goto_ptr(); 1085 } 1086 ctx->base.is_jmp = DISAS_NORETURN; 1087 } 1088 1089 /* 1090 * Relative jump to an address within PC - 2K +1 and PC + 2K (words). For 1091 * AVR microcontrollers with Program memory not exceeding 4K words (8KB) this 1092 * instruction can address the entire memory from every address location. See 1093 * also JMP. 1094 */ 1095 static bool trans_RJMP(DisasContext *ctx, arg_RJMP *a) 1096 { 1097 int dst = ctx->npc + a->imm; 1098 1099 gen_goto_tb(ctx, 0, dst); 1100 1101 return true; 1102 } 1103 1104 /* 1105 * Indirect jump to the address pointed to by the Z (16 bits) Pointer 1106 * Register in the Register File. The Z-pointer Register is 16 bits wide and 1107 * allows jump within the lowest 64K words (128KB) section of Program memory. 1108 * This instruction is not available in all devices. Refer to the device 1109 * specific instruction set summary. 1110 */ 1111 static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a) 1112 { 1113 if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) { 1114 return true; 1115 } 1116 1117 gen_jmp_z(ctx); 1118 1119 return true; 1120 } 1121 1122 /* 1123 * Indirect jump to the address pointed to by the Z (16 bits) Pointer 1124 * Register in the Register File and the EIND Register in the I/O space. This 1125 * instruction allows for indirect jumps to the entire 4M (words) Program 1126 * memory space. See also IJMP. This instruction is not available in all 1127 * devices. Refer to the device specific instruction set summary. 1128 */ 1129 static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a) 1130 { 1131 if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) { 1132 return true; 1133 } 1134 1135 gen_jmp_ez(ctx); 1136 return true; 1137 } 1138 1139 /* 1140 * Jump to an address within the entire 4M (words) Program memory. See also 1141 * RJMP. This instruction is not available in all devices. Refer to the device 1142 * specific instruction set summary.0 1143 */ 1144 static bool trans_JMP(DisasContext *ctx, arg_JMP *a) 1145 { 1146 if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) { 1147 return true; 1148 } 1149 1150 gen_goto_tb(ctx, 0, a->imm); 1151 1152 return true; 1153 } 1154 1155 /* 1156 * Relative call to an address within PC - 2K + 1 and PC + 2K (words). The 1157 * return address (the instruction after the RCALL) is stored onto the Stack. 1158 * See also CALL. For AVR microcontrollers with Program memory not exceeding 4K 1159 * words (8KB) this instruction can address the entire memory from every 1160 * address location. The Stack Pointer uses a post-decrement scheme during 1161 * RCALL. 1162 */ 1163 static bool trans_RCALL(DisasContext *ctx, arg_RCALL *a) 1164 { 1165 int ret = ctx->npc; 1166 int dst = ctx->npc + a->imm; 1167 1168 gen_push_ret(ctx, ret); 1169 gen_goto_tb(ctx, 0, dst); 1170 1171 return true; 1172 } 1173 1174 /* 1175 * Calls to a subroutine within the entire 4M (words) Program memory. The 1176 * return address (to the instruction after the CALL) will be stored onto the 1177 * Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during 1178 * CALL. This instruction is not available in all devices. Refer to the device 1179 * specific instruction set summary. 1180 */ 1181 static bool trans_ICALL(DisasContext *ctx, arg_ICALL *a) 1182 { 1183 if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) { 1184 return true; 1185 } 1186 1187 int ret = ctx->npc; 1188 1189 gen_push_ret(ctx, ret); 1190 gen_jmp_z(ctx); 1191 1192 return true; 1193 } 1194 1195 /* 1196 * Indirect call of a subroutine pointed to by the Z (16 bits) Pointer 1197 * Register in the Register File and the EIND Register in the I/O space. This 1198 * instruction allows for indirect calls to the entire 4M (words) Program 1199 * memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme 1200 * during EICALL. This instruction is not available in all devices. Refer to 1201 * the device specific instruction set summary. 1202 */ 1203 static bool trans_EICALL(DisasContext *ctx, arg_EICALL *a) 1204 { 1205 if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) { 1206 return true; 1207 } 1208 1209 int ret = ctx->npc; 1210 1211 gen_push_ret(ctx, ret); 1212 gen_jmp_ez(ctx); 1213 return true; 1214 } 1215 1216 /* 1217 * Calls to a subroutine within the entire Program memory. The return 1218 * address (to the instruction after the CALL) will be stored onto the Stack. 1219 * (See also RCALL). The Stack Pointer uses a post-decrement scheme during 1220 * CALL. This instruction is not available in all devices. Refer to the device 1221 * specific instruction set summary. 1222 */ 1223 static bool trans_CALL(DisasContext *ctx, arg_CALL *a) 1224 { 1225 if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) { 1226 return true; 1227 } 1228 1229 int Imm = a->imm; 1230 int ret = ctx->npc; 1231 1232 gen_push_ret(ctx, ret); 1233 gen_goto_tb(ctx, 0, Imm); 1234 1235 return true; 1236 } 1237 1238 /* 1239 * Returns from subroutine. The return address is loaded from the STACK. 1240 * The Stack Pointer uses a preincrement scheme during RET. 1241 */ 1242 static bool trans_RET(DisasContext *ctx, arg_RET *a) 1243 { 1244 gen_pop_ret(ctx, cpu_pc); 1245 1246 ctx->base.is_jmp = DISAS_LOOKUP; 1247 return true; 1248 } 1249 1250 /* 1251 * Returns from interrupt. The return address is loaded from the STACK and 1252 * the Global Interrupt Flag is set. Note that the Status Register is not 1253 * automatically stored when entering an interrupt routine, and it is not 1254 * restored when returning from an interrupt routine. This must be handled by 1255 * the application program. The Stack Pointer uses a pre-increment scheme 1256 * during RETI. 1257 */ 1258 static bool trans_RETI(DisasContext *ctx, arg_RETI *a) 1259 { 1260 gen_pop_ret(ctx, cpu_pc); 1261 tcg_gen_movi_tl(cpu_If, 1); 1262 1263 /* Need to return to main loop to re-evaluate interrupts. */ 1264 ctx->base.is_jmp = DISAS_EXIT; 1265 return true; 1266 } 1267 1268 /* 1269 * This instruction performs a compare between two registers Rd and Rr, and 1270 * skips the next instruction if Rd = Rr. 1271 */ 1272 static bool trans_CPSE(DisasContext *ctx, arg_CPSE *a) 1273 { 1274 ctx->skip_cond = TCG_COND_EQ; 1275 ctx->skip_var0 = cpu_r[a->rd]; 1276 ctx->skip_var1 = cpu_r[a->rr]; 1277 return true; 1278 } 1279 1280 /* 1281 * This instruction performs a compare between two registers Rd and Rr. 1282 * None of the registers are changed. All conditional branches can be used 1283 * after this instruction. 1284 */ 1285 static bool trans_CP(DisasContext *ctx, arg_CP *a) 1286 { 1287 TCGv Rd = cpu_r[a->rd]; 1288 TCGv Rr = cpu_r[a->rr]; 1289 TCGv R = tcg_temp_new_i32(); 1290 1291 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 1292 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 1293 1294 /* update status register */ 1295 gen_sub_CHf(R, Rd, Rr); 1296 gen_sub_Vf(R, Rd, Rr); 1297 gen_ZNSf(R); 1298 1299 tcg_temp_free_i32(R); 1300 1301 return true; 1302 } 1303 1304 /* 1305 * This instruction performs a compare between two registers Rd and Rr and 1306 * also takes into account the previous carry. None of the registers are 1307 * changed. All conditional branches can be used after this instruction. 1308 */ 1309 static bool trans_CPC(DisasContext *ctx, arg_CPC *a) 1310 { 1311 TCGv Rd = cpu_r[a->rd]; 1312 TCGv Rr = cpu_r[a->rr]; 1313 TCGv R = tcg_temp_new_i32(); 1314 TCGv zero = tcg_const_i32(0); 1315 1316 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 1317 tcg_gen_sub_tl(R, R, cpu_Cf); 1318 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 1319 /* update status register */ 1320 gen_sub_CHf(R, Rd, Rr); 1321 gen_sub_Vf(R, Rd, Rr); 1322 gen_NSf(R); 1323 1324 /* 1325 * Previous value remains unchanged when the result is zero; 1326 * cleared otherwise. 1327 */ 1328 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 1329 1330 tcg_temp_free_i32(zero); 1331 tcg_temp_free_i32(R); 1332 1333 return true; 1334 } 1335 1336 /* 1337 * This instruction performs a compare between register Rd and a constant. 1338 * The register is not changed. All conditional branches can be used after this 1339 * instruction. 1340 */ 1341 static bool trans_CPI(DisasContext *ctx, arg_CPI *a) 1342 { 1343 TCGv Rd = cpu_r[a->rd]; 1344 int Imm = a->imm; 1345 TCGv Rr = tcg_const_i32(Imm); 1346 TCGv R = tcg_temp_new_i32(); 1347 1348 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 1349 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 1350 1351 /* update status register */ 1352 gen_sub_CHf(R, Rd, Rr); 1353 gen_sub_Vf(R, Rd, Rr); 1354 gen_ZNSf(R); 1355 1356 tcg_temp_free_i32(R); 1357 tcg_temp_free_i32(Rr); 1358 1359 return true; 1360 } 1361 1362 /* 1363 * This instruction tests a single bit in a register and skips the next 1364 * instruction if the bit is cleared. 1365 */ 1366 static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a) 1367 { 1368 TCGv Rr = cpu_r[a->rr]; 1369 1370 ctx->skip_cond = TCG_COND_EQ; 1371 ctx->skip_var0 = tcg_temp_new(); 1372 1373 tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); 1374 return true; 1375 } 1376 1377 /* 1378 * This instruction tests a single bit in a register and skips the next 1379 * instruction if the bit is set. 1380 */ 1381 static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) 1382 { 1383 TCGv Rr = cpu_r[a->rr]; 1384 1385 ctx->skip_cond = TCG_COND_NE; 1386 ctx->skip_var0 = tcg_temp_new(); 1387 1388 tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); 1389 return true; 1390 } 1391 1392 /* 1393 * This instruction tests a single bit in an I/O Register and skips the 1394 * next instruction if the bit is cleared. This instruction operates on the 1395 * lower 32 I/O Registers -- addresses 0-31. 1396 */ 1397 static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) 1398 { 1399 TCGv temp = tcg_const_i32(a->reg); 1400 1401 gen_helper_inb(temp, cpu_env, temp); 1402 tcg_gen_andi_tl(temp, temp, 1 << a->bit); 1403 ctx->skip_cond = TCG_COND_EQ; 1404 ctx->skip_var0 = temp; 1405 1406 return true; 1407 } 1408 1409 /* 1410 * This instruction tests a single bit in an I/O Register and skips the 1411 * next instruction if the bit is set. This instruction operates on the lower 1412 * 32 I/O Registers -- addresses 0-31. 1413 */ 1414 static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) 1415 { 1416 TCGv temp = tcg_const_i32(a->reg); 1417 1418 gen_helper_inb(temp, cpu_env, temp); 1419 tcg_gen_andi_tl(temp, temp, 1 << a->bit); 1420 ctx->skip_cond = TCG_COND_NE; 1421 ctx->skip_var0 = temp; 1422 1423 return true; 1424 } 1425 1426 /* 1427 * Conditional relative branch. Tests a single bit in SREG and branches 1428 * relatively to PC if the bit is cleared. This instruction branches relatively 1429 * to PC in either direction (PC - 63 < = destination <= PC + 64). The 1430 * parameter k is the offset from PC and is represented in two's complement 1431 * form. 1432 */ 1433 static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a) 1434 { 1435 TCGLabel *not_taken = gen_new_label(); 1436 1437 TCGv var; 1438 1439 switch (a->bit) { 1440 case 0x00: 1441 var = cpu_Cf; 1442 break; 1443 case 0x01: 1444 var = cpu_Zf; 1445 break; 1446 case 0x02: 1447 var = cpu_Nf; 1448 break; 1449 case 0x03: 1450 var = cpu_Vf; 1451 break; 1452 case 0x04: 1453 var = cpu_Sf; 1454 break; 1455 case 0x05: 1456 var = cpu_Hf; 1457 break; 1458 case 0x06: 1459 var = cpu_Tf; 1460 break; 1461 case 0x07: 1462 var = cpu_If; 1463 break; 1464 default: 1465 g_assert_not_reached(); 1466 } 1467 1468 tcg_gen_brcondi_i32(TCG_COND_NE, var, 0, not_taken); 1469 gen_goto_tb(ctx, 0, ctx->npc + a->imm); 1470 gen_set_label(not_taken); 1471 1472 ctx->base.is_jmp = DISAS_CHAIN; 1473 return true; 1474 } 1475 1476 /* 1477 * Conditional relative branch. Tests a single bit in SREG and branches 1478 * relatively to PC if the bit is set. This instruction branches relatively to 1479 * PC in either direction (PC - 63 < = destination <= PC + 64). The parameter k 1480 * is the offset from PC and is represented in two's complement form. 1481 */ 1482 static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a) 1483 { 1484 TCGLabel *not_taken = gen_new_label(); 1485 1486 TCGv var; 1487 1488 switch (a->bit) { 1489 case 0x00: 1490 var = cpu_Cf; 1491 break; 1492 case 0x01: 1493 var = cpu_Zf; 1494 break; 1495 case 0x02: 1496 var = cpu_Nf; 1497 break; 1498 case 0x03: 1499 var = cpu_Vf; 1500 break; 1501 case 0x04: 1502 var = cpu_Sf; 1503 break; 1504 case 0x05: 1505 var = cpu_Hf; 1506 break; 1507 case 0x06: 1508 var = cpu_Tf; 1509 break; 1510 case 0x07: 1511 var = cpu_If; 1512 break; 1513 default: 1514 g_assert_not_reached(); 1515 } 1516 1517 tcg_gen_brcondi_i32(TCG_COND_EQ, var, 0, not_taken); 1518 gen_goto_tb(ctx, 0, ctx->npc + a->imm); 1519 gen_set_label(not_taken); 1520 1521 ctx->base.is_jmp = DISAS_CHAIN; 1522 return true; 1523 } 1524 1525 /* 1526 * Data Transfer Instructions 1527 */ 1528 1529 /* 1530 * in the gen_set_addr & gen_get_addr functions 1531 * H assumed to be in 0x00ff0000 format 1532 * M assumed to be in 0x000000ff format 1533 * L assumed to be in 0x000000ff format 1534 */ 1535 static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L) 1536 { 1537 1538 tcg_gen_andi_tl(L, addr, 0x000000ff); 1539 1540 tcg_gen_andi_tl(M, addr, 0x0000ff00); 1541 tcg_gen_shri_tl(M, M, 8); 1542 1543 tcg_gen_andi_tl(H, addr, 0x00ff0000); 1544 } 1545 1546 static void gen_set_xaddr(TCGv addr) 1547 { 1548 gen_set_addr(addr, cpu_rampX, cpu_r[27], cpu_r[26]); 1549 } 1550 1551 static void gen_set_yaddr(TCGv addr) 1552 { 1553 gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]); 1554 } 1555 1556 static void gen_set_zaddr(TCGv addr) 1557 { 1558 gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]); 1559 } 1560 1561 static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L) 1562 { 1563 TCGv addr = tcg_temp_new_i32(); 1564 1565 tcg_gen_deposit_tl(addr, M, H, 8, 8); 1566 tcg_gen_deposit_tl(addr, L, addr, 8, 16); 1567 1568 return addr; 1569 } 1570 1571 static TCGv gen_get_xaddr(void) 1572 { 1573 return gen_get_addr(cpu_rampX, cpu_r[27], cpu_r[26]); 1574 } 1575 1576 static TCGv gen_get_yaddr(void) 1577 { 1578 return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]); 1579 } 1580 1581 static TCGv gen_get_zaddr(void) 1582 { 1583 return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]); 1584 } 1585 1586 /* 1587 * Load one byte indirect from data space to register and stores an clear 1588 * the bits in data space specified by the register. The instruction can only 1589 * be used towards internal SRAM. The data location is pointed to by the Z (16 1590 * bits) Pointer Register in the Register File. Memory access is limited to the 1591 * current data segment of 64KB. To access another data segment in devices with 1592 * more than 64KB data space, the RAMPZ in register in the I/O area has to be 1593 * changed. The Z-pointer Register is left unchanged by the operation. This 1594 * instruction is especially suited for clearing status bits stored in SRAM. 1595 */ 1596 static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) 1597 { 1598 if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { 1599 gen_helper_fullwr(cpu_env, data, addr); 1600 } else { 1601 tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */ 1602 } 1603 } 1604 1605 static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) 1606 { 1607 if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { 1608 gen_helper_fullrd(data, cpu_env, addr); 1609 } else { 1610 tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */ 1611 } 1612 } 1613 1614 /* 1615 * This instruction makes a copy of one register into another. The source 1616 * register Rr is left unchanged, while the destination register Rd is loaded 1617 * with a copy of Rr. 1618 */ 1619 static bool trans_MOV(DisasContext *ctx, arg_MOV *a) 1620 { 1621 TCGv Rd = cpu_r[a->rd]; 1622 TCGv Rr = cpu_r[a->rr]; 1623 1624 tcg_gen_mov_tl(Rd, Rr); 1625 1626 return true; 1627 } 1628 1629 /* 1630 * This instruction makes a copy of one register pair into another register 1631 * pair. The source register pair Rr+1:Rr is left unchanged, while the 1632 * destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr. This 1633 * instruction is not available in all devices. Refer to the device specific 1634 * instruction set summary. 1635 */ 1636 static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a) 1637 { 1638 if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) { 1639 return true; 1640 } 1641 1642 TCGv RdL = cpu_r[a->rd]; 1643 TCGv RdH = cpu_r[a->rd + 1]; 1644 TCGv RrL = cpu_r[a->rr]; 1645 TCGv RrH = cpu_r[a->rr + 1]; 1646 1647 tcg_gen_mov_tl(RdH, RrH); 1648 tcg_gen_mov_tl(RdL, RrL); 1649 1650 return true; 1651 } 1652 1653 /* 1654 * Loads an 8 bit constant directly to register 16 to 31. 1655 */ 1656 static bool trans_LDI(DisasContext *ctx, arg_LDI *a) 1657 { 1658 TCGv Rd = cpu_r[a->rd]; 1659 int imm = a->imm; 1660 1661 tcg_gen_movi_tl(Rd, imm); 1662 1663 return true; 1664 } 1665 1666 /* 1667 * Loads one byte from the data space to a register. For parts with SRAM, 1668 * the data space consists of the Register File, I/O memory and internal SRAM 1669 * (and external SRAM if applicable). For parts without SRAM, the data space 1670 * consists of the register file only. The EEPROM has a separate address space. 1671 * A 16-bit address must be supplied. Memory access is limited to the current 1672 * data segment of 64KB. The LDS instruction uses the RAMPD Register to access 1673 * memory above 64KB. To access another data segment in devices with more than 1674 * 64KB data space, the RAMPD in register in the I/O area has to be changed. 1675 * This instruction is not available in all devices. Refer to the device 1676 * specific instruction set summary. 1677 */ 1678 static bool trans_LDS(DisasContext *ctx, arg_LDS *a) 1679 { 1680 TCGv Rd = cpu_r[a->rd]; 1681 TCGv addr = tcg_temp_new_i32(); 1682 TCGv H = cpu_rampD; 1683 a->imm = next_word(ctx); 1684 1685 tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ 1686 tcg_gen_shli_tl(addr, addr, 16); 1687 tcg_gen_ori_tl(addr, addr, a->imm); 1688 1689 gen_data_load(ctx, Rd, addr); 1690 1691 tcg_temp_free_i32(addr); 1692 1693 return true; 1694 } 1695 1696 /* 1697 * Loads one byte indirect from the data space to a register. For parts 1698 * with SRAM, the data space consists of the Register File, I/O memory and 1699 * internal SRAM (and external SRAM if applicable). For parts without SRAM, the 1700 * data space consists of the Register File only. In some parts the Flash 1701 * Memory has been mapped to the data space and can be read using this command. 1702 * The EEPROM has a separate address space. The data location is pointed to by 1703 * the X (16 bits) Pointer Register in the Register File. Memory access is 1704 * limited to the current data segment of 64KB. To access another data segment 1705 * in devices with more than 64KB data space, the RAMPX in register in the I/O 1706 * area has to be changed. The X-pointer Register can either be left unchanged 1707 * by the operation, or it can be post-incremented or predecremented. These 1708 * features are especially suited for accessing arrays, tables, and Stack 1709 * Pointer usage of the X-pointer Register. Note that only the low byte of the 1710 * X-pointer is updated in devices with no more than 256 bytes data space. For 1711 * such devices, the high byte of the pointer is not used by this instruction 1712 * and can be used for other purposes. The RAMPX Register in the I/O area is 1713 * updated in parts with more than 64KB data space or more than 64KB Program 1714 * memory, and the increment/decrement is added to the entire 24-bit address on 1715 * such devices. Not all variants of this instruction is available in all 1716 * devices. Refer to the device specific instruction set summary. In the 1717 * Reduced Core tinyAVR the LD instruction can be used to achieve the same 1718 * operation as LPM since the program memory is mapped to the data memory 1719 * space. 1720 */ 1721 static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a) 1722 { 1723 TCGv Rd = cpu_r[a->rd]; 1724 TCGv addr = gen_get_xaddr(); 1725 1726 gen_data_load(ctx, Rd, addr); 1727 1728 tcg_temp_free_i32(addr); 1729 1730 return true; 1731 } 1732 1733 static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a) 1734 { 1735 TCGv Rd = cpu_r[a->rd]; 1736 TCGv addr = gen_get_xaddr(); 1737 1738 gen_data_load(ctx, Rd, addr); 1739 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1740 1741 gen_set_xaddr(addr); 1742 1743 tcg_temp_free_i32(addr); 1744 1745 return true; 1746 } 1747 1748 static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a) 1749 { 1750 TCGv Rd = cpu_r[a->rd]; 1751 TCGv addr = gen_get_xaddr(); 1752 1753 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1754 gen_data_load(ctx, Rd, addr); 1755 gen_set_xaddr(addr); 1756 1757 tcg_temp_free_i32(addr); 1758 1759 return true; 1760 } 1761 1762 /* 1763 * Loads one byte indirect with or without displacement from the data space 1764 * to a register. For parts with SRAM, the data space consists of the Register 1765 * File, I/O memory and internal SRAM (and external SRAM if applicable). For 1766 * parts without SRAM, the data space consists of the Register File only. In 1767 * some parts the Flash Memory has been mapped to the data space and can be 1768 * read using this command. The EEPROM has a separate address space. The data 1769 * location is pointed to by the Y (16 bits) Pointer Register in the Register 1770 * File. Memory access is limited to the current data segment of 64KB. To 1771 * access another data segment in devices with more than 64KB data space, the 1772 * RAMPY in register in the I/O area has to be changed. The Y-pointer Register 1773 * can either be left unchanged by the operation, or it can be post-incremented 1774 * or predecremented. These features are especially suited for accessing 1775 * arrays, tables, and Stack Pointer usage of the Y-pointer Register. Note that 1776 * only the low byte of the Y-pointer is updated in devices with no more than 1777 * 256 bytes data space. For such devices, the high byte of the pointer is not 1778 * used by this instruction and can be used for other purposes. The RAMPY 1779 * Register in the I/O area is updated in parts with more than 64KB data space 1780 * or more than 64KB Program memory, and the increment/decrement/displacement 1781 * is added to the entire 24-bit address on such devices. Not all variants of 1782 * this instruction is available in all devices. Refer to the device specific 1783 * instruction set summary. In the Reduced Core tinyAVR the LD instruction can 1784 * be used to achieve the same operation as LPM since the program memory is 1785 * mapped to the data memory space. 1786 */ 1787 static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a) 1788 { 1789 TCGv Rd = cpu_r[a->rd]; 1790 TCGv addr = gen_get_yaddr(); 1791 1792 gen_data_load(ctx, Rd, addr); 1793 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1794 1795 gen_set_yaddr(addr); 1796 1797 tcg_temp_free_i32(addr); 1798 1799 return true; 1800 } 1801 1802 static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a) 1803 { 1804 TCGv Rd = cpu_r[a->rd]; 1805 TCGv addr = gen_get_yaddr(); 1806 1807 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1808 gen_data_load(ctx, Rd, addr); 1809 gen_set_yaddr(addr); 1810 1811 tcg_temp_free_i32(addr); 1812 1813 return true; 1814 } 1815 1816 static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a) 1817 { 1818 TCGv Rd = cpu_r[a->rd]; 1819 TCGv addr = gen_get_yaddr(); 1820 1821 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 1822 gen_data_load(ctx, Rd, addr); 1823 1824 tcg_temp_free_i32(addr); 1825 1826 return true; 1827 } 1828 1829 /* 1830 * Loads one byte indirect with or without displacement from the data space 1831 * to a register. For parts with SRAM, the data space consists of the Register 1832 * File, I/O memory and internal SRAM (and external SRAM if applicable). For 1833 * parts without SRAM, the data space consists of the Register File only. In 1834 * some parts the Flash Memory has been mapped to the data space and can be 1835 * read using this command. The EEPROM has a separate address space. The data 1836 * location is pointed to by the Z (16 bits) Pointer Register in the Register 1837 * File. Memory access is limited to the current data segment of 64KB. To 1838 * access another data segment in devices with more than 64KB data space, the 1839 * RAMPZ in register in the I/O area has to be changed. The Z-pointer Register 1840 * can either be left unchanged by the operation, or it can be post-incremented 1841 * or predecremented. These features are especially suited for Stack Pointer 1842 * usage of the Z-pointer Register, however because the Z-pointer Register can 1843 * be used for indirect subroutine calls, indirect jumps and table lookup, it 1844 * is often more convenient to use the X or Y-pointer as a dedicated Stack 1845 * Pointer. Note that only the low byte of the Z-pointer is updated in devices 1846 * with no more than 256 bytes data space. For such devices, the high byte of 1847 * the pointer is not used by this instruction and can be used for other 1848 * purposes. The RAMPZ Register in the I/O area is updated in parts with more 1849 * than 64KB data space or more than 64KB Program memory, and the 1850 * increment/decrement/displacement is added to the entire 24-bit address on 1851 * such devices. Not all variants of this instruction is available in all 1852 * devices. Refer to the device specific instruction set summary. In the 1853 * Reduced Core tinyAVR the LD instruction can be used to achieve the same 1854 * operation as LPM since the program memory is mapped to the data memory 1855 * space. For using the Z-pointer for table lookup in Program memory see the 1856 * LPM and ELPM instructions. 1857 */ 1858 static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a) 1859 { 1860 TCGv Rd = cpu_r[a->rd]; 1861 TCGv addr = gen_get_zaddr(); 1862 1863 gen_data_load(ctx, Rd, addr); 1864 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1865 1866 gen_set_zaddr(addr); 1867 1868 tcg_temp_free_i32(addr); 1869 1870 return true; 1871 } 1872 1873 static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a) 1874 { 1875 TCGv Rd = cpu_r[a->rd]; 1876 TCGv addr = gen_get_zaddr(); 1877 1878 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1879 gen_data_load(ctx, Rd, addr); 1880 1881 gen_set_zaddr(addr); 1882 1883 tcg_temp_free_i32(addr); 1884 1885 return true; 1886 } 1887 1888 static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a) 1889 { 1890 TCGv Rd = cpu_r[a->rd]; 1891 TCGv addr = gen_get_zaddr(); 1892 1893 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 1894 gen_data_load(ctx, Rd, addr); 1895 1896 tcg_temp_free_i32(addr); 1897 1898 return true; 1899 } 1900 1901 /* 1902 * Stores one byte from a Register to the data space. For parts with SRAM, 1903 * the data space consists of the Register File, I/O memory and internal SRAM 1904 * (and external SRAM if applicable). For parts without SRAM, the data space 1905 * consists of the Register File only. The EEPROM has a separate address space. 1906 * A 16-bit address must be supplied. Memory access is limited to the current 1907 * data segment of 64KB. The STS instruction uses the RAMPD Register to access 1908 * memory above 64KB. To access another data segment in devices with more than 1909 * 64KB data space, the RAMPD in register in the I/O area has to be changed. 1910 * This instruction is not available in all devices. Refer to the device 1911 * specific instruction set summary. 1912 */ 1913 static bool trans_STS(DisasContext *ctx, arg_STS *a) 1914 { 1915 TCGv Rd = cpu_r[a->rd]; 1916 TCGv addr = tcg_temp_new_i32(); 1917 TCGv H = cpu_rampD; 1918 a->imm = next_word(ctx); 1919 1920 tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ 1921 tcg_gen_shli_tl(addr, addr, 16); 1922 tcg_gen_ori_tl(addr, addr, a->imm); 1923 gen_data_store(ctx, Rd, addr); 1924 1925 tcg_temp_free_i32(addr); 1926 1927 return true; 1928 } 1929 1930 /* 1931 * Stores one byte indirect from a register to data space. For parts with SRAM, 1932 * the data space consists of the Register File, I/O memory, and internal SRAM 1933 * (and external SRAM if applicable). For parts without SRAM, the data space 1934 * consists of the Register File only. The EEPROM has a separate address space. 1935 * 1936 * The data location is pointed to by the X (16 bits) Pointer Register in the 1937 * Register File. Memory access is limited to the current data segment of 64KB. 1938 * To access another data segment in devices with more than 64KB data space, the 1939 * RAMPX in register in the I/O area has to be changed. 1940 * 1941 * The X-pointer Register can either be left unchanged by the operation, or it 1942 * can be post-incremented or pre-decremented. These features are especially 1943 * suited for accessing arrays, tables, and Stack Pointer usage of the 1944 * X-pointer Register. Note that only the low byte of the X-pointer is updated 1945 * in devices with no more than 256 bytes data space. For such devices, the high 1946 * byte of the pointer is not used by this instruction and can be used for other 1947 * purposes. The RAMPX Register in the I/O area is updated in parts with more 1948 * than 64KB data space or more than 64KB Program memory, and the increment / 1949 * decrement is added to the entire 24-bit address on such devices. 1950 */ 1951 static bool trans_STX1(DisasContext *ctx, arg_STX1 *a) 1952 { 1953 TCGv Rd = cpu_r[a->rr]; 1954 TCGv addr = gen_get_xaddr(); 1955 1956 gen_data_store(ctx, Rd, addr); 1957 1958 tcg_temp_free_i32(addr); 1959 1960 return true; 1961 } 1962 1963 static bool trans_STX2(DisasContext *ctx, arg_STX2 *a) 1964 { 1965 TCGv Rd = cpu_r[a->rr]; 1966 TCGv addr = gen_get_xaddr(); 1967 1968 gen_data_store(ctx, Rd, addr); 1969 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1970 gen_set_xaddr(addr); 1971 1972 tcg_temp_free_i32(addr); 1973 1974 return true; 1975 } 1976 1977 static bool trans_STX3(DisasContext *ctx, arg_STX3 *a) 1978 { 1979 TCGv Rd = cpu_r[a->rr]; 1980 TCGv addr = gen_get_xaddr(); 1981 1982 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1983 gen_data_store(ctx, Rd, addr); 1984 gen_set_xaddr(addr); 1985 1986 tcg_temp_free_i32(addr); 1987 1988 return true; 1989 } 1990 1991 /* 1992 * Stores one byte indirect with or without displacement from a register to data 1993 * space. For parts with SRAM, the data space consists of the Register File, I/O 1994 * memory, and internal SRAM (and external SRAM if applicable). For parts 1995 * without SRAM, the data space consists of the Register File only. The EEPROM 1996 * has a separate address space. 1997 * 1998 * The data location is pointed to by the Y (16 bits) Pointer Register in the 1999 * Register File. Memory access is limited to the current data segment of 64KB. 2000 * To access another data segment in devices with more than 64KB data space, the 2001 * RAMPY in register in the I/O area has to be changed. 2002 * 2003 * The Y-pointer Register can either be left unchanged by the operation, or it 2004 * can be post-incremented or pre-decremented. These features are especially 2005 * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer 2006 * Register. Note that only the low byte of the Y-pointer is updated in devices 2007 * with no more than 256 bytes data space. For such devices, the high byte of 2008 * the pointer is not used by this instruction and can be used for other 2009 * purposes. The RAMPY Register in the I/O area is updated in parts with more 2010 * than 64KB data space or more than 64KB Program memory, and the increment / 2011 * decrement / displacement is added to the entire 24-bit address on such 2012 * devices. 2013 */ 2014 static bool trans_STY2(DisasContext *ctx, arg_STY2 *a) 2015 { 2016 TCGv Rd = cpu_r[a->rd]; 2017 TCGv addr = gen_get_yaddr(); 2018 2019 gen_data_store(ctx, Rd, addr); 2020 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2021 gen_set_yaddr(addr); 2022 2023 tcg_temp_free_i32(addr); 2024 2025 return true; 2026 } 2027 2028 static bool trans_STY3(DisasContext *ctx, arg_STY3 *a) 2029 { 2030 TCGv Rd = cpu_r[a->rd]; 2031 TCGv addr = gen_get_yaddr(); 2032 2033 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 2034 gen_data_store(ctx, Rd, addr); 2035 gen_set_yaddr(addr); 2036 2037 tcg_temp_free_i32(addr); 2038 2039 return true; 2040 } 2041 2042 static bool trans_STDY(DisasContext *ctx, arg_STDY *a) 2043 { 2044 TCGv Rd = cpu_r[a->rd]; 2045 TCGv addr = gen_get_yaddr(); 2046 2047 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 2048 gen_data_store(ctx, Rd, addr); 2049 2050 tcg_temp_free_i32(addr); 2051 2052 return true; 2053 } 2054 2055 /* 2056 * Stores one byte indirect with or without displacement from a register to data 2057 * space. For parts with SRAM, the data space consists of the Register File, I/O 2058 * memory, and internal SRAM (and external SRAM if applicable). For parts 2059 * without SRAM, the data space consists of the Register File only. The EEPROM 2060 * has a separate address space. 2061 * 2062 * The data location is pointed to by the Y (16 bits) Pointer Register in the 2063 * Register File. Memory access is limited to the current data segment of 64KB. 2064 * To access another data segment in devices with more than 64KB data space, the 2065 * RAMPY in register in the I/O area has to be changed. 2066 * 2067 * The Y-pointer Register can either be left unchanged by the operation, or it 2068 * can be post-incremented or pre-decremented. These features are especially 2069 * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer 2070 * Register. Note that only the low byte of the Y-pointer is updated in devices 2071 * with no more than 256 bytes data space. For such devices, the high byte of 2072 * the pointer is not used by this instruction and can be used for other 2073 * purposes. The RAMPY Register in the I/O area is updated in parts with more 2074 * than 64KB data space or more than 64KB Program memory, and the increment / 2075 * decrement / displacement is added to the entire 24-bit address on such 2076 * devices. 2077 */ 2078 static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a) 2079 { 2080 TCGv Rd = cpu_r[a->rd]; 2081 TCGv addr = gen_get_zaddr(); 2082 2083 gen_data_store(ctx, Rd, addr); 2084 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2085 2086 gen_set_zaddr(addr); 2087 2088 tcg_temp_free_i32(addr); 2089 2090 return true; 2091 } 2092 2093 static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a) 2094 { 2095 TCGv Rd = cpu_r[a->rd]; 2096 TCGv addr = gen_get_zaddr(); 2097 2098 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 2099 gen_data_store(ctx, Rd, addr); 2100 2101 gen_set_zaddr(addr); 2102 2103 tcg_temp_free_i32(addr); 2104 2105 return true; 2106 } 2107 2108 static bool trans_STDZ(DisasContext *ctx, arg_STDZ *a) 2109 { 2110 TCGv Rd = cpu_r[a->rd]; 2111 TCGv addr = gen_get_zaddr(); 2112 2113 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 2114 gen_data_store(ctx, Rd, addr); 2115 2116 tcg_temp_free_i32(addr); 2117 2118 return true; 2119 } 2120 2121 /* 2122 * Loads one byte pointed to by the Z-register into the destination 2123 * register Rd. This instruction features a 100% space effective constant 2124 * initialization or constant data fetch. The Program memory is organized in 2125 * 16-bit words while the Z-pointer is a byte address. Thus, the least 2126 * significant bit of the Z-pointer selects either low byte (ZLSB = 0) or high 2127 * byte (ZLSB = 1). This instruction can address the first 64KB (32K words) of 2128 * Program memory. The Zpointer Register can either be left unchanged by the 2129 * operation, or it can be incremented. The incrementation does not apply to 2130 * the RAMPZ Register. 2131 * 2132 * Devices with Self-Programming capability can use the LPM instruction to read 2133 * the Fuse and Lock bit values. 2134 */ 2135 static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a) 2136 { 2137 if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) { 2138 return true; 2139 } 2140 2141 TCGv Rd = cpu_r[0]; 2142 TCGv addr = tcg_temp_new_i32(); 2143 TCGv H = cpu_r[31]; 2144 TCGv L = cpu_r[30]; 2145 2146 tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 2147 tcg_gen_or_tl(addr, addr, L); 2148 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2149 2150 tcg_temp_free_i32(addr); 2151 2152 return true; 2153 } 2154 2155 static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a) 2156 { 2157 if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) { 2158 return true; 2159 } 2160 2161 TCGv Rd = cpu_r[a->rd]; 2162 TCGv addr = tcg_temp_new_i32(); 2163 TCGv H = cpu_r[31]; 2164 TCGv L = cpu_r[30]; 2165 2166 tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 2167 tcg_gen_or_tl(addr, addr, L); 2168 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2169 2170 tcg_temp_free_i32(addr); 2171 2172 return true; 2173 } 2174 2175 static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a) 2176 { 2177 if (!avr_have_feature(ctx, AVR_FEATURE_LPMX)) { 2178 return true; 2179 } 2180 2181 TCGv Rd = cpu_r[a->rd]; 2182 TCGv addr = tcg_temp_new_i32(); 2183 TCGv H = cpu_r[31]; 2184 TCGv L = cpu_r[30]; 2185 2186 tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 2187 tcg_gen_or_tl(addr, addr, L); 2188 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2189 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2190 tcg_gen_andi_tl(L, addr, 0xff); 2191 tcg_gen_shri_tl(addr, addr, 8); 2192 tcg_gen_andi_tl(H, addr, 0xff); 2193 2194 tcg_temp_free_i32(addr); 2195 2196 return true; 2197 } 2198 2199 /* 2200 * Loads one byte pointed to by the Z-register and the RAMPZ Register in 2201 * the I/O space, and places this byte in the destination register Rd. This 2202 * instruction features a 100% space effective constant initialization or 2203 * constant data fetch. The Program memory is organized in 16-bit words while 2204 * the Z-pointer is a byte address. Thus, the least significant bit of the 2205 * Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This 2206 * instruction can address the entire Program memory space. The Z-pointer 2207 * Register can either be left unchanged by the operation, or it can be 2208 * incremented. The incrementation applies to the entire 24-bit concatenation 2209 * of the RAMPZ and Z-pointer Registers. 2210 * 2211 * Devices with Self-Programming capability can use the ELPM instruction to 2212 * read the Fuse and Lock bit value. 2213 */ 2214 static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a) 2215 { 2216 if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) { 2217 return true; 2218 } 2219 2220 TCGv Rd = cpu_r[0]; 2221 TCGv addr = gen_get_zaddr(); 2222 2223 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2224 2225 tcg_temp_free_i32(addr); 2226 2227 return true; 2228 } 2229 2230 static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a) 2231 { 2232 if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) { 2233 return true; 2234 } 2235 2236 TCGv Rd = cpu_r[a->rd]; 2237 TCGv addr = gen_get_zaddr(); 2238 2239 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2240 2241 tcg_temp_free_i32(addr); 2242 2243 return true; 2244 } 2245 2246 static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a) 2247 { 2248 if (!avr_have_feature(ctx, AVR_FEATURE_ELPMX)) { 2249 return true; 2250 } 2251 2252 TCGv Rd = cpu_r[a->rd]; 2253 TCGv addr = gen_get_zaddr(); 2254 2255 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2256 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2257 gen_set_zaddr(addr); 2258 2259 tcg_temp_free_i32(addr); 2260 2261 return true; 2262 } 2263 2264 /* 2265 * SPM can be used to erase a page in the Program memory, to write a page 2266 * in the Program memory (that is already erased), and to set Boot Loader Lock 2267 * bits. In some devices, the Program memory can be written one word at a time, 2268 * in other devices an entire page can be programmed simultaneously after first 2269 * filling a temporary page buffer. In all cases, the Program memory must be 2270 * erased one page at a time. When erasing the Program memory, the RAMPZ and 2271 * Z-register are used as page address. When writing the Program memory, the 2272 * RAMPZ and Z-register are used as page or word address, and the R1:R0 2273 * register pair is used as data(1). When setting the Boot Loader Lock bits, 2274 * the R1:R0 register pair is used as data. Refer to the device documentation 2275 * for detailed description of SPM usage. This instruction can address the 2276 * entire Program memory. 2277 * 2278 * The SPM instruction is not available in all devices. Refer to the device 2279 * specific instruction set summary. 2280 * 2281 * Note: 1. R1 determines the instruction high byte, and R0 determines the 2282 * instruction low byte. 2283 */ 2284 static bool trans_SPM(DisasContext *ctx, arg_SPM *a) 2285 { 2286 /* TODO */ 2287 if (!avr_have_feature(ctx, AVR_FEATURE_SPM)) { 2288 return true; 2289 } 2290 2291 return true; 2292 } 2293 2294 static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) 2295 { 2296 /* TODO */ 2297 if (!avr_have_feature(ctx, AVR_FEATURE_SPMX)) { 2298 return true; 2299 } 2300 2301 return true; 2302 } 2303 2304 /* 2305 * Loads data from the I/O Space (Ports, Timers, Configuration Registers, 2306 * etc.) into register Rd in the Register File. 2307 */ 2308 static bool trans_IN(DisasContext *ctx, arg_IN *a) 2309 { 2310 TCGv Rd = cpu_r[a->rd]; 2311 TCGv port = tcg_const_i32(a->imm); 2312 2313 gen_helper_inb(Rd, cpu_env, port); 2314 2315 tcg_temp_free_i32(port); 2316 2317 return true; 2318 } 2319 2320 /* 2321 * Stores data from register Rr in the Register File to I/O Space (Ports, 2322 * Timers, Configuration Registers, etc.). 2323 */ 2324 static bool trans_OUT(DisasContext *ctx, arg_OUT *a) 2325 { 2326 TCGv Rd = cpu_r[a->rd]; 2327 TCGv port = tcg_const_i32(a->imm); 2328 2329 gen_helper_outb(cpu_env, port, Rd); 2330 2331 tcg_temp_free_i32(port); 2332 2333 return true; 2334 } 2335 2336 /* 2337 * This instruction stores the contents of register Rr on the STACK. The 2338 * Stack Pointer is post-decremented by 1 after the PUSH. This instruction is 2339 * not available in all devices. Refer to the device specific instruction set 2340 * summary. 2341 */ 2342 static bool trans_PUSH(DisasContext *ctx, arg_PUSH *a) 2343 { 2344 TCGv Rd = cpu_r[a->rd]; 2345 2346 gen_data_store(ctx, Rd, cpu_sp); 2347 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 2348 2349 return true; 2350 } 2351 2352 /* 2353 * This instruction loads register Rd with a byte from the STACK. The Stack 2354 * Pointer is pre-incremented by 1 before the POP. This instruction is not 2355 * available in all devices. Refer to the device specific instruction set 2356 * summary. 2357 */ 2358 static bool trans_POP(DisasContext *ctx, arg_POP *a) 2359 { 2360 /* 2361 * Using a temp to work around some strange behaviour: 2362 * tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 2363 * gen_data_load(ctx, Rd, cpu_sp); 2364 * seems to cause the add to happen twice. 2365 * This doesn't happen if either the add or the load is removed. 2366 */ 2367 TCGv t1 = tcg_temp_new_i32(); 2368 TCGv Rd = cpu_r[a->rd]; 2369 2370 tcg_gen_addi_tl(t1, cpu_sp, 1); 2371 gen_data_load(ctx, Rd, t1); 2372 tcg_gen_mov_tl(cpu_sp, t1); 2373 2374 return true; 2375 } 2376 2377 /* 2378 * Exchanges one byte indirect between register and data space. The data 2379 * location is pointed to by the Z (16 bits) Pointer Register in the Register 2380 * File. Memory access is limited to the current data segment of 64KB. To 2381 * access another data segment in devices with more than 64KB data space, the 2382 * RAMPZ in register in the I/O area has to be changed. 2383 * 2384 * The Z-pointer Register is left unchanged by the operation. This instruction 2385 * is especially suited for writing/reading status bits stored in SRAM. 2386 */ 2387 static bool trans_XCH(DisasContext *ctx, arg_XCH *a) 2388 { 2389 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2390 return true; 2391 } 2392 2393 TCGv Rd = cpu_r[a->rd]; 2394 TCGv t0 = tcg_temp_new_i32(); 2395 TCGv addr = gen_get_zaddr(); 2396 2397 gen_data_load(ctx, t0, addr); 2398 gen_data_store(ctx, Rd, addr); 2399 tcg_gen_mov_tl(Rd, t0); 2400 2401 tcg_temp_free_i32(t0); 2402 tcg_temp_free_i32(addr); 2403 2404 return true; 2405 } 2406 2407 /* 2408 * Load one byte indirect from data space to register and set bits in data 2409 * space specified by the register. The instruction can only be used towards 2410 * internal SRAM. The data location is pointed to by the Z (16 bits) Pointer 2411 * Register in the Register File. Memory access is limited to the current data 2412 * segment of 64KB. To access another data segment in devices with more than 2413 * 64KB data space, the RAMPZ in register in the I/O area has to be changed. 2414 * 2415 * The Z-pointer Register is left unchanged by the operation. This instruction 2416 * is especially suited for setting status bits stored in SRAM. 2417 */ 2418 static bool trans_LAS(DisasContext *ctx, arg_LAS *a) 2419 { 2420 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2421 return true; 2422 } 2423 2424 TCGv Rr = cpu_r[a->rd]; 2425 TCGv addr = gen_get_zaddr(); 2426 TCGv t0 = tcg_temp_new_i32(); 2427 TCGv t1 = tcg_temp_new_i32(); 2428 2429 gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 2430 tcg_gen_or_tl(t1, t0, Rr); 2431 tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */ 2432 gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 2433 2434 tcg_temp_free_i32(t1); 2435 tcg_temp_free_i32(t0); 2436 tcg_temp_free_i32(addr); 2437 2438 return true; 2439 } 2440 2441 /* 2442 * Load one byte indirect from data space to register and stores and clear 2443 * the bits in data space specified by the register. The instruction can 2444 * only be used towards internal SRAM. The data location is pointed to by 2445 * the Z (16 bits) Pointer Register in the Register File. Memory access is 2446 * limited to the current data segment of 64KB. To access another data 2447 * segment in devices with more than 64KB data space, the RAMPZ in register 2448 * in the I/O area has to be changed. 2449 * 2450 * The Z-pointer Register is left unchanged by the operation. This instruction 2451 * is especially suited for clearing status bits stored in SRAM. 2452 */ 2453 static bool trans_LAC(DisasContext *ctx, arg_LAC *a) 2454 { 2455 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2456 return true; 2457 } 2458 2459 TCGv Rr = cpu_r[a->rd]; 2460 TCGv addr = gen_get_zaddr(); 2461 TCGv t0 = tcg_temp_new_i32(); 2462 TCGv t1 = tcg_temp_new_i32(); 2463 2464 gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 2465 tcg_gen_andc_tl(t1, t0, Rr); /* t1 = t0 & (0xff - Rr) = t0 & ~Rr */ 2466 tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */ 2467 gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 2468 2469 tcg_temp_free_i32(t1); 2470 tcg_temp_free_i32(t0); 2471 tcg_temp_free_i32(addr); 2472 2473 return true; 2474 } 2475 2476 2477 /* 2478 * Load one byte indirect from data space to register and toggles bits in 2479 * the data space specified by the register. The instruction can only be used 2480 * towards SRAM. The data location is pointed to by the Z (16 bits) Pointer 2481 * Register in the Register File. Memory access is limited to the current data 2482 * segment of 64KB. To access another data segment in devices with more than 2483 * 64KB data space, the RAMPZ in register in the I/O area has to be changed. 2484 * 2485 * The Z-pointer Register is left unchanged by the operation. This instruction 2486 * is especially suited for changing status bits stored in SRAM. 2487 */ 2488 static bool trans_LAT(DisasContext *ctx, arg_LAT *a) 2489 { 2490 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2491 return true; 2492 } 2493 2494 TCGv Rd = cpu_r[a->rd]; 2495 TCGv addr = gen_get_zaddr(); 2496 TCGv t0 = tcg_temp_new_i32(); 2497 TCGv t1 = tcg_temp_new_i32(); 2498 2499 gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 2500 tcg_gen_xor_tl(t1, t0, Rd); 2501 tcg_gen_mov_tl(Rd, t0); /* Rd = t0 */ 2502 gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 2503 2504 tcg_temp_free_i32(t1); 2505 tcg_temp_free_i32(t0); 2506 tcg_temp_free_i32(addr); 2507 2508 return true; 2509 } 2510 2511 /* 2512 * Bit and Bit-test Instructions 2513 */ 2514 static void gen_rshift_ZNVSf(TCGv R) 2515 { 2516 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 2517 tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 2518 tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf); 2519 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 2520 } 2521 2522 /* 2523 * Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is 2524 * loaded into the C Flag of the SREG. This operation effectively divides an 2525 * unsigned value by two. The C Flag can be used to round the result. 2526 */ 2527 static bool trans_LSR(DisasContext *ctx, arg_LSR *a) 2528 { 2529 TCGv Rd = cpu_r[a->rd]; 2530 2531 tcg_gen_andi_tl(cpu_Cf, Rd, 1); 2532 tcg_gen_shri_tl(Rd, Rd, 1); 2533 2534 /* update status register */ 2535 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, Rd, 0); /* Zf = Rd == 0 */ 2536 tcg_gen_movi_tl(cpu_Nf, 0); 2537 tcg_gen_mov_tl(cpu_Vf, cpu_Cf); 2538 tcg_gen_mov_tl(cpu_Sf, cpu_Vf); 2539 2540 return true; 2541 } 2542 2543 /* 2544 * Shifts all bits in Rd one place to the right. The C Flag is shifted into 2545 * bit 7 of Rd. Bit 0 is shifted into the C Flag. This operation, combined 2546 * with ASR, effectively divides multi-byte signed values by two. Combined with 2547 * LSR it effectively divides multi-byte unsigned values by two. The Carry Flag 2548 * can be used to round the result. 2549 */ 2550 static bool trans_ROR(DisasContext *ctx, arg_ROR *a) 2551 { 2552 TCGv Rd = cpu_r[a->rd]; 2553 TCGv t0 = tcg_temp_new_i32(); 2554 2555 tcg_gen_shli_tl(t0, cpu_Cf, 7); 2556 2557 /* update status register */ 2558 tcg_gen_andi_tl(cpu_Cf, Rd, 1); 2559 2560 /* update output register */ 2561 tcg_gen_shri_tl(Rd, Rd, 1); 2562 tcg_gen_or_tl(Rd, Rd, t0); 2563 2564 /* update status register */ 2565 gen_rshift_ZNVSf(Rd); 2566 2567 tcg_temp_free_i32(t0); 2568 2569 return true; 2570 } 2571 2572 /* 2573 * Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 2574 * is loaded into the C Flag of the SREG. This operation effectively divides a 2575 * signed value by two without changing its sign. The Carry Flag can be used to 2576 * round the result. 2577 */ 2578 static bool trans_ASR(DisasContext *ctx, arg_ASR *a) 2579 { 2580 TCGv Rd = cpu_r[a->rd]; 2581 TCGv t0 = tcg_temp_new_i32(); 2582 2583 /* update status register */ 2584 tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf = Rd(0) */ 2585 2586 /* update output register */ 2587 tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd = (Rd & 0x80) | (Rd >> 1) */ 2588 tcg_gen_shri_tl(Rd, Rd, 1); 2589 tcg_gen_or_tl(Rd, Rd, t0); 2590 2591 /* update status register */ 2592 gen_rshift_ZNVSf(Rd); 2593 2594 tcg_temp_free_i32(t0); 2595 2596 return true; 2597 } 2598 2599 /* 2600 * Swaps high and low nibbles in a register. 2601 */ 2602 static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a) 2603 { 2604 TCGv Rd = cpu_r[a->rd]; 2605 TCGv t0 = tcg_temp_new_i32(); 2606 TCGv t1 = tcg_temp_new_i32(); 2607 2608 tcg_gen_andi_tl(t0, Rd, 0x0f); 2609 tcg_gen_shli_tl(t0, t0, 4); 2610 tcg_gen_andi_tl(t1, Rd, 0xf0); 2611 tcg_gen_shri_tl(t1, t1, 4); 2612 tcg_gen_or_tl(Rd, t0, t1); 2613 2614 tcg_temp_free_i32(t1); 2615 tcg_temp_free_i32(t0); 2616 2617 return true; 2618 } 2619 2620 /* 2621 * Sets a specified bit in an I/O Register. This instruction operates on 2622 * the lower 32 I/O Registers -- addresses 0-31. 2623 */ 2624 static bool trans_SBI(DisasContext *ctx, arg_SBI *a) 2625 { 2626 TCGv data = tcg_temp_new_i32(); 2627 TCGv port = tcg_const_i32(a->reg); 2628 2629 gen_helper_inb(data, cpu_env, port); 2630 tcg_gen_ori_tl(data, data, 1 << a->bit); 2631 gen_helper_outb(cpu_env, port, data); 2632 2633 tcg_temp_free_i32(port); 2634 tcg_temp_free_i32(data); 2635 2636 return true; 2637 } 2638 2639 /* 2640 * Clears a specified bit in an I/O Register. This instruction operates on 2641 * the lower 32 I/O Registers -- addresses 0-31. 2642 */ 2643 static bool trans_CBI(DisasContext *ctx, arg_CBI *a) 2644 { 2645 TCGv data = tcg_temp_new_i32(); 2646 TCGv port = tcg_const_i32(a->reg); 2647 2648 gen_helper_inb(data, cpu_env, port); 2649 tcg_gen_andi_tl(data, data, ~(1 << a->bit)); 2650 gen_helper_outb(cpu_env, port, data); 2651 2652 tcg_temp_free_i32(data); 2653 tcg_temp_free_i32(port); 2654 2655 return true; 2656 } 2657 2658 /* 2659 * Stores bit b from Rd to the T Flag in SREG (Status Register). 2660 */ 2661 static bool trans_BST(DisasContext *ctx, arg_BST *a) 2662 { 2663 TCGv Rd = cpu_r[a->rd]; 2664 2665 tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit); 2666 tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit); 2667 2668 return true; 2669 } 2670 2671 /* 2672 * Copies the T Flag in the SREG (Status Register) to bit b in register Rd. 2673 */ 2674 static bool trans_BLD(DisasContext *ctx, arg_BLD *a) 2675 { 2676 TCGv Rd = cpu_r[a->rd]; 2677 TCGv t1 = tcg_temp_new_i32(); 2678 2679 tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear bit */ 2680 tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */ 2681 tcg_gen_or_tl(Rd, Rd, t1); 2682 2683 tcg_temp_free_i32(t1); 2684 2685 return true; 2686 } 2687 2688 /* 2689 * Sets a single Flag or bit in SREG. 2690 */ 2691 static bool trans_BSET(DisasContext *ctx, arg_BSET *a) 2692 { 2693 switch (a->bit) { 2694 case 0x00: 2695 tcg_gen_movi_tl(cpu_Cf, 0x01); 2696 break; 2697 case 0x01: 2698 tcg_gen_movi_tl(cpu_Zf, 0x01); 2699 break; 2700 case 0x02: 2701 tcg_gen_movi_tl(cpu_Nf, 0x01); 2702 break; 2703 case 0x03: 2704 tcg_gen_movi_tl(cpu_Vf, 0x01); 2705 break; 2706 case 0x04: 2707 tcg_gen_movi_tl(cpu_Sf, 0x01); 2708 break; 2709 case 0x05: 2710 tcg_gen_movi_tl(cpu_Hf, 0x01); 2711 break; 2712 case 0x06: 2713 tcg_gen_movi_tl(cpu_Tf, 0x01); 2714 break; 2715 case 0x07: 2716 tcg_gen_movi_tl(cpu_If, 0x01); 2717 break; 2718 } 2719 2720 return true; 2721 } 2722 2723 /* 2724 * Clears a single Flag in SREG. 2725 */ 2726 static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a) 2727 { 2728 switch (a->bit) { 2729 case 0x00: 2730 tcg_gen_movi_tl(cpu_Cf, 0x00); 2731 break; 2732 case 0x01: 2733 tcg_gen_movi_tl(cpu_Zf, 0x00); 2734 break; 2735 case 0x02: 2736 tcg_gen_movi_tl(cpu_Nf, 0x00); 2737 break; 2738 case 0x03: 2739 tcg_gen_movi_tl(cpu_Vf, 0x00); 2740 break; 2741 case 0x04: 2742 tcg_gen_movi_tl(cpu_Sf, 0x00); 2743 break; 2744 case 0x05: 2745 tcg_gen_movi_tl(cpu_Hf, 0x00); 2746 break; 2747 case 0x06: 2748 tcg_gen_movi_tl(cpu_Tf, 0x00); 2749 break; 2750 case 0x07: 2751 tcg_gen_movi_tl(cpu_If, 0x00); 2752 break; 2753 } 2754 2755 return true; 2756 } 2757 2758 /* 2759 * MCU Control Instructions 2760 */ 2761 2762 /* 2763 * The BREAK instruction is used by the On-chip Debug system, and is 2764 * normally not used in the application software. When the BREAK instruction is 2765 * executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip 2766 * Debugger access to internal resources. If any Lock bits are set, or either 2767 * the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK 2768 * instruction as a NOP and will not enter the Stopped mode. This instruction 2769 * is not available in all devices. Refer to the device specific instruction 2770 * set summary. 2771 */ 2772 static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a) 2773 { 2774 if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) { 2775 return true; 2776 } 2777 2778 #ifdef BREAKPOINT_ON_BREAK 2779 tcg_gen_movi_tl(cpu_pc, ctx->npc - 1); 2780 gen_helper_debug(cpu_env); 2781 ctx->base.is_jmp = DISAS_EXIT; 2782 #else 2783 /* NOP */ 2784 #endif 2785 2786 return true; 2787 } 2788 2789 /* 2790 * This instruction performs a single cycle No Operation. 2791 */ 2792 static bool trans_NOP(DisasContext *ctx, arg_NOP *a) 2793 { 2794 2795 /* NOP */ 2796 2797 return true; 2798 } 2799 2800 /* 2801 * This instruction sets the circuit in sleep mode defined by the MCU 2802 * Control Register. 2803 */ 2804 static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a) 2805 { 2806 gen_helper_sleep(cpu_env); 2807 ctx->base.is_jmp = DISAS_NORETURN; 2808 return true; 2809 } 2810 2811 /* 2812 * This instruction resets the Watchdog Timer. This instruction must be 2813 * executed within a limited time given by the WD prescaler. See the Watchdog 2814 * Timer hardware specification. 2815 */ 2816 static bool trans_WDR(DisasContext *ctx, arg_WDR *a) 2817 { 2818 gen_helper_wdr(cpu_env); 2819 2820 return true; 2821 } 2822 2823 /* 2824 * Core translation mechanism functions: 2825 * 2826 * - translate() 2827 * - canonicalize_skip() 2828 * - gen_intermediate_code() 2829 * - restore_state_to_opc() 2830 * 2831 */ 2832 static void translate(DisasContext *ctx) 2833 { 2834 uint32_t opcode = next_word(ctx); 2835 2836 if (!decode_insn(ctx, opcode)) { 2837 gen_helper_unsupported(cpu_env); 2838 ctx->base.is_jmp = DISAS_NORETURN; 2839 } 2840 } 2841 2842 /* Standardize the cpu_skip condition to NE. */ 2843 static bool canonicalize_skip(DisasContext *ctx) 2844 { 2845 switch (ctx->skip_cond) { 2846 case TCG_COND_NEVER: 2847 /* Normal case: cpu_skip is known to be false. */ 2848 return false; 2849 2850 case TCG_COND_ALWAYS: 2851 /* 2852 * Breakpoint case: cpu_skip is known to be true, via TB_FLAGS_SKIP. 2853 * The breakpoint is on the instruction being skipped, at the start 2854 * of the TranslationBlock. No need to update. 2855 */ 2856 return false; 2857 2858 case TCG_COND_NE: 2859 if (ctx->skip_var1 == NULL) { 2860 tcg_gen_mov_tl(cpu_skip, ctx->skip_var0); 2861 } else { 2862 tcg_gen_xor_tl(cpu_skip, ctx->skip_var0, ctx->skip_var1); 2863 ctx->skip_var1 = NULL; 2864 } 2865 break; 2866 2867 default: 2868 /* Convert to a NE condition vs 0. */ 2869 if (ctx->skip_var1 == NULL) { 2870 tcg_gen_setcondi_tl(ctx->skip_cond, cpu_skip, ctx->skip_var0, 0); 2871 } else { 2872 tcg_gen_setcond_tl(ctx->skip_cond, cpu_skip, 2873 ctx->skip_var0, ctx->skip_var1); 2874 ctx->skip_var1 = NULL; 2875 } 2876 ctx->skip_cond = TCG_COND_NE; 2877 break; 2878 } 2879 ctx->skip_var0 = cpu_skip; 2880 return true; 2881 } 2882 2883 static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 2884 { 2885 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2886 CPUAVRState *env = cs->env_ptr; 2887 uint32_t tb_flags = ctx->base.tb->flags; 2888 2889 ctx->cs = cs; 2890 ctx->env = env; 2891 ctx->npc = ctx->base.pc_first / 2; 2892 2893 ctx->skip_cond = TCG_COND_NEVER; 2894 if (tb_flags & TB_FLAGS_SKIP) { 2895 ctx->skip_cond = TCG_COND_ALWAYS; 2896 ctx->skip_var0 = cpu_skip; 2897 } 2898 2899 if (tb_flags & TB_FLAGS_FULL_ACCESS) { 2900 /* 2901 * This flag is set by ST/LD instruction we will regenerate it ONLY 2902 * with mem/cpu memory access instead of mem access 2903 */ 2904 ctx->base.max_insns = 1; 2905 } 2906 } 2907 2908 static void avr_tr_tb_start(DisasContextBase *db, CPUState *cs) 2909 { 2910 } 2911 2912 static void avr_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 2913 { 2914 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2915 2916 tcg_gen_insn_start(ctx->npc); 2917 } 2918 2919 static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 2920 { 2921 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2922 TCGLabel *skip_label = NULL; 2923 2924 /* Conditionally skip the next instruction, if indicated. */ 2925 if (ctx->skip_cond != TCG_COND_NEVER) { 2926 skip_label = gen_new_label(); 2927 if (ctx->skip_var0 == cpu_skip) { 2928 /* 2929 * Copy cpu_skip so that we may zero it before the branch. 2930 * This ensures that cpu_skip is non-zero after the label 2931 * if and only if the skipped insn itself sets a skip. 2932 */ 2933 ctx->skip_var0 = tcg_temp_new(); 2934 tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); 2935 tcg_gen_movi_tl(cpu_skip, 0); 2936 } 2937 if (ctx->skip_var1 == NULL) { 2938 tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0, 0, skip_label); 2939 } else { 2940 tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0, 2941 ctx->skip_var1, skip_label); 2942 ctx->skip_var1 = NULL; 2943 } 2944 ctx->skip_cond = TCG_COND_NEVER; 2945 ctx->skip_var0 = NULL; 2946 } 2947 2948 translate(ctx); 2949 2950 ctx->base.pc_next = ctx->npc * 2; 2951 2952 if (skip_label) { 2953 canonicalize_skip(ctx); 2954 gen_set_label(skip_label); 2955 2956 switch (ctx->base.is_jmp) { 2957 case DISAS_NORETURN: 2958 ctx->base.is_jmp = DISAS_CHAIN; 2959 break; 2960 case DISAS_NEXT: 2961 if (ctx->base.tb->flags & TB_FLAGS_SKIP) { 2962 ctx->base.is_jmp = DISAS_TOO_MANY; 2963 } 2964 break; 2965 default: 2966 break; 2967 } 2968 } 2969 2970 if (ctx->base.is_jmp == DISAS_NEXT) { 2971 target_ulong page_first = ctx->base.pc_first & TARGET_PAGE_MASK; 2972 2973 if ((ctx->base.pc_next - page_first) >= TARGET_PAGE_SIZE - 4) { 2974 ctx->base.is_jmp = DISAS_TOO_MANY; 2975 } 2976 } 2977 } 2978 2979 static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 2980 { 2981 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2982 bool nonconst_skip = canonicalize_skip(ctx); 2983 /* 2984 * Because we disable interrupts while env->skip is set, 2985 * we must return to the main loop to re-evaluate afterward. 2986 */ 2987 bool force_exit = ctx->base.tb->flags & TB_FLAGS_SKIP; 2988 2989 switch (ctx->base.is_jmp) { 2990 case DISAS_NORETURN: 2991 assert(!nonconst_skip); 2992 break; 2993 case DISAS_NEXT: 2994 case DISAS_TOO_MANY: 2995 case DISAS_CHAIN: 2996 if (!nonconst_skip && !force_exit) { 2997 /* Note gen_goto_tb checks singlestep. */ 2998 gen_goto_tb(ctx, 1, ctx->npc); 2999 break; 3000 } 3001 tcg_gen_movi_tl(cpu_pc, ctx->npc); 3002 /* fall through */ 3003 case DISAS_LOOKUP: 3004 if (!force_exit) { 3005 tcg_gen_lookup_and_goto_ptr(); 3006 break; 3007 } 3008 /* fall through */ 3009 case DISAS_EXIT: 3010 tcg_gen_exit_tb(NULL, 0); 3011 break; 3012 default: 3013 g_assert_not_reached(); 3014 } 3015 } 3016 3017 static void avr_tr_disas_log(const DisasContextBase *dcbase, 3018 CPUState *cs, FILE *logfile) 3019 { 3020 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 3021 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 3022 } 3023 3024 static const TranslatorOps avr_tr_ops = { 3025 .init_disas_context = avr_tr_init_disas_context, 3026 .tb_start = avr_tr_tb_start, 3027 .insn_start = avr_tr_insn_start, 3028 .translate_insn = avr_tr_translate_insn, 3029 .tb_stop = avr_tr_tb_stop, 3030 .disas_log = avr_tr_disas_log, 3031 }; 3032 3033 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 3034 target_ulong pc, void *host_pc) 3035 { 3036 DisasContext dc = { }; 3037 translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base); 3038 } 3039