1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2019-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "tcg/tcg.h" 24 #include "cpu.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "exec/cpu_ldst.h" 28 #include "exec/helper-proto.h" 29 #include "exec/helper-gen.h" 30 #include "exec/log.h" 31 #include "exec/translator.h" 32 #include "exec/gen-icount.h" 33 34 /* 35 * Define if you want a BREAK instruction translated to a breakpoint 36 * Active debugging connection is assumed 37 * This is for 38 * https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests 39 * tests 40 */ 41 #undef BREAKPOINT_ON_BREAK 42 43 static TCGv cpu_pc; 44 45 static TCGv cpu_Cf; 46 static TCGv cpu_Zf; 47 static TCGv cpu_Nf; 48 static TCGv cpu_Vf; 49 static TCGv cpu_Sf; 50 static TCGv cpu_Hf; 51 static TCGv cpu_Tf; 52 static TCGv cpu_If; 53 54 static TCGv cpu_rampD; 55 static TCGv cpu_rampX; 56 static TCGv cpu_rampY; 57 static TCGv cpu_rampZ; 58 59 static TCGv cpu_r[NUMBER_OF_CPU_REGISTERS]; 60 static TCGv cpu_eind; 61 static TCGv cpu_sp; 62 63 static TCGv cpu_skip; 64 65 static const char reg_names[NUMBER_OF_CPU_REGISTERS][8] = { 66 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 67 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 68 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 69 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 70 }; 71 #define REG(x) (cpu_r[x]) 72 73 #define DISAS_EXIT DISAS_TARGET_0 /* We want return to the cpu main loop. */ 74 #define DISAS_LOOKUP DISAS_TARGET_1 /* We have a variable condition exit. */ 75 #define DISAS_CHAIN DISAS_TARGET_2 /* We have a single condition exit. */ 76 77 typedef struct DisasContext DisasContext; 78 79 /* This is the state at translation time. */ 80 struct DisasContext { 81 DisasContextBase base; 82 83 CPUAVRState *env; 84 CPUState *cs; 85 86 target_long npc; 87 uint32_t opcode; 88 89 /* Routine used to access memory */ 90 int memidx; 91 92 /* 93 * some AVR instructions can make the following instruction to be skipped 94 * Let's name those instructions 95 * A - instruction that can skip the next one 96 * B - instruction that can be skipped. this depends on execution of A 97 * there are two scenarios 98 * 1. A and B belong to the same translation block 99 * 2. A is the last instruction in the translation block and B is the last 100 * 101 * following variables are used to simplify the skipping logic, they are 102 * used in the following manner (sketch) 103 * 104 * TCGLabel *skip_label = NULL; 105 * if (ctx->skip_cond != TCG_COND_NEVER) { 106 * skip_label = gen_new_label(); 107 * tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label); 108 * } 109 * 110 * translate(ctx); 111 * 112 * if (skip_label) { 113 * gen_set_label(skip_label); 114 * } 115 */ 116 TCGv skip_var0; 117 TCGv skip_var1; 118 TCGCond skip_cond; 119 }; 120 121 void avr_cpu_tcg_init(void) 122 { 123 int i; 124 125 #define AVR_REG_OFFS(x) offsetof(CPUAVRState, x) 126 cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc"); 127 cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf"); 128 cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf"); 129 cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf"); 130 cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf"); 131 cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf"); 132 cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf"); 133 cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf"); 134 cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If"); 135 cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD"); 136 cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX"); 137 cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY"); 138 cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ"); 139 cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind"); 140 cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp"); 141 cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip"); 142 143 for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) { 144 cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]), 145 reg_names[i]); 146 } 147 #undef AVR_REG_OFFS 148 } 149 150 static int to_regs_16_31_by_one(DisasContext *ctx, int indx) 151 { 152 return 16 + (indx % 16); 153 } 154 155 static int to_regs_16_23_by_one(DisasContext *ctx, int indx) 156 { 157 return 16 + (indx % 8); 158 } 159 160 static int to_regs_24_30_by_two(DisasContext *ctx, int indx) 161 { 162 return 24 + (indx % 4) * 2; 163 } 164 165 static int to_regs_00_30_by_two(DisasContext *ctx, int indx) 166 { 167 return (indx % 16) * 2; 168 } 169 170 static uint16_t next_word(DisasContext *ctx) 171 { 172 return cpu_lduw_code(ctx->env, ctx->npc++ * 2); 173 } 174 175 static int append_16(DisasContext *ctx, int x) 176 { 177 return x << 16 | next_word(ctx); 178 } 179 180 static bool avr_have_feature(DisasContext *ctx, int feature) 181 { 182 if (!avr_feature(ctx->env, feature)) { 183 gen_helper_unsupported(cpu_env); 184 ctx->base.is_jmp = DISAS_NORETURN; 185 return false; 186 } 187 return true; 188 } 189 190 static bool decode_insn(DisasContext *ctx, uint16_t insn); 191 #include "decode-insn.c.inc" 192 193 /* 194 * Arithmetic Instructions 195 */ 196 197 /* 198 * Utility functions for updating status registers: 199 * 200 * - gen_add_CHf() 201 * - gen_add_Vf() 202 * - gen_sub_CHf() 203 * - gen_sub_Vf() 204 * - gen_NSf() 205 * - gen_ZNSf() 206 * 207 */ 208 209 static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr) 210 { 211 TCGv t1 = tcg_temp_new_i32(); 212 TCGv t2 = tcg_temp_new_i32(); 213 TCGv t3 = tcg_temp_new_i32(); 214 215 tcg_gen_and_tl(t1, Rd, Rr); /* t1 = Rd & Rr */ 216 tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd & ~R */ 217 tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr & ~R */ 218 tcg_gen_or_tl(t1, t1, t2); /* t1 = t1 | t2 | t3 */ 219 tcg_gen_or_tl(t1, t1, t3); 220 221 tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */ 222 tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */ 223 tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1); 224 225 tcg_temp_free_i32(t3); 226 tcg_temp_free_i32(t2); 227 tcg_temp_free_i32(t1); 228 } 229 230 static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr) 231 { 232 TCGv t1 = tcg_temp_new_i32(); 233 TCGv t2 = tcg_temp_new_i32(); 234 235 /* t1 = Rd & Rr & ~R | ~Rd & ~Rr & R */ 236 /* = (Rd ^ R) & ~(Rd ^ Rr) */ 237 tcg_gen_xor_tl(t1, Rd, R); 238 tcg_gen_xor_tl(t2, Rd, Rr); 239 tcg_gen_andc_tl(t1, t1, t2); 240 241 tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */ 242 243 tcg_temp_free_i32(t2); 244 tcg_temp_free_i32(t1); 245 } 246 247 static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr) 248 { 249 TCGv t1 = tcg_temp_new_i32(); 250 TCGv t2 = tcg_temp_new_i32(); 251 TCGv t3 = tcg_temp_new_i32(); 252 253 tcg_gen_not_tl(t1, Rd); /* t1 = ~Rd */ 254 tcg_gen_and_tl(t2, t1, Rr); /* t2 = ~Rd & Rr */ 255 tcg_gen_or_tl(t3, t1, Rr); /* t3 = (~Rd | Rr) & R */ 256 tcg_gen_and_tl(t3, t3, R); 257 tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */ 258 259 tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */ 260 tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */ 261 tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1); 262 263 tcg_temp_free_i32(t3); 264 tcg_temp_free_i32(t2); 265 tcg_temp_free_i32(t1); 266 } 267 268 static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr) 269 { 270 TCGv t1 = tcg_temp_new_i32(); 271 TCGv t2 = tcg_temp_new_i32(); 272 273 /* t1 = Rd & ~Rr & ~R | ~Rd & Rr & R */ 274 /* = (Rd ^ R) & (Rd ^ R) */ 275 tcg_gen_xor_tl(t1, Rd, R); 276 tcg_gen_xor_tl(t2, Rd, Rr); 277 tcg_gen_and_tl(t1, t1, t2); 278 279 tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */ 280 281 tcg_temp_free_i32(t2); 282 tcg_temp_free_i32(t1); 283 } 284 285 static void gen_NSf(TCGv R) 286 { 287 tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 288 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 289 } 290 291 static void gen_ZNSf(TCGv R) 292 { 293 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 294 295 /* update status register */ 296 tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 297 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 298 } 299 300 /* 301 * Adds two registers without the C Flag and places the result in the 302 * destination register Rd. 303 */ 304 static bool trans_ADD(DisasContext *ctx, arg_ADD *a) 305 { 306 TCGv Rd = cpu_r[a->rd]; 307 TCGv Rr = cpu_r[a->rr]; 308 TCGv R = tcg_temp_new_i32(); 309 310 tcg_gen_add_tl(R, Rd, Rr); /* Rd = Rd + Rr */ 311 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 312 313 /* update status register */ 314 gen_add_CHf(R, Rd, Rr); 315 gen_add_Vf(R, Rd, Rr); 316 gen_ZNSf(R); 317 318 /* update output registers */ 319 tcg_gen_mov_tl(Rd, R); 320 321 tcg_temp_free_i32(R); 322 323 return true; 324 } 325 326 /* 327 * Adds two registers and the contents of the C Flag and places the result in 328 * the destination register Rd. 329 */ 330 static bool trans_ADC(DisasContext *ctx, arg_ADC *a) 331 { 332 TCGv Rd = cpu_r[a->rd]; 333 TCGv Rr = cpu_r[a->rr]; 334 TCGv R = tcg_temp_new_i32(); 335 336 tcg_gen_add_tl(R, Rd, Rr); /* R = Rd + Rr + Cf */ 337 tcg_gen_add_tl(R, R, cpu_Cf); 338 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 339 340 /* update status register */ 341 gen_add_CHf(R, Rd, Rr); 342 gen_add_Vf(R, Rd, Rr); 343 gen_ZNSf(R); 344 345 /* update output registers */ 346 tcg_gen_mov_tl(Rd, R); 347 348 tcg_temp_free_i32(R); 349 350 return true; 351 } 352 353 /* 354 * Adds an immediate value (0 - 63) to a register pair and places the result 355 * in the register pair. This instruction operates on the upper four register 356 * pairs, and is well suited for operations on the pointer registers. This 357 * instruction is not available in all devices. Refer to the device specific 358 * instruction set summary. 359 */ 360 static bool trans_ADIW(DisasContext *ctx, arg_ADIW *a) 361 { 362 if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) { 363 return true; 364 } 365 366 TCGv RdL = cpu_r[a->rd]; 367 TCGv RdH = cpu_r[a->rd + 1]; 368 int Imm = (a->imm); 369 TCGv R = tcg_temp_new_i32(); 370 TCGv Rd = tcg_temp_new_i32(); 371 372 tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */ 373 tcg_gen_addi_tl(R, Rd, Imm); /* R = Rd + Imm */ 374 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 375 376 /* update status register */ 377 tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */ 378 tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15); 379 tcg_gen_andc_tl(cpu_Vf, R, Rd); /* Vf = R & ~Rd */ 380 tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15); 381 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 382 tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */ 383 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf);/* Sf = Nf ^ Vf */ 384 385 /* update output registers */ 386 tcg_gen_andi_tl(RdL, R, 0xff); 387 tcg_gen_shri_tl(RdH, R, 8); 388 389 tcg_temp_free_i32(Rd); 390 tcg_temp_free_i32(R); 391 392 return true; 393 } 394 395 /* 396 * Subtracts two registers and places the result in the destination 397 * register Rd. 398 */ 399 static bool trans_SUB(DisasContext *ctx, arg_SUB *a) 400 { 401 TCGv Rd = cpu_r[a->rd]; 402 TCGv Rr = cpu_r[a->rr]; 403 TCGv R = tcg_temp_new_i32(); 404 405 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 406 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 407 408 /* update status register */ 409 tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */ 410 gen_sub_CHf(R, Rd, Rr); 411 gen_sub_Vf(R, Rd, Rr); 412 gen_ZNSf(R); 413 414 /* update output registers */ 415 tcg_gen_mov_tl(Rd, R); 416 417 tcg_temp_free_i32(R); 418 419 return true; 420 } 421 422 /* 423 * Subtracts a register and a constant and places the result in the 424 * destination register Rd. This instruction is working on Register R16 to R31 425 * and is very well suited for operations on the X, Y, and Z-pointers. 426 */ 427 static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a) 428 { 429 TCGv Rd = cpu_r[a->rd]; 430 TCGv Rr = tcg_const_i32(a->imm); 431 TCGv R = tcg_temp_new_i32(); 432 433 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */ 434 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 435 436 /* update status register */ 437 gen_sub_CHf(R, Rd, Rr); 438 gen_sub_Vf(R, Rd, Rr); 439 gen_ZNSf(R); 440 441 /* update output registers */ 442 tcg_gen_mov_tl(Rd, R); 443 444 tcg_temp_free_i32(R); 445 tcg_temp_free_i32(Rr); 446 447 return true; 448 } 449 450 /* 451 * Subtracts two registers and subtracts with the C Flag and places the 452 * result in the destination register Rd. 453 */ 454 static bool trans_SBC(DisasContext *ctx, arg_SBC *a) 455 { 456 TCGv Rd = cpu_r[a->rd]; 457 TCGv Rr = cpu_r[a->rr]; 458 TCGv R = tcg_temp_new_i32(); 459 TCGv zero = tcg_const_i32(0); 460 461 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 462 tcg_gen_sub_tl(R, R, cpu_Cf); 463 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 464 465 /* update status register */ 466 gen_sub_CHf(R, Rd, Rr); 467 gen_sub_Vf(R, Rd, Rr); 468 gen_NSf(R); 469 470 /* 471 * Previous value remains unchanged when the result is zero; 472 * cleared otherwise. 473 */ 474 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 475 476 /* update output registers */ 477 tcg_gen_mov_tl(Rd, R); 478 479 tcg_temp_free_i32(zero); 480 tcg_temp_free_i32(R); 481 482 return true; 483 } 484 485 /* 486 * SBCI -- Subtract Immediate with Carry 487 */ 488 static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a) 489 { 490 TCGv Rd = cpu_r[a->rd]; 491 TCGv Rr = tcg_const_i32(a->imm); 492 TCGv R = tcg_temp_new_i32(); 493 TCGv zero = tcg_const_i32(0); 494 495 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 496 tcg_gen_sub_tl(R, R, cpu_Cf); 497 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 498 499 /* update status register */ 500 gen_sub_CHf(R, Rd, Rr); 501 gen_sub_Vf(R, Rd, Rr); 502 gen_NSf(R); 503 504 /* 505 * Previous value remains unchanged when the result is zero; 506 * cleared otherwise. 507 */ 508 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 509 510 /* update output registers */ 511 tcg_gen_mov_tl(Rd, R); 512 513 tcg_temp_free_i32(zero); 514 tcg_temp_free_i32(R); 515 tcg_temp_free_i32(Rr); 516 517 return true; 518 } 519 520 /* 521 * Subtracts an immediate value (0-63) from a register pair and places the 522 * result in the register pair. This instruction operates on the upper four 523 * register pairs, and is well suited for operations on the Pointer Registers. 524 * This instruction is not available in all devices. Refer to the device 525 * specific instruction set summary. 526 */ 527 static bool trans_SBIW(DisasContext *ctx, arg_SBIW *a) 528 { 529 if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) { 530 return true; 531 } 532 533 TCGv RdL = cpu_r[a->rd]; 534 TCGv RdH = cpu_r[a->rd + 1]; 535 int Imm = (a->imm); 536 TCGv R = tcg_temp_new_i32(); 537 TCGv Rd = tcg_temp_new_i32(); 538 539 tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */ 540 tcg_gen_subi_tl(R, Rd, Imm); /* R = Rd - Imm */ 541 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 542 543 /* update status register */ 544 tcg_gen_andc_tl(cpu_Cf, R, Rd); 545 tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15); /* Cf = R & ~Rd */ 546 tcg_gen_andc_tl(cpu_Vf, Rd, R); 547 tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15); /* Vf = Rd & ~R */ 548 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 549 tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */ 550 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 551 552 /* update output registers */ 553 tcg_gen_andi_tl(RdL, R, 0xff); 554 tcg_gen_shri_tl(RdH, R, 8); 555 556 tcg_temp_free_i32(Rd); 557 tcg_temp_free_i32(R); 558 559 return true; 560 } 561 562 /* 563 * Performs the logical AND between the contents of register Rd and register 564 * Rr and places the result in the destination register Rd. 565 */ 566 static bool trans_AND(DisasContext *ctx, arg_AND *a) 567 { 568 TCGv Rd = cpu_r[a->rd]; 569 TCGv Rr = cpu_r[a->rr]; 570 TCGv R = tcg_temp_new_i32(); 571 572 tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */ 573 574 /* update status register */ 575 tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */ 576 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 577 gen_ZNSf(R); 578 579 /* update output registers */ 580 tcg_gen_mov_tl(Rd, R); 581 582 tcg_temp_free_i32(R); 583 584 return true; 585 } 586 587 /* 588 * Performs the logical AND between the contents of register Rd and a constant 589 * and places the result in the destination register Rd. 590 */ 591 static bool trans_ANDI(DisasContext *ctx, arg_ANDI *a) 592 { 593 TCGv Rd = cpu_r[a->rd]; 594 int Imm = (a->imm); 595 596 tcg_gen_andi_tl(Rd, Rd, Imm); /* Rd = Rd & Imm */ 597 598 /* update status register */ 599 tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */ 600 gen_ZNSf(Rd); 601 602 return true; 603 } 604 605 /* 606 * Performs the logical OR between the contents of register Rd and register 607 * Rr and places the result in the destination register Rd. 608 */ 609 static bool trans_OR(DisasContext *ctx, arg_OR *a) 610 { 611 TCGv Rd = cpu_r[a->rd]; 612 TCGv Rr = cpu_r[a->rr]; 613 TCGv R = tcg_temp_new_i32(); 614 615 tcg_gen_or_tl(R, Rd, Rr); 616 617 /* update status register */ 618 tcg_gen_movi_tl(cpu_Vf, 0); 619 gen_ZNSf(R); 620 621 /* update output registers */ 622 tcg_gen_mov_tl(Rd, R); 623 624 tcg_temp_free_i32(R); 625 626 return true; 627 } 628 629 /* 630 * Performs the logical OR between the contents of register Rd and a 631 * constant and places the result in the destination register Rd. 632 */ 633 static bool trans_ORI(DisasContext *ctx, arg_ORI *a) 634 { 635 TCGv Rd = cpu_r[a->rd]; 636 int Imm = (a->imm); 637 638 tcg_gen_ori_tl(Rd, Rd, Imm); /* Rd = Rd | Imm */ 639 640 /* update status register */ 641 tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */ 642 gen_ZNSf(Rd); 643 644 return true; 645 } 646 647 /* 648 * Performs the logical EOR between the contents of register Rd and 649 * register Rr and places the result in the destination register Rd. 650 */ 651 static bool trans_EOR(DisasContext *ctx, arg_EOR *a) 652 { 653 TCGv Rd = cpu_r[a->rd]; 654 TCGv Rr = cpu_r[a->rr]; 655 656 tcg_gen_xor_tl(Rd, Rd, Rr); 657 658 /* update status register */ 659 tcg_gen_movi_tl(cpu_Vf, 0); 660 gen_ZNSf(Rd); 661 662 return true; 663 } 664 665 /* 666 * Clears the specified bits in register Rd. Performs the logical AND 667 * between the contents of register Rd and the complement of the constant mask 668 * K. The result will be placed in register Rd. 669 */ 670 static bool trans_COM(DisasContext *ctx, arg_COM *a) 671 { 672 TCGv Rd = cpu_r[a->rd]; 673 674 tcg_gen_xori_tl(Rd, Rd, 0xff); 675 676 /* update status register */ 677 tcg_gen_movi_tl(cpu_Cf, 1); /* Cf = 1 */ 678 tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */ 679 gen_ZNSf(Rd); 680 return true; 681 } 682 683 /* 684 * Replaces the contents of register Rd with its two's complement; the 685 * value $80 is left unchanged. 686 */ 687 static bool trans_NEG(DisasContext *ctx, arg_NEG *a) 688 { 689 TCGv Rd = cpu_r[a->rd]; 690 TCGv t0 = tcg_const_i32(0); 691 TCGv R = tcg_temp_new_i32(); 692 693 tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */ 694 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 695 696 /* update status register */ 697 gen_sub_CHf(R, t0, Rd); 698 gen_sub_Vf(R, t0, Rd); 699 gen_ZNSf(R); 700 701 /* update output registers */ 702 tcg_gen_mov_tl(Rd, R); 703 704 tcg_temp_free_i32(t0); 705 tcg_temp_free_i32(R); 706 707 return true; 708 } 709 710 /* 711 * Adds one -1- to the contents of register Rd and places the result in the 712 * destination register Rd. The C Flag in SREG is not affected by the 713 * operation, thus allowing the INC instruction to be used on a loop counter in 714 * multiple-precision computations. When operating on unsigned numbers, only 715 * BREQ and BRNE branches can be expected to perform consistently. When 716 * operating on two's complement values, all signed branches are available. 717 */ 718 static bool trans_INC(DisasContext *ctx, arg_INC *a) 719 { 720 TCGv Rd = cpu_r[a->rd]; 721 722 tcg_gen_addi_tl(Rd, Rd, 1); 723 tcg_gen_andi_tl(Rd, Rd, 0xff); 724 725 /* update status register */ 726 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x80); /* Vf = Rd == 0x80 */ 727 gen_ZNSf(Rd); 728 729 return true; 730 } 731 732 /* 733 * Subtracts one -1- from the contents of register Rd and places the result 734 * in the destination register Rd. The C Flag in SREG is not affected by the 735 * operation, thus allowing the DEC instruction to be used on a loop counter in 736 * multiple-precision computations. When operating on unsigned values, only 737 * BREQ and BRNE branches can be expected to perform consistently. When 738 * operating on two's complement values, all signed branches are available. 739 */ 740 static bool trans_DEC(DisasContext *ctx, arg_DEC *a) 741 { 742 TCGv Rd = cpu_r[a->rd]; 743 744 tcg_gen_subi_tl(Rd, Rd, 1); /* Rd = Rd - 1 */ 745 tcg_gen_andi_tl(Rd, Rd, 0xff); /* make it 8 bits */ 746 747 /* update status register */ 748 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x7f); /* Vf = Rd == 0x7f */ 749 gen_ZNSf(Rd); 750 751 return true; 752 } 753 754 /* 755 * This instruction performs 8-bit x 8-bit -> 16-bit unsigned multiplication. 756 */ 757 static bool trans_MUL(DisasContext *ctx, arg_MUL *a) 758 { 759 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 760 return true; 761 } 762 763 TCGv R0 = cpu_r[0]; 764 TCGv R1 = cpu_r[1]; 765 TCGv Rd = cpu_r[a->rd]; 766 TCGv Rr = cpu_r[a->rr]; 767 TCGv R = tcg_temp_new_i32(); 768 769 tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd * Rr */ 770 tcg_gen_andi_tl(R0, R, 0xff); 771 tcg_gen_shri_tl(R1, R, 8); 772 773 /* update status register */ 774 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 775 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 776 777 tcg_temp_free_i32(R); 778 779 return true; 780 } 781 782 /* 783 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication. 784 */ 785 static bool trans_MULS(DisasContext *ctx, arg_MULS *a) 786 { 787 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 788 return true; 789 } 790 791 TCGv R0 = cpu_r[0]; 792 TCGv R1 = cpu_r[1]; 793 TCGv Rd = cpu_r[a->rd]; 794 TCGv Rr = cpu_r[a->rr]; 795 TCGv R = tcg_temp_new_i32(); 796 TCGv t0 = tcg_temp_new_i32(); 797 TCGv t1 = tcg_temp_new_i32(); 798 799 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 800 tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */ 801 tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */ 802 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 803 tcg_gen_andi_tl(R0, R, 0xff); 804 tcg_gen_shri_tl(R1, R, 8); 805 806 /* update status register */ 807 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 808 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 809 810 tcg_temp_free_i32(t1); 811 tcg_temp_free_i32(t0); 812 tcg_temp_free_i32(R); 813 814 return true; 815 } 816 817 /* 818 * This instruction performs 8-bit x 8-bit -> 16-bit multiplication of a 819 * signed and an unsigned number. 820 */ 821 static bool trans_MULSU(DisasContext *ctx, arg_MULSU *a) 822 { 823 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 824 return true; 825 } 826 827 TCGv R0 = cpu_r[0]; 828 TCGv R1 = cpu_r[1]; 829 TCGv Rd = cpu_r[a->rd]; 830 TCGv Rr = cpu_r[a->rr]; 831 TCGv R = tcg_temp_new_i32(); 832 TCGv t0 = tcg_temp_new_i32(); 833 834 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 835 tcg_gen_mul_tl(R, t0, Rr); /* R = Rd * Rr */ 836 tcg_gen_andi_tl(R, R, 0xffff); /* make R 16 bits */ 837 tcg_gen_andi_tl(R0, R, 0xff); 838 tcg_gen_shri_tl(R1, R, 8); 839 840 /* update status register */ 841 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 842 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 843 844 tcg_temp_free_i32(t0); 845 tcg_temp_free_i32(R); 846 847 return true; 848 } 849 850 /* 851 * This instruction performs 8-bit x 8-bit -> 16-bit unsigned 852 * multiplication and shifts the result one bit left. 853 */ 854 static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a) 855 { 856 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 857 return true; 858 } 859 860 TCGv R0 = cpu_r[0]; 861 TCGv R1 = cpu_r[1]; 862 TCGv Rd = cpu_r[a->rd]; 863 TCGv Rr = cpu_r[a->rr]; 864 TCGv R = tcg_temp_new_i32(); 865 866 tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd * Rr */ 867 868 /* update status register */ 869 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 870 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 871 872 /* update output registers */ 873 tcg_gen_shli_tl(R, R, 1); 874 tcg_gen_andi_tl(R0, R, 0xff); 875 tcg_gen_shri_tl(R1, R, 8); 876 tcg_gen_andi_tl(R1, R1, 0xff); 877 878 879 tcg_temp_free_i32(R); 880 881 return true; 882 } 883 884 /* 885 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication 886 * and shifts the result one bit left. 887 */ 888 static bool trans_FMULS(DisasContext *ctx, arg_FMULS *a) 889 { 890 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 891 return true; 892 } 893 894 TCGv R0 = cpu_r[0]; 895 TCGv R1 = cpu_r[1]; 896 TCGv Rd = cpu_r[a->rd]; 897 TCGv Rr = cpu_r[a->rr]; 898 TCGv R = tcg_temp_new_i32(); 899 TCGv t0 = tcg_temp_new_i32(); 900 TCGv t1 = tcg_temp_new_i32(); 901 902 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 903 tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */ 904 tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */ 905 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 906 907 /* update status register */ 908 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 909 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 910 911 /* update output registers */ 912 tcg_gen_shli_tl(R, R, 1); 913 tcg_gen_andi_tl(R0, R, 0xff); 914 tcg_gen_shri_tl(R1, R, 8); 915 tcg_gen_andi_tl(R1, R1, 0xff); 916 917 tcg_temp_free_i32(t1); 918 tcg_temp_free_i32(t0); 919 tcg_temp_free_i32(R); 920 921 return true; 922 } 923 924 /* 925 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication 926 * and shifts the result one bit left. 927 */ 928 static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU *a) 929 { 930 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 931 return true; 932 } 933 934 TCGv R0 = cpu_r[0]; 935 TCGv R1 = cpu_r[1]; 936 TCGv Rd = cpu_r[a->rd]; 937 TCGv Rr = cpu_r[a->rr]; 938 TCGv R = tcg_temp_new_i32(); 939 TCGv t0 = tcg_temp_new_i32(); 940 941 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 942 tcg_gen_mul_tl(R, t0, Rr); /* R = Rd * Rr */ 943 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 944 945 /* update status register */ 946 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 947 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 948 949 /* update output registers */ 950 tcg_gen_shli_tl(R, R, 1); 951 tcg_gen_andi_tl(R0, R, 0xff); 952 tcg_gen_shri_tl(R1, R, 8); 953 tcg_gen_andi_tl(R1, R1, 0xff); 954 955 tcg_temp_free_i32(t0); 956 tcg_temp_free_i32(R); 957 958 return true; 959 } 960 961 /* 962 * The module is an instruction set extension to the AVR CPU, performing 963 * DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in 964 * the CPU register file, registers R0-R7, where LSB of data is placed in LSB 965 * of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (including 966 * parity bits) is placed in registers R8- R15, organized in the register file 967 * with LSB of key in LSB of R8 and MSB of key in MSB of R15. Executing one DES 968 * instruction performs one round in the DES algorithm. Sixteen rounds must be 969 * executed in increasing order to form the correct DES ciphertext or 970 * plaintext. Intermediate results are stored in the register file (R0-R15) 971 * after each DES instruction. The instruction's operand (K) determines which 972 * round is executed, and the half carry flag (H) determines whether encryption 973 * or decryption is performed. The DES algorithm is described in 974 * "Specifications for the Data Encryption Standard" (Federal Information 975 * Processing Standards Publication 46). Intermediate results in this 976 * implementation differ from the standard because the initial permutation and 977 * the inverse initial permutation are performed each iteration. This does not 978 * affect the result in the final ciphertext or plaintext, but reduces 979 * execution time. 980 */ 981 static bool trans_DES(DisasContext *ctx, arg_DES *a) 982 { 983 /* TODO */ 984 if (!avr_have_feature(ctx, AVR_FEATURE_DES)) { 985 return true; 986 } 987 988 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); 989 990 return true; 991 } 992 993 /* 994 * Branch Instructions 995 */ 996 static void gen_jmp_ez(DisasContext *ctx) 997 { 998 tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8); 999 tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind); 1000 ctx->base.is_jmp = DISAS_LOOKUP; 1001 } 1002 1003 static void gen_jmp_z(DisasContext *ctx) 1004 { 1005 tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8); 1006 ctx->base.is_jmp = DISAS_LOOKUP; 1007 } 1008 1009 static void gen_push_ret(DisasContext *ctx, int ret) 1010 { 1011 if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { 1012 1013 TCGv t0 = tcg_const_i32((ret & 0x0000ff)); 1014 1015 tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB); 1016 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1017 1018 tcg_temp_free_i32(t0); 1019 } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { 1020 1021 TCGv t0 = tcg_const_i32((ret & 0x00ffff)); 1022 1023 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1024 tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1025 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1026 1027 tcg_temp_free_i32(t0); 1028 1029 } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { 1030 1031 TCGv lo = tcg_const_i32((ret & 0x0000ff)); 1032 TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8); 1033 1034 tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); 1035 tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); 1036 tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1037 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1038 1039 tcg_temp_free_i32(lo); 1040 tcg_temp_free_i32(hi); 1041 } 1042 } 1043 1044 static void gen_pop_ret(DisasContext *ctx, TCGv ret) 1045 { 1046 if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { 1047 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1048 tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB); 1049 } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { 1050 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1051 tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1052 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1053 } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { 1054 TCGv lo = tcg_temp_new_i32(); 1055 TCGv hi = tcg_temp_new_i32(); 1056 1057 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1058 tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1059 1060 tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); 1061 tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); 1062 1063 tcg_gen_deposit_tl(ret, lo, hi, 8, 16); 1064 1065 tcg_temp_free_i32(lo); 1066 tcg_temp_free_i32(hi); 1067 } 1068 } 1069 1070 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 1071 { 1072 const TranslationBlock *tb = ctx->base.tb; 1073 1074 if (translator_use_goto_tb(&ctx->base, dest)) { 1075 tcg_gen_goto_tb(n); 1076 tcg_gen_movi_i32(cpu_pc, dest); 1077 tcg_gen_exit_tb(tb, n); 1078 } else { 1079 tcg_gen_movi_i32(cpu_pc, dest); 1080 tcg_gen_lookup_and_goto_ptr(); 1081 } 1082 ctx->base.is_jmp = DISAS_NORETURN; 1083 } 1084 1085 /* 1086 * Relative jump to an address within PC - 2K +1 and PC + 2K (words). For 1087 * AVR microcontrollers with Program memory not exceeding 4K words (8KB) this 1088 * instruction can address the entire memory from every address location. See 1089 * also JMP. 1090 */ 1091 static bool trans_RJMP(DisasContext *ctx, arg_RJMP *a) 1092 { 1093 int dst = ctx->npc + a->imm; 1094 1095 gen_goto_tb(ctx, 0, dst); 1096 1097 return true; 1098 } 1099 1100 /* 1101 * Indirect jump to the address pointed to by the Z (16 bits) Pointer 1102 * Register in the Register File. The Z-pointer Register is 16 bits wide and 1103 * allows jump within the lowest 64K words (128KB) section of Program memory. 1104 * This instruction is not available in all devices. Refer to the device 1105 * specific instruction set summary. 1106 */ 1107 static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a) 1108 { 1109 if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) { 1110 return true; 1111 } 1112 1113 gen_jmp_z(ctx); 1114 1115 return true; 1116 } 1117 1118 /* 1119 * Indirect jump to the address pointed to by the Z (16 bits) Pointer 1120 * Register in the Register File and the EIND Register in the I/O space. This 1121 * instruction allows for indirect jumps to the entire 4M (words) Program 1122 * memory space. See also IJMP. This instruction is not available in all 1123 * devices. Refer to the device specific instruction set summary. 1124 */ 1125 static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a) 1126 { 1127 if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) { 1128 return true; 1129 } 1130 1131 gen_jmp_ez(ctx); 1132 return true; 1133 } 1134 1135 /* 1136 * Jump to an address within the entire 4M (words) Program memory. See also 1137 * RJMP. This instruction is not available in all devices. Refer to the device 1138 * specific instruction set summary.0 1139 */ 1140 static bool trans_JMP(DisasContext *ctx, arg_JMP *a) 1141 { 1142 if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) { 1143 return true; 1144 } 1145 1146 gen_goto_tb(ctx, 0, a->imm); 1147 1148 return true; 1149 } 1150 1151 /* 1152 * Relative call to an address within PC - 2K + 1 and PC + 2K (words). The 1153 * return address (the instruction after the RCALL) is stored onto the Stack. 1154 * See also CALL. For AVR microcontrollers with Program memory not exceeding 4K 1155 * words (8KB) this instruction can address the entire memory from every 1156 * address location. The Stack Pointer uses a post-decrement scheme during 1157 * RCALL. 1158 */ 1159 static bool trans_RCALL(DisasContext *ctx, arg_RCALL *a) 1160 { 1161 int ret = ctx->npc; 1162 int dst = ctx->npc + a->imm; 1163 1164 gen_push_ret(ctx, ret); 1165 gen_goto_tb(ctx, 0, dst); 1166 1167 return true; 1168 } 1169 1170 /* 1171 * Calls to a subroutine within the entire 4M (words) Program memory. The 1172 * return address (to the instruction after the CALL) will be stored onto the 1173 * Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during 1174 * CALL. This instruction is not available in all devices. Refer to the device 1175 * specific instruction set summary. 1176 */ 1177 static bool trans_ICALL(DisasContext *ctx, arg_ICALL *a) 1178 { 1179 if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) { 1180 return true; 1181 } 1182 1183 int ret = ctx->npc; 1184 1185 gen_push_ret(ctx, ret); 1186 gen_jmp_z(ctx); 1187 1188 return true; 1189 } 1190 1191 /* 1192 * Indirect call of a subroutine pointed to by the Z (16 bits) Pointer 1193 * Register in the Register File and the EIND Register in the I/O space. This 1194 * instruction allows for indirect calls to the entire 4M (words) Program 1195 * memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme 1196 * during EICALL. This instruction is not available in all devices. Refer to 1197 * the device specific instruction set summary. 1198 */ 1199 static bool trans_EICALL(DisasContext *ctx, arg_EICALL *a) 1200 { 1201 if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) { 1202 return true; 1203 } 1204 1205 int ret = ctx->npc; 1206 1207 gen_push_ret(ctx, ret); 1208 gen_jmp_ez(ctx); 1209 return true; 1210 } 1211 1212 /* 1213 * Calls to a subroutine within the entire Program memory. The return 1214 * address (to the instruction after the CALL) will be stored onto the Stack. 1215 * (See also RCALL). The Stack Pointer uses a post-decrement scheme during 1216 * CALL. This instruction is not available in all devices. Refer to the device 1217 * specific instruction set summary. 1218 */ 1219 static bool trans_CALL(DisasContext *ctx, arg_CALL *a) 1220 { 1221 if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) { 1222 return true; 1223 } 1224 1225 int Imm = a->imm; 1226 int ret = ctx->npc; 1227 1228 gen_push_ret(ctx, ret); 1229 gen_goto_tb(ctx, 0, Imm); 1230 1231 return true; 1232 } 1233 1234 /* 1235 * Returns from subroutine. The return address is loaded from the STACK. 1236 * The Stack Pointer uses a preincrement scheme during RET. 1237 */ 1238 static bool trans_RET(DisasContext *ctx, arg_RET *a) 1239 { 1240 gen_pop_ret(ctx, cpu_pc); 1241 1242 ctx->base.is_jmp = DISAS_LOOKUP; 1243 return true; 1244 } 1245 1246 /* 1247 * Returns from interrupt. The return address is loaded from the STACK and 1248 * the Global Interrupt Flag is set. Note that the Status Register is not 1249 * automatically stored when entering an interrupt routine, and it is not 1250 * restored when returning from an interrupt routine. This must be handled by 1251 * the application program. The Stack Pointer uses a pre-increment scheme 1252 * during RETI. 1253 */ 1254 static bool trans_RETI(DisasContext *ctx, arg_RETI *a) 1255 { 1256 gen_pop_ret(ctx, cpu_pc); 1257 tcg_gen_movi_tl(cpu_If, 1); 1258 1259 /* Need to return to main loop to re-evaluate interrupts. */ 1260 ctx->base.is_jmp = DISAS_EXIT; 1261 return true; 1262 } 1263 1264 /* 1265 * This instruction performs a compare between two registers Rd and Rr, and 1266 * skips the next instruction if Rd = Rr. 1267 */ 1268 static bool trans_CPSE(DisasContext *ctx, arg_CPSE *a) 1269 { 1270 ctx->skip_cond = TCG_COND_EQ; 1271 ctx->skip_var0 = cpu_r[a->rd]; 1272 ctx->skip_var1 = cpu_r[a->rr]; 1273 return true; 1274 } 1275 1276 /* 1277 * This instruction performs a compare between two registers Rd and Rr. 1278 * None of the registers are changed. All conditional branches can be used 1279 * after this instruction. 1280 */ 1281 static bool trans_CP(DisasContext *ctx, arg_CP *a) 1282 { 1283 TCGv Rd = cpu_r[a->rd]; 1284 TCGv Rr = cpu_r[a->rr]; 1285 TCGv R = tcg_temp_new_i32(); 1286 1287 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 1288 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 1289 1290 /* update status register */ 1291 gen_sub_CHf(R, Rd, Rr); 1292 gen_sub_Vf(R, Rd, Rr); 1293 gen_ZNSf(R); 1294 1295 tcg_temp_free_i32(R); 1296 1297 return true; 1298 } 1299 1300 /* 1301 * This instruction performs a compare between two registers Rd and Rr and 1302 * also takes into account the previous carry. None of the registers are 1303 * changed. All conditional branches can be used after this instruction. 1304 */ 1305 static bool trans_CPC(DisasContext *ctx, arg_CPC *a) 1306 { 1307 TCGv Rd = cpu_r[a->rd]; 1308 TCGv Rr = cpu_r[a->rr]; 1309 TCGv R = tcg_temp_new_i32(); 1310 TCGv zero = tcg_const_i32(0); 1311 1312 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 1313 tcg_gen_sub_tl(R, R, cpu_Cf); 1314 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 1315 /* update status register */ 1316 gen_sub_CHf(R, Rd, Rr); 1317 gen_sub_Vf(R, Rd, Rr); 1318 gen_NSf(R); 1319 1320 /* 1321 * Previous value remains unchanged when the result is zero; 1322 * cleared otherwise. 1323 */ 1324 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 1325 1326 tcg_temp_free_i32(zero); 1327 tcg_temp_free_i32(R); 1328 1329 return true; 1330 } 1331 1332 /* 1333 * This instruction performs a compare between register Rd and a constant. 1334 * The register is not changed. All conditional branches can be used after this 1335 * instruction. 1336 */ 1337 static bool trans_CPI(DisasContext *ctx, arg_CPI *a) 1338 { 1339 TCGv Rd = cpu_r[a->rd]; 1340 int Imm = a->imm; 1341 TCGv Rr = tcg_const_i32(Imm); 1342 TCGv R = tcg_temp_new_i32(); 1343 1344 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 1345 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 1346 1347 /* update status register */ 1348 gen_sub_CHf(R, Rd, Rr); 1349 gen_sub_Vf(R, Rd, Rr); 1350 gen_ZNSf(R); 1351 1352 tcg_temp_free_i32(R); 1353 tcg_temp_free_i32(Rr); 1354 1355 return true; 1356 } 1357 1358 /* 1359 * This instruction tests a single bit in a register and skips the next 1360 * instruction if the bit is cleared. 1361 */ 1362 static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a) 1363 { 1364 TCGv Rr = cpu_r[a->rr]; 1365 1366 ctx->skip_cond = TCG_COND_EQ; 1367 ctx->skip_var0 = tcg_temp_new(); 1368 1369 tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); 1370 return true; 1371 } 1372 1373 /* 1374 * This instruction tests a single bit in a register and skips the next 1375 * instruction if the bit is set. 1376 */ 1377 static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) 1378 { 1379 TCGv Rr = cpu_r[a->rr]; 1380 1381 ctx->skip_cond = TCG_COND_NE; 1382 ctx->skip_var0 = tcg_temp_new(); 1383 1384 tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); 1385 return true; 1386 } 1387 1388 /* 1389 * This instruction tests a single bit in an I/O Register and skips the 1390 * next instruction if the bit is cleared. This instruction operates on the 1391 * lower 32 I/O Registers -- addresses 0-31. 1392 */ 1393 static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) 1394 { 1395 TCGv temp = tcg_const_i32(a->reg); 1396 1397 gen_helper_inb(temp, cpu_env, temp); 1398 tcg_gen_andi_tl(temp, temp, 1 << a->bit); 1399 ctx->skip_cond = TCG_COND_EQ; 1400 ctx->skip_var0 = temp; 1401 1402 return true; 1403 } 1404 1405 /* 1406 * This instruction tests a single bit in an I/O Register and skips the 1407 * next instruction if the bit is set. This instruction operates on the lower 1408 * 32 I/O Registers -- addresses 0-31. 1409 */ 1410 static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) 1411 { 1412 TCGv temp = tcg_const_i32(a->reg); 1413 1414 gen_helper_inb(temp, cpu_env, temp); 1415 tcg_gen_andi_tl(temp, temp, 1 << a->bit); 1416 ctx->skip_cond = TCG_COND_NE; 1417 ctx->skip_var0 = temp; 1418 1419 return true; 1420 } 1421 1422 /* 1423 * Conditional relative branch. Tests a single bit in SREG and branches 1424 * relatively to PC if the bit is cleared. This instruction branches relatively 1425 * to PC in either direction (PC - 63 < = destination <= PC + 64). The 1426 * parameter k is the offset from PC and is represented in two's complement 1427 * form. 1428 */ 1429 static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a) 1430 { 1431 TCGLabel *not_taken = gen_new_label(); 1432 1433 TCGv var; 1434 1435 switch (a->bit) { 1436 case 0x00: 1437 var = cpu_Cf; 1438 break; 1439 case 0x01: 1440 var = cpu_Zf; 1441 break; 1442 case 0x02: 1443 var = cpu_Nf; 1444 break; 1445 case 0x03: 1446 var = cpu_Vf; 1447 break; 1448 case 0x04: 1449 var = cpu_Sf; 1450 break; 1451 case 0x05: 1452 var = cpu_Hf; 1453 break; 1454 case 0x06: 1455 var = cpu_Tf; 1456 break; 1457 case 0x07: 1458 var = cpu_If; 1459 break; 1460 default: 1461 g_assert_not_reached(); 1462 } 1463 1464 tcg_gen_brcondi_i32(TCG_COND_NE, var, 0, not_taken); 1465 gen_goto_tb(ctx, 0, ctx->npc + a->imm); 1466 gen_set_label(not_taken); 1467 1468 ctx->base.is_jmp = DISAS_CHAIN; 1469 return true; 1470 } 1471 1472 /* 1473 * Conditional relative branch. Tests a single bit in SREG and branches 1474 * relatively to PC if the bit is set. This instruction branches relatively to 1475 * PC in either direction (PC - 63 < = destination <= PC + 64). The parameter k 1476 * is the offset from PC and is represented in two's complement form. 1477 */ 1478 static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a) 1479 { 1480 TCGLabel *not_taken = gen_new_label(); 1481 1482 TCGv var; 1483 1484 switch (a->bit) { 1485 case 0x00: 1486 var = cpu_Cf; 1487 break; 1488 case 0x01: 1489 var = cpu_Zf; 1490 break; 1491 case 0x02: 1492 var = cpu_Nf; 1493 break; 1494 case 0x03: 1495 var = cpu_Vf; 1496 break; 1497 case 0x04: 1498 var = cpu_Sf; 1499 break; 1500 case 0x05: 1501 var = cpu_Hf; 1502 break; 1503 case 0x06: 1504 var = cpu_Tf; 1505 break; 1506 case 0x07: 1507 var = cpu_If; 1508 break; 1509 default: 1510 g_assert_not_reached(); 1511 } 1512 1513 tcg_gen_brcondi_i32(TCG_COND_EQ, var, 0, not_taken); 1514 gen_goto_tb(ctx, 0, ctx->npc + a->imm); 1515 gen_set_label(not_taken); 1516 1517 ctx->base.is_jmp = DISAS_CHAIN; 1518 return true; 1519 } 1520 1521 /* 1522 * Data Transfer Instructions 1523 */ 1524 1525 /* 1526 * in the gen_set_addr & gen_get_addr functions 1527 * H assumed to be in 0x00ff0000 format 1528 * M assumed to be in 0x000000ff format 1529 * L assumed to be in 0x000000ff format 1530 */ 1531 static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L) 1532 { 1533 1534 tcg_gen_andi_tl(L, addr, 0x000000ff); 1535 1536 tcg_gen_andi_tl(M, addr, 0x0000ff00); 1537 tcg_gen_shri_tl(M, M, 8); 1538 1539 tcg_gen_andi_tl(H, addr, 0x00ff0000); 1540 } 1541 1542 static void gen_set_xaddr(TCGv addr) 1543 { 1544 gen_set_addr(addr, cpu_rampX, cpu_r[27], cpu_r[26]); 1545 } 1546 1547 static void gen_set_yaddr(TCGv addr) 1548 { 1549 gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]); 1550 } 1551 1552 static void gen_set_zaddr(TCGv addr) 1553 { 1554 gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]); 1555 } 1556 1557 static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L) 1558 { 1559 TCGv addr = tcg_temp_new_i32(); 1560 1561 tcg_gen_deposit_tl(addr, M, H, 8, 8); 1562 tcg_gen_deposit_tl(addr, L, addr, 8, 16); 1563 1564 return addr; 1565 } 1566 1567 static TCGv gen_get_xaddr(void) 1568 { 1569 return gen_get_addr(cpu_rampX, cpu_r[27], cpu_r[26]); 1570 } 1571 1572 static TCGv gen_get_yaddr(void) 1573 { 1574 return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]); 1575 } 1576 1577 static TCGv gen_get_zaddr(void) 1578 { 1579 return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]); 1580 } 1581 1582 /* 1583 * Load one byte indirect from data space to register and stores an clear 1584 * the bits in data space specified by the register. The instruction can only 1585 * be used towards internal SRAM. The data location is pointed to by the Z (16 1586 * bits) Pointer Register in the Register File. Memory access is limited to the 1587 * current data segment of 64KB. To access another data segment in devices with 1588 * more than 64KB data space, the RAMPZ in register in the I/O area has to be 1589 * changed. The Z-pointer Register is left unchanged by the operation. This 1590 * instruction is especially suited for clearing status bits stored in SRAM. 1591 */ 1592 static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) 1593 { 1594 if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { 1595 gen_helper_fullwr(cpu_env, data, addr); 1596 } else { 1597 tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */ 1598 } 1599 } 1600 1601 static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) 1602 { 1603 if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { 1604 gen_helper_fullrd(data, cpu_env, addr); 1605 } else { 1606 tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */ 1607 } 1608 } 1609 1610 /* 1611 * This instruction makes a copy of one register into another. The source 1612 * register Rr is left unchanged, while the destination register Rd is loaded 1613 * with a copy of Rr. 1614 */ 1615 static bool trans_MOV(DisasContext *ctx, arg_MOV *a) 1616 { 1617 TCGv Rd = cpu_r[a->rd]; 1618 TCGv Rr = cpu_r[a->rr]; 1619 1620 tcg_gen_mov_tl(Rd, Rr); 1621 1622 return true; 1623 } 1624 1625 /* 1626 * This instruction makes a copy of one register pair into another register 1627 * pair. The source register pair Rr+1:Rr is left unchanged, while the 1628 * destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr. This 1629 * instruction is not available in all devices. Refer to the device specific 1630 * instruction set summary. 1631 */ 1632 static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a) 1633 { 1634 if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) { 1635 return true; 1636 } 1637 1638 TCGv RdL = cpu_r[a->rd]; 1639 TCGv RdH = cpu_r[a->rd + 1]; 1640 TCGv RrL = cpu_r[a->rr]; 1641 TCGv RrH = cpu_r[a->rr + 1]; 1642 1643 tcg_gen_mov_tl(RdH, RrH); 1644 tcg_gen_mov_tl(RdL, RrL); 1645 1646 return true; 1647 } 1648 1649 /* 1650 * Loads an 8 bit constant directly to register 16 to 31. 1651 */ 1652 static bool trans_LDI(DisasContext *ctx, arg_LDI *a) 1653 { 1654 TCGv Rd = cpu_r[a->rd]; 1655 int imm = a->imm; 1656 1657 tcg_gen_movi_tl(Rd, imm); 1658 1659 return true; 1660 } 1661 1662 /* 1663 * Loads one byte from the data space to a register. For parts with SRAM, 1664 * the data space consists of the Register File, I/O memory and internal SRAM 1665 * (and external SRAM if applicable). For parts without SRAM, the data space 1666 * consists of the register file only. The EEPROM has a separate address space. 1667 * A 16-bit address must be supplied. Memory access is limited to the current 1668 * data segment of 64KB. The LDS instruction uses the RAMPD Register to access 1669 * memory above 64KB. To access another data segment in devices with more than 1670 * 64KB data space, the RAMPD in register in the I/O area has to be changed. 1671 * This instruction is not available in all devices. Refer to the device 1672 * specific instruction set summary. 1673 */ 1674 static bool trans_LDS(DisasContext *ctx, arg_LDS *a) 1675 { 1676 TCGv Rd = cpu_r[a->rd]; 1677 TCGv addr = tcg_temp_new_i32(); 1678 TCGv H = cpu_rampD; 1679 a->imm = next_word(ctx); 1680 1681 tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ 1682 tcg_gen_shli_tl(addr, addr, 16); 1683 tcg_gen_ori_tl(addr, addr, a->imm); 1684 1685 gen_data_load(ctx, Rd, addr); 1686 1687 tcg_temp_free_i32(addr); 1688 1689 return true; 1690 } 1691 1692 /* 1693 * Loads one byte indirect from the data space to a register. For parts 1694 * with SRAM, the data space consists of the Register File, I/O memory and 1695 * internal SRAM (and external SRAM if applicable). For parts without SRAM, the 1696 * data space consists of the Register File only. In some parts the Flash 1697 * Memory has been mapped to the data space and can be read using this command. 1698 * The EEPROM has a separate address space. The data location is pointed to by 1699 * the X (16 bits) Pointer Register in the Register File. Memory access is 1700 * limited to the current data segment of 64KB. To access another data segment 1701 * in devices with more than 64KB data space, the RAMPX in register in the I/O 1702 * area has to be changed. The X-pointer Register can either be left unchanged 1703 * by the operation, or it can be post-incremented or predecremented. These 1704 * features are especially suited for accessing arrays, tables, and Stack 1705 * Pointer usage of the X-pointer Register. Note that only the low byte of the 1706 * X-pointer is updated in devices with no more than 256 bytes data space. For 1707 * such devices, the high byte of the pointer is not used by this instruction 1708 * and can be used for other purposes. The RAMPX Register in the I/O area is 1709 * updated in parts with more than 64KB data space or more than 64KB Program 1710 * memory, and the increment/decrement is added to the entire 24-bit address on 1711 * such devices. Not all variants of this instruction is available in all 1712 * devices. Refer to the device specific instruction set summary. In the 1713 * Reduced Core tinyAVR the LD instruction can be used to achieve the same 1714 * operation as LPM since the program memory is mapped to the data memory 1715 * space. 1716 */ 1717 static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a) 1718 { 1719 TCGv Rd = cpu_r[a->rd]; 1720 TCGv addr = gen_get_xaddr(); 1721 1722 gen_data_load(ctx, Rd, addr); 1723 1724 tcg_temp_free_i32(addr); 1725 1726 return true; 1727 } 1728 1729 static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a) 1730 { 1731 TCGv Rd = cpu_r[a->rd]; 1732 TCGv addr = gen_get_xaddr(); 1733 1734 gen_data_load(ctx, Rd, addr); 1735 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1736 1737 gen_set_xaddr(addr); 1738 1739 tcg_temp_free_i32(addr); 1740 1741 return true; 1742 } 1743 1744 static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a) 1745 { 1746 TCGv Rd = cpu_r[a->rd]; 1747 TCGv addr = gen_get_xaddr(); 1748 1749 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1750 gen_data_load(ctx, Rd, addr); 1751 gen_set_xaddr(addr); 1752 1753 tcg_temp_free_i32(addr); 1754 1755 return true; 1756 } 1757 1758 /* 1759 * Loads one byte indirect with or without displacement from the data space 1760 * to a register. For parts with SRAM, the data space consists of the Register 1761 * File, I/O memory and internal SRAM (and external SRAM if applicable). For 1762 * parts without SRAM, the data space consists of the Register File only. In 1763 * some parts the Flash Memory has been mapped to the data space and can be 1764 * read using this command. The EEPROM has a separate address space. The data 1765 * location is pointed to by the Y (16 bits) Pointer Register in the Register 1766 * File. Memory access is limited to the current data segment of 64KB. To 1767 * access another data segment in devices with more than 64KB data space, the 1768 * RAMPY in register in the I/O area has to be changed. The Y-pointer Register 1769 * can either be left unchanged by the operation, or it can be post-incremented 1770 * or predecremented. These features are especially suited for accessing 1771 * arrays, tables, and Stack Pointer usage of the Y-pointer Register. Note that 1772 * only the low byte of the Y-pointer is updated in devices with no more than 1773 * 256 bytes data space. For such devices, the high byte of the pointer is not 1774 * used by this instruction and can be used for other purposes. The RAMPY 1775 * Register in the I/O area is updated in parts with more than 64KB data space 1776 * or more than 64KB Program memory, and the increment/decrement/displacement 1777 * is added to the entire 24-bit address on such devices. Not all variants of 1778 * this instruction is available in all devices. Refer to the device specific 1779 * instruction set summary. In the Reduced Core tinyAVR the LD instruction can 1780 * be used to achieve the same operation as LPM since the program memory is 1781 * mapped to the data memory space. 1782 */ 1783 static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a) 1784 { 1785 TCGv Rd = cpu_r[a->rd]; 1786 TCGv addr = gen_get_yaddr(); 1787 1788 gen_data_load(ctx, Rd, addr); 1789 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1790 1791 gen_set_yaddr(addr); 1792 1793 tcg_temp_free_i32(addr); 1794 1795 return true; 1796 } 1797 1798 static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a) 1799 { 1800 TCGv Rd = cpu_r[a->rd]; 1801 TCGv addr = gen_get_yaddr(); 1802 1803 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1804 gen_data_load(ctx, Rd, addr); 1805 gen_set_yaddr(addr); 1806 1807 tcg_temp_free_i32(addr); 1808 1809 return true; 1810 } 1811 1812 static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a) 1813 { 1814 TCGv Rd = cpu_r[a->rd]; 1815 TCGv addr = gen_get_yaddr(); 1816 1817 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 1818 gen_data_load(ctx, Rd, addr); 1819 1820 tcg_temp_free_i32(addr); 1821 1822 return true; 1823 } 1824 1825 /* 1826 * Loads one byte indirect with or without displacement from the data space 1827 * to a register. For parts with SRAM, the data space consists of the Register 1828 * File, I/O memory and internal SRAM (and external SRAM if applicable). For 1829 * parts without SRAM, the data space consists of the Register File only. In 1830 * some parts the Flash Memory has been mapped to the data space and can be 1831 * read using this command. The EEPROM has a separate address space. The data 1832 * location is pointed to by the Z (16 bits) Pointer Register in the Register 1833 * File. Memory access is limited to the current data segment of 64KB. To 1834 * access another data segment in devices with more than 64KB data space, the 1835 * RAMPZ in register in the I/O area has to be changed. The Z-pointer Register 1836 * can either be left unchanged by the operation, or it can be post-incremented 1837 * or predecremented. These features are especially suited for Stack Pointer 1838 * usage of the Z-pointer Register, however because the Z-pointer Register can 1839 * be used for indirect subroutine calls, indirect jumps and table lookup, it 1840 * is often more convenient to use the X or Y-pointer as a dedicated Stack 1841 * Pointer. Note that only the low byte of the Z-pointer is updated in devices 1842 * with no more than 256 bytes data space. For such devices, the high byte of 1843 * the pointer is not used by this instruction and can be used for other 1844 * purposes. The RAMPZ Register in the I/O area is updated in parts with more 1845 * than 64KB data space or more than 64KB Program memory, and the 1846 * increment/decrement/displacement is added to the entire 24-bit address on 1847 * such devices. Not all variants of this instruction is available in all 1848 * devices. Refer to the device specific instruction set summary. In the 1849 * Reduced Core tinyAVR the LD instruction can be used to achieve the same 1850 * operation as LPM since the program memory is mapped to the data memory 1851 * space. For using the Z-pointer for table lookup in Program memory see the 1852 * LPM and ELPM instructions. 1853 */ 1854 static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a) 1855 { 1856 TCGv Rd = cpu_r[a->rd]; 1857 TCGv addr = gen_get_zaddr(); 1858 1859 gen_data_load(ctx, Rd, addr); 1860 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1861 1862 gen_set_zaddr(addr); 1863 1864 tcg_temp_free_i32(addr); 1865 1866 return true; 1867 } 1868 1869 static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a) 1870 { 1871 TCGv Rd = cpu_r[a->rd]; 1872 TCGv addr = gen_get_zaddr(); 1873 1874 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1875 gen_data_load(ctx, Rd, addr); 1876 1877 gen_set_zaddr(addr); 1878 1879 tcg_temp_free_i32(addr); 1880 1881 return true; 1882 } 1883 1884 static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a) 1885 { 1886 TCGv Rd = cpu_r[a->rd]; 1887 TCGv addr = gen_get_zaddr(); 1888 1889 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 1890 gen_data_load(ctx, Rd, addr); 1891 1892 tcg_temp_free_i32(addr); 1893 1894 return true; 1895 } 1896 1897 /* 1898 * Stores one byte from a Register to the data space. For parts with SRAM, 1899 * the data space consists of the Register File, I/O memory and internal SRAM 1900 * (and external SRAM if applicable). For parts without SRAM, the data space 1901 * consists of the Register File only. The EEPROM has a separate address space. 1902 * A 16-bit address must be supplied. Memory access is limited to the current 1903 * data segment of 64KB. The STS instruction uses the RAMPD Register to access 1904 * memory above 64KB. To access another data segment in devices with more than 1905 * 64KB data space, the RAMPD in register in the I/O area has to be changed. 1906 * This instruction is not available in all devices. Refer to the device 1907 * specific instruction set summary. 1908 */ 1909 static bool trans_STS(DisasContext *ctx, arg_STS *a) 1910 { 1911 TCGv Rd = cpu_r[a->rd]; 1912 TCGv addr = tcg_temp_new_i32(); 1913 TCGv H = cpu_rampD; 1914 a->imm = next_word(ctx); 1915 1916 tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ 1917 tcg_gen_shli_tl(addr, addr, 16); 1918 tcg_gen_ori_tl(addr, addr, a->imm); 1919 gen_data_store(ctx, Rd, addr); 1920 1921 tcg_temp_free_i32(addr); 1922 1923 return true; 1924 } 1925 1926 /* 1927 * Stores one byte indirect from a register to data space. For parts with SRAM, 1928 * the data space consists of the Register File, I/O memory, and internal SRAM 1929 * (and external SRAM if applicable). For parts without SRAM, the data space 1930 * consists of the Register File only. The EEPROM has a separate address space. 1931 * 1932 * The data location is pointed to by the X (16 bits) Pointer Register in the 1933 * Register File. Memory access is limited to the current data segment of 64KB. 1934 * To access another data segment in devices with more than 64KB data space, the 1935 * RAMPX in register in the I/O area has to be changed. 1936 * 1937 * The X-pointer Register can either be left unchanged by the operation, or it 1938 * can be post-incremented or pre-decremented. These features are especially 1939 * suited for accessing arrays, tables, and Stack Pointer usage of the 1940 * X-pointer Register. Note that only the low byte of the X-pointer is updated 1941 * in devices with no more than 256 bytes data space. For such devices, the high 1942 * byte of the pointer is not used by this instruction and can be used for other 1943 * purposes. The RAMPX Register in the I/O area is updated in parts with more 1944 * than 64KB data space or more than 64KB Program memory, and the increment / 1945 * decrement is added to the entire 24-bit address on such devices. 1946 */ 1947 static bool trans_STX1(DisasContext *ctx, arg_STX1 *a) 1948 { 1949 TCGv Rd = cpu_r[a->rr]; 1950 TCGv addr = gen_get_xaddr(); 1951 1952 gen_data_store(ctx, Rd, addr); 1953 1954 tcg_temp_free_i32(addr); 1955 1956 return true; 1957 } 1958 1959 static bool trans_STX2(DisasContext *ctx, arg_STX2 *a) 1960 { 1961 TCGv Rd = cpu_r[a->rr]; 1962 TCGv addr = gen_get_xaddr(); 1963 1964 gen_data_store(ctx, Rd, addr); 1965 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1966 gen_set_xaddr(addr); 1967 1968 tcg_temp_free_i32(addr); 1969 1970 return true; 1971 } 1972 1973 static bool trans_STX3(DisasContext *ctx, arg_STX3 *a) 1974 { 1975 TCGv Rd = cpu_r[a->rr]; 1976 TCGv addr = gen_get_xaddr(); 1977 1978 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1979 gen_data_store(ctx, Rd, addr); 1980 gen_set_xaddr(addr); 1981 1982 tcg_temp_free_i32(addr); 1983 1984 return true; 1985 } 1986 1987 /* 1988 * Stores one byte indirect with or without displacement from a register to data 1989 * space. For parts with SRAM, the data space consists of the Register File, I/O 1990 * memory, and internal SRAM (and external SRAM if applicable). For parts 1991 * without SRAM, the data space consists of the Register File only. The EEPROM 1992 * has a separate address space. 1993 * 1994 * The data location is pointed to by the Y (16 bits) Pointer Register in the 1995 * Register File. Memory access is limited to the current data segment of 64KB. 1996 * To access another data segment in devices with more than 64KB data space, the 1997 * RAMPY in register in the I/O area has to be changed. 1998 * 1999 * The Y-pointer Register can either be left unchanged by the operation, or it 2000 * can be post-incremented or pre-decremented. These features are especially 2001 * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer 2002 * Register. Note that only the low byte of the Y-pointer is updated in devices 2003 * with no more than 256 bytes data space. For such devices, the high byte of 2004 * the pointer is not used by this instruction and can be used for other 2005 * purposes. The RAMPY Register in the I/O area is updated in parts with more 2006 * than 64KB data space or more than 64KB Program memory, and the increment / 2007 * decrement / displacement is added to the entire 24-bit address on such 2008 * devices. 2009 */ 2010 static bool trans_STY2(DisasContext *ctx, arg_STY2 *a) 2011 { 2012 TCGv Rd = cpu_r[a->rd]; 2013 TCGv addr = gen_get_yaddr(); 2014 2015 gen_data_store(ctx, Rd, addr); 2016 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2017 gen_set_yaddr(addr); 2018 2019 tcg_temp_free_i32(addr); 2020 2021 return true; 2022 } 2023 2024 static bool trans_STY3(DisasContext *ctx, arg_STY3 *a) 2025 { 2026 TCGv Rd = cpu_r[a->rd]; 2027 TCGv addr = gen_get_yaddr(); 2028 2029 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 2030 gen_data_store(ctx, Rd, addr); 2031 gen_set_yaddr(addr); 2032 2033 tcg_temp_free_i32(addr); 2034 2035 return true; 2036 } 2037 2038 static bool trans_STDY(DisasContext *ctx, arg_STDY *a) 2039 { 2040 TCGv Rd = cpu_r[a->rd]; 2041 TCGv addr = gen_get_yaddr(); 2042 2043 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 2044 gen_data_store(ctx, Rd, addr); 2045 2046 tcg_temp_free_i32(addr); 2047 2048 return true; 2049 } 2050 2051 /* 2052 * Stores one byte indirect with or without displacement from a register to data 2053 * space. For parts with SRAM, the data space consists of the Register File, I/O 2054 * memory, and internal SRAM (and external SRAM if applicable). For parts 2055 * without SRAM, the data space consists of the Register File only. The EEPROM 2056 * has a separate address space. 2057 * 2058 * The data location is pointed to by the Y (16 bits) Pointer Register in the 2059 * Register File. Memory access is limited to the current data segment of 64KB. 2060 * To access another data segment in devices with more than 64KB data space, the 2061 * RAMPY in register in the I/O area has to be changed. 2062 * 2063 * The Y-pointer Register can either be left unchanged by the operation, or it 2064 * can be post-incremented or pre-decremented. These features are especially 2065 * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer 2066 * Register. Note that only the low byte of the Y-pointer is updated in devices 2067 * with no more than 256 bytes data space. For such devices, the high byte of 2068 * the pointer is not used by this instruction and can be used for other 2069 * purposes. The RAMPY Register in the I/O area is updated in parts with more 2070 * than 64KB data space or more than 64KB Program memory, and the increment / 2071 * decrement / displacement is added to the entire 24-bit address on such 2072 * devices. 2073 */ 2074 static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a) 2075 { 2076 TCGv Rd = cpu_r[a->rd]; 2077 TCGv addr = gen_get_zaddr(); 2078 2079 gen_data_store(ctx, Rd, addr); 2080 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2081 2082 gen_set_zaddr(addr); 2083 2084 tcg_temp_free_i32(addr); 2085 2086 return true; 2087 } 2088 2089 static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a) 2090 { 2091 TCGv Rd = cpu_r[a->rd]; 2092 TCGv addr = gen_get_zaddr(); 2093 2094 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 2095 gen_data_store(ctx, Rd, addr); 2096 2097 gen_set_zaddr(addr); 2098 2099 tcg_temp_free_i32(addr); 2100 2101 return true; 2102 } 2103 2104 static bool trans_STDZ(DisasContext *ctx, arg_STDZ *a) 2105 { 2106 TCGv Rd = cpu_r[a->rd]; 2107 TCGv addr = gen_get_zaddr(); 2108 2109 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 2110 gen_data_store(ctx, Rd, addr); 2111 2112 tcg_temp_free_i32(addr); 2113 2114 return true; 2115 } 2116 2117 /* 2118 * Loads one byte pointed to by the Z-register into the destination 2119 * register Rd. This instruction features a 100% space effective constant 2120 * initialization or constant data fetch. The Program memory is organized in 2121 * 16-bit words while the Z-pointer is a byte address. Thus, the least 2122 * significant bit of the Z-pointer selects either low byte (ZLSB = 0) or high 2123 * byte (ZLSB = 1). This instruction can address the first 64KB (32K words) of 2124 * Program memory. The Zpointer Register can either be left unchanged by the 2125 * operation, or it can be incremented. The incrementation does not apply to 2126 * the RAMPZ Register. 2127 * 2128 * Devices with Self-Programming capability can use the LPM instruction to read 2129 * the Fuse and Lock bit values. 2130 */ 2131 static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a) 2132 { 2133 if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) { 2134 return true; 2135 } 2136 2137 TCGv Rd = cpu_r[0]; 2138 TCGv addr = tcg_temp_new_i32(); 2139 TCGv H = cpu_r[31]; 2140 TCGv L = cpu_r[30]; 2141 2142 tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 2143 tcg_gen_or_tl(addr, addr, L); 2144 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2145 2146 tcg_temp_free_i32(addr); 2147 2148 return true; 2149 } 2150 2151 static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a) 2152 { 2153 if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) { 2154 return true; 2155 } 2156 2157 TCGv Rd = cpu_r[a->rd]; 2158 TCGv addr = tcg_temp_new_i32(); 2159 TCGv H = cpu_r[31]; 2160 TCGv L = cpu_r[30]; 2161 2162 tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 2163 tcg_gen_or_tl(addr, addr, L); 2164 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2165 2166 tcg_temp_free_i32(addr); 2167 2168 return true; 2169 } 2170 2171 static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a) 2172 { 2173 if (!avr_have_feature(ctx, AVR_FEATURE_LPMX)) { 2174 return true; 2175 } 2176 2177 TCGv Rd = cpu_r[a->rd]; 2178 TCGv addr = tcg_temp_new_i32(); 2179 TCGv H = cpu_r[31]; 2180 TCGv L = cpu_r[30]; 2181 2182 tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 2183 tcg_gen_or_tl(addr, addr, L); 2184 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2185 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2186 tcg_gen_andi_tl(L, addr, 0xff); 2187 tcg_gen_shri_tl(addr, addr, 8); 2188 tcg_gen_andi_tl(H, addr, 0xff); 2189 2190 tcg_temp_free_i32(addr); 2191 2192 return true; 2193 } 2194 2195 /* 2196 * Loads one byte pointed to by the Z-register and the RAMPZ Register in 2197 * the I/O space, and places this byte in the destination register Rd. This 2198 * instruction features a 100% space effective constant initialization or 2199 * constant data fetch. The Program memory is organized in 16-bit words while 2200 * the Z-pointer is a byte address. Thus, the least significant bit of the 2201 * Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This 2202 * instruction can address the entire Program memory space. The Z-pointer 2203 * Register can either be left unchanged by the operation, or it can be 2204 * incremented. The incrementation applies to the entire 24-bit concatenation 2205 * of the RAMPZ and Z-pointer Registers. 2206 * 2207 * Devices with Self-Programming capability can use the ELPM instruction to 2208 * read the Fuse and Lock bit value. 2209 */ 2210 static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a) 2211 { 2212 if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) { 2213 return true; 2214 } 2215 2216 TCGv Rd = cpu_r[0]; 2217 TCGv addr = gen_get_zaddr(); 2218 2219 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2220 2221 tcg_temp_free_i32(addr); 2222 2223 return true; 2224 } 2225 2226 static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a) 2227 { 2228 if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) { 2229 return true; 2230 } 2231 2232 TCGv Rd = cpu_r[a->rd]; 2233 TCGv addr = gen_get_zaddr(); 2234 2235 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2236 2237 tcg_temp_free_i32(addr); 2238 2239 return true; 2240 } 2241 2242 static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a) 2243 { 2244 if (!avr_have_feature(ctx, AVR_FEATURE_ELPMX)) { 2245 return true; 2246 } 2247 2248 TCGv Rd = cpu_r[a->rd]; 2249 TCGv addr = gen_get_zaddr(); 2250 2251 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2252 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2253 gen_set_zaddr(addr); 2254 2255 tcg_temp_free_i32(addr); 2256 2257 return true; 2258 } 2259 2260 /* 2261 * SPM can be used to erase a page in the Program memory, to write a page 2262 * in the Program memory (that is already erased), and to set Boot Loader Lock 2263 * bits. In some devices, the Program memory can be written one word at a time, 2264 * in other devices an entire page can be programmed simultaneously after first 2265 * filling a temporary page buffer. In all cases, the Program memory must be 2266 * erased one page at a time. When erasing the Program memory, the RAMPZ and 2267 * Z-register are used as page address. When writing the Program memory, the 2268 * RAMPZ and Z-register are used as page or word address, and the R1:R0 2269 * register pair is used as data(1). When setting the Boot Loader Lock bits, 2270 * the R1:R0 register pair is used as data. Refer to the device documentation 2271 * for detailed description of SPM usage. This instruction can address the 2272 * entire Program memory. 2273 * 2274 * The SPM instruction is not available in all devices. Refer to the device 2275 * specific instruction set summary. 2276 * 2277 * Note: 1. R1 determines the instruction high byte, and R0 determines the 2278 * instruction low byte. 2279 */ 2280 static bool trans_SPM(DisasContext *ctx, arg_SPM *a) 2281 { 2282 /* TODO */ 2283 if (!avr_have_feature(ctx, AVR_FEATURE_SPM)) { 2284 return true; 2285 } 2286 2287 return true; 2288 } 2289 2290 static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) 2291 { 2292 /* TODO */ 2293 if (!avr_have_feature(ctx, AVR_FEATURE_SPMX)) { 2294 return true; 2295 } 2296 2297 return true; 2298 } 2299 2300 /* 2301 * Loads data from the I/O Space (Ports, Timers, Configuration Registers, 2302 * etc.) into register Rd in the Register File. 2303 */ 2304 static bool trans_IN(DisasContext *ctx, arg_IN *a) 2305 { 2306 TCGv Rd = cpu_r[a->rd]; 2307 TCGv port = tcg_const_i32(a->imm); 2308 2309 gen_helper_inb(Rd, cpu_env, port); 2310 2311 tcg_temp_free_i32(port); 2312 2313 return true; 2314 } 2315 2316 /* 2317 * Stores data from register Rr in the Register File to I/O Space (Ports, 2318 * Timers, Configuration Registers, etc.). 2319 */ 2320 static bool trans_OUT(DisasContext *ctx, arg_OUT *a) 2321 { 2322 TCGv Rd = cpu_r[a->rd]; 2323 TCGv port = tcg_const_i32(a->imm); 2324 2325 gen_helper_outb(cpu_env, port, Rd); 2326 2327 tcg_temp_free_i32(port); 2328 2329 return true; 2330 } 2331 2332 /* 2333 * This instruction stores the contents of register Rr on the STACK. The 2334 * Stack Pointer is post-decremented by 1 after the PUSH. This instruction is 2335 * not available in all devices. Refer to the device specific instruction set 2336 * summary. 2337 */ 2338 static bool trans_PUSH(DisasContext *ctx, arg_PUSH *a) 2339 { 2340 TCGv Rd = cpu_r[a->rd]; 2341 2342 gen_data_store(ctx, Rd, cpu_sp); 2343 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 2344 2345 return true; 2346 } 2347 2348 /* 2349 * This instruction loads register Rd with a byte from the STACK. The Stack 2350 * Pointer is pre-incremented by 1 before the POP. This instruction is not 2351 * available in all devices. Refer to the device specific instruction set 2352 * summary. 2353 */ 2354 static bool trans_POP(DisasContext *ctx, arg_POP *a) 2355 { 2356 /* 2357 * Using a temp to work around some strange behaviour: 2358 * tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 2359 * gen_data_load(ctx, Rd, cpu_sp); 2360 * seems to cause the add to happen twice. 2361 * This doesn't happen if either the add or the load is removed. 2362 */ 2363 TCGv t1 = tcg_temp_new_i32(); 2364 TCGv Rd = cpu_r[a->rd]; 2365 2366 tcg_gen_addi_tl(t1, cpu_sp, 1); 2367 gen_data_load(ctx, Rd, t1); 2368 tcg_gen_mov_tl(cpu_sp, t1); 2369 2370 return true; 2371 } 2372 2373 /* 2374 * Exchanges one byte indirect between register and data space. The data 2375 * location is pointed to by the Z (16 bits) Pointer Register in the Register 2376 * File. Memory access is limited to the current data segment of 64KB. To 2377 * access another data segment in devices with more than 64KB data space, the 2378 * RAMPZ in register in the I/O area has to be changed. 2379 * 2380 * The Z-pointer Register is left unchanged by the operation. This instruction 2381 * is especially suited for writing/reading status bits stored in SRAM. 2382 */ 2383 static bool trans_XCH(DisasContext *ctx, arg_XCH *a) 2384 { 2385 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2386 return true; 2387 } 2388 2389 TCGv Rd = cpu_r[a->rd]; 2390 TCGv t0 = tcg_temp_new_i32(); 2391 TCGv addr = gen_get_zaddr(); 2392 2393 gen_data_load(ctx, t0, addr); 2394 gen_data_store(ctx, Rd, addr); 2395 tcg_gen_mov_tl(Rd, t0); 2396 2397 tcg_temp_free_i32(t0); 2398 tcg_temp_free_i32(addr); 2399 2400 return true; 2401 } 2402 2403 /* 2404 * Load one byte indirect from data space to register and set bits in data 2405 * space specified by the register. The instruction can only be used towards 2406 * internal SRAM. The data location is pointed to by the Z (16 bits) Pointer 2407 * Register in the Register File. Memory access is limited to the current data 2408 * segment of 64KB. To access another data segment in devices with more than 2409 * 64KB data space, the RAMPZ in register in the I/O area has to be changed. 2410 * 2411 * The Z-pointer Register is left unchanged by the operation. This instruction 2412 * is especially suited for setting status bits stored in SRAM. 2413 */ 2414 static bool trans_LAS(DisasContext *ctx, arg_LAS *a) 2415 { 2416 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2417 return true; 2418 } 2419 2420 TCGv Rr = cpu_r[a->rd]; 2421 TCGv addr = gen_get_zaddr(); 2422 TCGv t0 = tcg_temp_new_i32(); 2423 TCGv t1 = tcg_temp_new_i32(); 2424 2425 gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 2426 tcg_gen_or_tl(t1, t0, Rr); 2427 tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */ 2428 gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 2429 2430 tcg_temp_free_i32(t1); 2431 tcg_temp_free_i32(t0); 2432 tcg_temp_free_i32(addr); 2433 2434 return true; 2435 } 2436 2437 /* 2438 * Load one byte indirect from data space to register and stores and clear 2439 * the bits in data space specified by the register. The instruction can 2440 * only be used towards internal SRAM. The data location is pointed to by 2441 * the Z (16 bits) Pointer Register in the Register File. Memory access is 2442 * limited to the current data segment of 64KB. To access another data 2443 * segment in devices with more than 64KB data space, the RAMPZ in register 2444 * in the I/O area has to be changed. 2445 * 2446 * The Z-pointer Register is left unchanged by the operation. This instruction 2447 * is especially suited for clearing status bits stored in SRAM. 2448 */ 2449 static bool trans_LAC(DisasContext *ctx, arg_LAC *a) 2450 { 2451 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2452 return true; 2453 } 2454 2455 TCGv Rr = cpu_r[a->rd]; 2456 TCGv addr = gen_get_zaddr(); 2457 TCGv t0 = tcg_temp_new_i32(); 2458 TCGv t1 = tcg_temp_new_i32(); 2459 2460 gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 2461 tcg_gen_andc_tl(t1, t0, Rr); /* t1 = t0 & (0xff - Rr) = t0 & ~Rr */ 2462 tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */ 2463 gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 2464 2465 tcg_temp_free_i32(t1); 2466 tcg_temp_free_i32(t0); 2467 tcg_temp_free_i32(addr); 2468 2469 return true; 2470 } 2471 2472 2473 /* 2474 * Load one byte indirect from data space to register and toggles bits in 2475 * the data space specified by the register. The instruction can only be used 2476 * towards SRAM. The data location is pointed to by the Z (16 bits) Pointer 2477 * Register in the Register File. Memory access is limited to the current data 2478 * segment of 64KB. To access another data segment in devices with more than 2479 * 64KB data space, the RAMPZ in register in the I/O area has to be changed. 2480 * 2481 * The Z-pointer Register is left unchanged by the operation. This instruction 2482 * is especially suited for changing status bits stored in SRAM. 2483 */ 2484 static bool trans_LAT(DisasContext *ctx, arg_LAT *a) 2485 { 2486 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2487 return true; 2488 } 2489 2490 TCGv Rd = cpu_r[a->rd]; 2491 TCGv addr = gen_get_zaddr(); 2492 TCGv t0 = tcg_temp_new_i32(); 2493 TCGv t1 = tcg_temp_new_i32(); 2494 2495 gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 2496 tcg_gen_xor_tl(t1, t0, Rd); 2497 tcg_gen_mov_tl(Rd, t0); /* Rd = t0 */ 2498 gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 2499 2500 tcg_temp_free_i32(t1); 2501 tcg_temp_free_i32(t0); 2502 tcg_temp_free_i32(addr); 2503 2504 return true; 2505 } 2506 2507 /* 2508 * Bit and Bit-test Instructions 2509 */ 2510 static void gen_rshift_ZNVSf(TCGv R) 2511 { 2512 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 2513 tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 2514 tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf); 2515 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 2516 } 2517 2518 /* 2519 * Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is 2520 * loaded into the C Flag of the SREG. This operation effectively divides an 2521 * unsigned value by two. The C Flag can be used to round the result. 2522 */ 2523 static bool trans_LSR(DisasContext *ctx, arg_LSR *a) 2524 { 2525 TCGv Rd = cpu_r[a->rd]; 2526 2527 tcg_gen_andi_tl(cpu_Cf, Rd, 1); 2528 tcg_gen_shri_tl(Rd, Rd, 1); 2529 2530 /* update status register */ 2531 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, Rd, 0); /* Zf = Rd == 0 */ 2532 tcg_gen_movi_tl(cpu_Nf, 0); 2533 tcg_gen_mov_tl(cpu_Vf, cpu_Cf); 2534 tcg_gen_mov_tl(cpu_Sf, cpu_Vf); 2535 2536 return true; 2537 } 2538 2539 /* 2540 * Shifts all bits in Rd one place to the right. The C Flag is shifted into 2541 * bit 7 of Rd. Bit 0 is shifted into the C Flag. This operation, combined 2542 * with ASR, effectively divides multi-byte signed values by two. Combined with 2543 * LSR it effectively divides multi-byte unsigned values by two. The Carry Flag 2544 * can be used to round the result. 2545 */ 2546 static bool trans_ROR(DisasContext *ctx, arg_ROR *a) 2547 { 2548 TCGv Rd = cpu_r[a->rd]; 2549 TCGv t0 = tcg_temp_new_i32(); 2550 2551 tcg_gen_shli_tl(t0, cpu_Cf, 7); 2552 2553 /* update status register */ 2554 tcg_gen_andi_tl(cpu_Cf, Rd, 1); 2555 2556 /* update output register */ 2557 tcg_gen_shri_tl(Rd, Rd, 1); 2558 tcg_gen_or_tl(Rd, Rd, t0); 2559 2560 /* update status register */ 2561 gen_rshift_ZNVSf(Rd); 2562 2563 tcg_temp_free_i32(t0); 2564 2565 return true; 2566 } 2567 2568 /* 2569 * Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 2570 * is loaded into the C Flag of the SREG. This operation effectively divides a 2571 * signed value by two without changing its sign. The Carry Flag can be used to 2572 * round the result. 2573 */ 2574 static bool trans_ASR(DisasContext *ctx, arg_ASR *a) 2575 { 2576 TCGv Rd = cpu_r[a->rd]; 2577 TCGv t0 = tcg_temp_new_i32(); 2578 2579 /* update status register */ 2580 tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf = Rd(0) */ 2581 2582 /* update output register */ 2583 tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd = (Rd & 0x80) | (Rd >> 1) */ 2584 tcg_gen_shri_tl(Rd, Rd, 1); 2585 tcg_gen_or_tl(Rd, Rd, t0); 2586 2587 /* update status register */ 2588 gen_rshift_ZNVSf(Rd); 2589 2590 tcg_temp_free_i32(t0); 2591 2592 return true; 2593 } 2594 2595 /* 2596 * Swaps high and low nibbles in a register. 2597 */ 2598 static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a) 2599 { 2600 TCGv Rd = cpu_r[a->rd]; 2601 TCGv t0 = tcg_temp_new_i32(); 2602 TCGv t1 = tcg_temp_new_i32(); 2603 2604 tcg_gen_andi_tl(t0, Rd, 0x0f); 2605 tcg_gen_shli_tl(t0, t0, 4); 2606 tcg_gen_andi_tl(t1, Rd, 0xf0); 2607 tcg_gen_shri_tl(t1, t1, 4); 2608 tcg_gen_or_tl(Rd, t0, t1); 2609 2610 tcg_temp_free_i32(t1); 2611 tcg_temp_free_i32(t0); 2612 2613 return true; 2614 } 2615 2616 /* 2617 * Sets a specified bit in an I/O Register. This instruction operates on 2618 * the lower 32 I/O Registers -- addresses 0-31. 2619 */ 2620 static bool trans_SBI(DisasContext *ctx, arg_SBI *a) 2621 { 2622 TCGv data = tcg_temp_new_i32(); 2623 TCGv port = tcg_const_i32(a->reg); 2624 2625 gen_helper_inb(data, cpu_env, port); 2626 tcg_gen_ori_tl(data, data, 1 << a->bit); 2627 gen_helper_outb(cpu_env, port, data); 2628 2629 tcg_temp_free_i32(port); 2630 tcg_temp_free_i32(data); 2631 2632 return true; 2633 } 2634 2635 /* 2636 * Clears a specified bit in an I/O Register. This instruction operates on 2637 * the lower 32 I/O Registers -- addresses 0-31. 2638 */ 2639 static bool trans_CBI(DisasContext *ctx, arg_CBI *a) 2640 { 2641 TCGv data = tcg_temp_new_i32(); 2642 TCGv port = tcg_const_i32(a->reg); 2643 2644 gen_helper_inb(data, cpu_env, port); 2645 tcg_gen_andi_tl(data, data, ~(1 << a->bit)); 2646 gen_helper_outb(cpu_env, port, data); 2647 2648 tcg_temp_free_i32(data); 2649 tcg_temp_free_i32(port); 2650 2651 return true; 2652 } 2653 2654 /* 2655 * Stores bit b from Rd to the T Flag in SREG (Status Register). 2656 */ 2657 static bool trans_BST(DisasContext *ctx, arg_BST *a) 2658 { 2659 TCGv Rd = cpu_r[a->rd]; 2660 2661 tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit); 2662 tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit); 2663 2664 return true; 2665 } 2666 2667 /* 2668 * Copies the T Flag in the SREG (Status Register) to bit b in register Rd. 2669 */ 2670 static bool trans_BLD(DisasContext *ctx, arg_BLD *a) 2671 { 2672 TCGv Rd = cpu_r[a->rd]; 2673 TCGv t1 = tcg_temp_new_i32(); 2674 2675 tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear bit */ 2676 tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */ 2677 tcg_gen_or_tl(Rd, Rd, t1); 2678 2679 tcg_temp_free_i32(t1); 2680 2681 return true; 2682 } 2683 2684 /* 2685 * Sets a single Flag or bit in SREG. 2686 */ 2687 static bool trans_BSET(DisasContext *ctx, arg_BSET *a) 2688 { 2689 switch (a->bit) { 2690 case 0x00: 2691 tcg_gen_movi_tl(cpu_Cf, 0x01); 2692 break; 2693 case 0x01: 2694 tcg_gen_movi_tl(cpu_Zf, 0x01); 2695 break; 2696 case 0x02: 2697 tcg_gen_movi_tl(cpu_Nf, 0x01); 2698 break; 2699 case 0x03: 2700 tcg_gen_movi_tl(cpu_Vf, 0x01); 2701 break; 2702 case 0x04: 2703 tcg_gen_movi_tl(cpu_Sf, 0x01); 2704 break; 2705 case 0x05: 2706 tcg_gen_movi_tl(cpu_Hf, 0x01); 2707 break; 2708 case 0x06: 2709 tcg_gen_movi_tl(cpu_Tf, 0x01); 2710 break; 2711 case 0x07: 2712 tcg_gen_movi_tl(cpu_If, 0x01); 2713 break; 2714 } 2715 2716 return true; 2717 } 2718 2719 /* 2720 * Clears a single Flag in SREG. 2721 */ 2722 static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a) 2723 { 2724 switch (a->bit) { 2725 case 0x00: 2726 tcg_gen_movi_tl(cpu_Cf, 0x00); 2727 break; 2728 case 0x01: 2729 tcg_gen_movi_tl(cpu_Zf, 0x00); 2730 break; 2731 case 0x02: 2732 tcg_gen_movi_tl(cpu_Nf, 0x00); 2733 break; 2734 case 0x03: 2735 tcg_gen_movi_tl(cpu_Vf, 0x00); 2736 break; 2737 case 0x04: 2738 tcg_gen_movi_tl(cpu_Sf, 0x00); 2739 break; 2740 case 0x05: 2741 tcg_gen_movi_tl(cpu_Hf, 0x00); 2742 break; 2743 case 0x06: 2744 tcg_gen_movi_tl(cpu_Tf, 0x00); 2745 break; 2746 case 0x07: 2747 tcg_gen_movi_tl(cpu_If, 0x00); 2748 break; 2749 } 2750 2751 return true; 2752 } 2753 2754 /* 2755 * MCU Control Instructions 2756 */ 2757 2758 /* 2759 * The BREAK instruction is used by the On-chip Debug system, and is 2760 * normally not used in the application software. When the BREAK instruction is 2761 * executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip 2762 * Debugger access to internal resources. If any Lock bits are set, or either 2763 * the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK 2764 * instruction as a NOP and will not enter the Stopped mode. This instruction 2765 * is not available in all devices. Refer to the device specific instruction 2766 * set summary. 2767 */ 2768 static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a) 2769 { 2770 if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) { 2771 return true; 2772 } 2773 2774 #ifdef BREAKPOINT_ON_BREAK 2775 tcg_gen_movi_tl(cpu_pc, ctx->npc - 1); 2776 gen_helper_debug(cpu_env); 2777 ctx->base.is_jmp = DISAS_EXIT; 2778 #else 2779 /* NOP */ 2780 #endif 2781 2782 return true; 2783 } 2784 2785 /* 2786 * This instruction performs a single cycle No Operation. 2787 */ 2788 static bool trans_NOP(DisasContext *ctx, arg_NOP *a) 2789 { 2790 2791 /* NOP */ 2792 2793 return true; 2794 } 2795 2796 /* 2797 * This instruction sets the circuit in sleep mode defined by the MCU 2798 * Control Register. 2799 */ 2800 static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a) 2801 { 2802 gen_helper_sleep(cpu_env); 2803 ctx->base.is_jmp = DISAS_NORETURN; 2804 return true; 2805 } 2806 2807 /* 2808 * This instruction resets the Watchdog Timer. This instruction must be 2809 * executed within a limited time given by the WD prescaler. See the Watchdog 2810 * Timer hardware specification. 2811 */ 2812 static bool trans_WDR(DisasContext *ctx, arg_WDR *a) 2813 { 2814 gen_helper_wdr(cpu_env); 2815 2816 return true; 2817 } 2818 2819 /* 2820 * Core translation mechanism functions: 2821 * 2822 * - translate() 2823 * - canonicalize_skip() 2824 * - gen_intermediate_code() 2825 * - restore_state_to_opc() 2826 * 2827 */ 2828 static void translate(DisasContext *ctx) 2829 { 2830 uint32_t opcode = next_word(ctx); 2831 2832 if (!decode_insn(ctx, opcode)) { 2833 gen_helper_unsupported(cpu_env); 2834 ctx->base.is_jmp = DISAS_NORETURN; 2835 } 2836 } 2837 2838 /* Standardize the cpu_skip condition to NE. */ 2839 static bool canonicalize_skip(DisasContext *ctx) 2840 { 2841 switch (ctx->skip_cond) { 2842 case TCG_COND_NEVER: 2843 /* Normal case: cpu_skip is known to be false. */ 2844 return false; 2845 2846 case TCG_COND_ALWAYS: 2847 /* 2848 * Breakpoint case: cpu_skip is known to be true, via TB_FLAGS_SKIP. 2849 * The breakpoint is on the instruction being skipped, at the start 2850 * of the TranslationBlock. No need to update. 2851 */ 2852 return false; 2853 2854 case TCG_COND_NE: 2855 if (ctx->skip_var1 == NULL) { 2856 tcg_gen_mov_tl(cpu_skip, ctx->skip_var0); 2857 } else { 2858 tcg_gen_xor_tl(cpu_skip, ctx->skip_var0, ctx->skip_var1); 2859 ctx->skip_var1 = NULL; 2860 } 2861 break; 2862 2863 default: 2864 /* Convert to a NE condition vs 0. */ 2865 if (ctx->skip_var1 == NULL) { 2866 tcg_gen_setcondi_tl(ctx->skip_cond, cpu_skip, ctx->skip_var0, 0); 2867 } else { 2868 tcg_gen_setcond_tl(ctx->skip_cond, cpu_skip, 2869 ctx->skip_var0, ctx->skip_var1); 2870 ctx->skip_var1 = NULL; 2871 } 2872 ctx->skip_cond = TCG_COND_NE; 2873 break; 2874 } 2875 ctx->skip_var0 = cpu_skip; 2876 return true; 2877 } 2878 2879 static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 2880 { 2881 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2882 CPUAVRState *env = cs->env_ptr; 2883 uint32_t tb_flags = ctx->base.tb->flags; 2884 2885 ctx->cs = cs; 2886 ctx->env = env; 2887 ctx->npc = ctx->base.pc_first / 2; 2888 2889 ctx->skip_cond = TCG_COND_NEVER; 2890 if (tb_flags & TB_FLAGS_SKIP) { 2891 ctx->skip_cond = TCG_COND_ALWAYS; 2892 ctx->skip_var0 = cpu_skip; 2893 } 2894 2895 if (tb_flags & TB_FLAGS_FULL_ACCESS) { 2896 /* 2897 * This flag is set by ST/LD instruction we will regenerate it ONLY 2898 * with mem/cpu memory access instead of mem access 2899 */ 2900 ctx->base.max_insns = 1; 2901 } 2902 } 2903 2904 static void avr_tr_tb_start(DisasContextBase *db, CPUState *cs) 2905 { 2906 } 2907 2908 static void avr_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 2909 { 2910 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2911 2912 tcg_gen_insn_start(ctx->npc); 2913 } 2914 2915 static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 2916 { 2917 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2918 TCGLabel *skip_label = NULL; 2919 2920 /* Conditionally skip the next instruction, if indicated. */ 2921 if (ctx->skip_cond != TCG_COND_NEVER) { 2922 skip_label = gen_new_label(); 2923 if (ctx->skip_var0 == cpu_skip) { 2924 /* 2925 * Copy cpu_skip so that we may zero it before the branch. 2926 * This ensures that cpu_skip is non-zero after the label 2927 * if and only if the skipped insn itself sets a skip. 2928 */ 2929 ctx->skip_var0 = tcg_temp_new(); 2930 tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); 2931 tcg_gen_movi_tl(cpu_skip, 0); 2932 } 2933 if (ctx->skip_var1 == NULL) { 2934 tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0, 0, skip_label); 2935 } else { 2936 tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0, 2937 ctx->skip_var1, skip_label); 2938 ctx->skip_var1 = NULL; 2939 } 2940 ctx->skip_cond = TCG_COND_NEVER; 2941 ctx->skip_var0 = NULL; 2942 } 2943 2944 translate(ctx); 2945 2946 ctx->base.pc_next = ctx->npc * 2; 2947 2948 if (skip_label) { 2949 canonicalize_skip(ctx); 2950 gen_set_label(skip_label); 2951 2952 switch (ctx->base.is_jmp) { 2953 case DISAS_NORETURN: 2954 ctx->base.is_jmp = DISAS_CHAIN; 2955 break; 2956 case DISAS_NEXT: 2957 if (ctx->base.tb->flags & TB_FLAGS_SKIP) { 2958 ctx->base.is_jmp = DISAS_TOO_MANY; 2959 } 2960 break; 2961 default: 2962 break; 2963 } 2964 } 2965 2966 if (ctx->base.is_jmp == DISAS_NEXT) { 2967 target_ulong page_first = ctx->base.pc_first & TARGET_PAGE_MASK; 2968 2969 if ((ctx->base.pc_next - page_first) >= TARGET_PAGE_SIZE - 4) { 2970 ctx->base.is_jmp = DISAS_TOO_MANY; 2971 } 2972 } 2973 } 2974 2975 static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 2976 { 2977 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2978 bool nonconst_skip = canonicalize_skip(ctx); 2979 /* 2980 * Because we disable interrupts while env->skip is set, 2981 * we must return to the main loop to re-evaluate afterward. 2982 */ 2983 bool force_exit = ctx->base.tb->flags & TB_FLAGS_SKIP; 2984 2985 switch (ctx->base.is_jmp) { 2986 case DISAS_NORETURN: 2987 assert(!nonconst_skip); 2988 break; 2989 case DISAS_NEXT: 2990 case DISAS_TOO_MANY: 2991 case DISAS_CHAIN: 2992 if (!nonconst_skip && !force_exit) { 2993 /* Note gen_goto_tb checks singlestep. */ 2994 gen_goto_tb(ctx, 1, ctx->npc); 2995 break; 2996 } 2997 tcg_gen_movi_tl(cpu_pc, ctx->npc); 2998 /* fall through */ 2999 case DISAS_LOOKUP: 3000 if (!force_exit) { 3001 tcg_gen_lookup_and_goto_ptr(); 3002 break; 3003 } 3004 /* fall through */ 3005 case DISAS_EXIT: 3006 tcg_gen_exit_tb(NULL, 0); 3007 break; 3008 default: 3009 g_assert_not_reached(); 3010 } 3011 } 3012 3013 static void avr_tr_disas_log(const DisasContextBase *dcbase, 3014 CPUState *cs, FILE *logfile) 3015 { 3016 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 3017 target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 3018 } 3019 3020 static const TranslatorOps avr_tr_ops = { 3021 .init_disas_context = avr_tr_init_disas_context, 3022 .tb_start = avr_tr_tb_start, 3023 .insn_start = avr_tr_insn_start, 3024 .translate_insn = avr_tr_translate_insn, 3025 .tb_stop = avr_tr_tb_stop, 3026 .disas_log = avr_tr_disas_log, 3027 }; 3028 3029 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 3030 target_ulong pc, void *host_pc) 3031 { 3032 DisasContext dc = { }; 3033 translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base); 3034 } 3035