1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2019-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "tcg/tcg.h" 24 #include "cpu.h" 25 #include "exec/exec-all.h" 26 #include "tcg/tcg-op.h" 27 #include "exec/cpu_ldst.h" 28 #include "exec/helper-proto.h" 29 #include "exec/helper-gen.h" 30 #include "exec/log.h" 31 #include "exec/translator.h" 32 #include "exec/gen-icount.h" 33 34 /* 35 * Define if you want a BREAK instruction translated to a breakpoint 36 * Active debugging connection is assumed 37 * This is for 38 * https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests 39 * tests 40 */ 41 #undef BREAKPOINT_ON_BREAK 42 43 static TCGv cpu_pc; 44 45 static TCGv cpu_Cf; 46 static TCGv cpu_Zf; 47 static TCGv cpu_Nf; 48 static TCGv cpu_Vf; 49 static TCGv cpu_Sf; 50 static TCGv cpu_Hf; 51 static TCGv cpu_Tf; 52 static TCGv cpu_If; 53 54 static TCGv cpu_rampD; 55 static TCGv cpu_rampX; 56 static TCGv cpu_rampY; 57 static TCGv cpu_rampZ; 58 59 static TCGv cpu_r[NUMBER_OF_CPU_REGISTERS]; 60 static TCGv cpu_eind; 61 static TCGv cpu_sp; 62 63 static TCGv cpu_skip; 64 65 static const char reg_names[NUMBER_OF_CPU_REGISTERS][8] = { 66 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 67 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 68 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 69 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 70 }; 71 #define REG(x) (cpu_r[x]) 72 73 #define DISAS_EXIT DISAS_TARGET_0 /* We want return to the cpu main loop. */ 74 #define DISAS_LOOKUP DISAS_TARGET_1 /* We have a variable condition exit. */ 75 #define DISAS_CHAIN DISAS_TARGET_2 /* We have a single condition exit. */ 76 77 typedef struct DisasContext DisasContext; 78 79 /* This is the state at translation time. */ 80 struct DisasContext { 81 DisasContextBase base; 82 83 CPUAVRState *env; 84 CPUState *cs; 85 86 target_long npc; 87 uint32_t opcode; 88 89 /* Routine used to access memory */ 90 int memidx; 91 92 /* 93 * some AVR instructions can make the following instruction to be skipped 94 * Let's name those instructions 95 * A - instruction that can skip the next one 96 * B - instruction that can be skipped. this depends on execution of A 97 * there are two scenarios 98 * 1. A and B belong to the same translation block 99 * 2. A is the last instruction in the translation block and B is the last 100 * 101 * following variables are used to simplify the skipping logic, they are 102 * used in the following manner (sketch) 103 * 104 * TCGLabel *skip_label = NULL; 105 * if (ctx->skip_cond != TCG_COND_NEVER) { 106 * skip_label = gen_new_label(); 107 * tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label); 108 * } 109 * 110 * if (free_skip_var0) { 111 * tcg_temp_free(skip_var0); 112 * free_skip_var0 = false; 113 * } 114 * 115 * translate(ctx); 116 * 117 * if (skip_label) { 118 * gen_set_label(skip_label); 119 * } 120 */ 121 TCGv skip_var0; 122 TCGv skip_var1; 123 TCGCond skip_cond; 124 bool free_skip_var0; 125 }; 126 127 void avr_cpu_tcg_init(void) 128 { 129 int i; 130 131 #define AVR_REG_OFFS(x) offsetof(CPUAVRState, x) 132 cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc"); 133 cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf"); 134 cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf"); 135 cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf"); 136 cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf"); 137 cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf"); 138 cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf"); 139 cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf"); 140 cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If"); 141 cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD"); 142 cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX"); 143 cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY"); 144 cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ"); 145 cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind"); 146 cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp"); 147 cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip"); 148 149 for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) { 150 cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]), 151 reg_names[i]); 152 } 153 #undef AVR_REG_OFFS 154 } 155 156 static int to_regs_16_31_by_one(DisasContext *ctx, int indx) 157 { 158 return 16 + (indx % 16); 159 } 160 161 static int to_regs_16_23_by_one(DisasContext *ctx, int indx) 162 { 163 return 16 + (indx % 8); 164 } 165 166 static int to_regs_24_30_by_two(DisasContext *ctx, int indx) 167 { 168 return 24 + (indx % 4) * 2; 169 } 170 171 static int to_regs_00_30_by_two(DisasContext *ctx, int indx) 172 { 173 return (indx % 16) * 2; 174 } 175 176 static uint16_t next_word(DisasContext *ctx) 177 { 178 return cpu_lduw_code(ctx->env, ctx->npc++ * 2); 179 } 180 181 static int append_16(DisasContext *ctx, int x) 182 { 183 return x << 16 | next_word(ctx); 184 } 185 186 static bool avr_have_feature(DisasContext *ctx, int feature) 187 { 188 if (!avr_feature(ctx->env, feature)) { 189 gen_helper_unsupported(cpu_env); 190 ctx->base.is_jmp = DISAS_NORETURN; 191 return false; 192 } 193 return true; 194 } 195 196 static bool decode_insn(DisasContext *ctx, uint16_t insn); 197 #include "decode-insn.c.inc" 198 199 /* 200 * Arithmetic Instructions 201 */ 202 203 /* 204 * Utility functions for updating status registers: 205 * 206 * - gen_add_CHf() 207 * - gen_add_Vf() 208 * - gen_sub_CHf() 209 * - gen_sub_Vf() 210 * - gen_NSf() 211 * - gen_ZNSf() 212 * 213 */ 214 215 static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr) 216 { 217 TCGv t1 = tcg_temp_new_i32(); 218 TCGv t2 = tcg_temp_new_i32(); 219 TCGv t3 = tcg_temp_new_i32(); 220 221 tcg_gen_and_tl(t1, Rd, Rr); /* t1 = Rd & Rr */ 222 tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd & ~R */ 223 tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr & ~R */ 224 tcg_gen_or_tl(t1, t1, t2); /* t1 = t1 | t2 | t3 */ 225 tcg_gen_or_tl(t1, t1, t3); 226 227 tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */ 228 tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */ 229 tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1); 230 231 tcg_temp_free_i32(t3); 232 tcg_temp_free_i32(t2); 233 tcg_temp_free_i32(t1); 234 } 235 236 static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr) 237 { 238 TCGv t1 = tcg_temp_new_i32(); 239 TCGv t2 = tcg_temp_new_i32(); 240 241 /* t1 = Rd & Rr & ~R | ~Rd & ~Rr & R */ 242 /* = (Rd ^ R) & ~(Rd ^ Rr) */ 243 tcg_gen_xor_tl(t1, Rd, R); 244 tcg_gen_xor_tl(t2, Rd, Rr); 245 tcg_gen_andc_tl(t1, t1, t2); 246 247 tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */ 248 249 tcg_temp_free_i32(t2); 250 tcg_temp_free_i32(t1); 251 } 252 253 static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr) 254 { 255 TCGv t1 = tcg_temp_new_i32(); 256 TCGv t2 = tcg_temp_new_i32(); 257 TCGv t3 = tcg_temp_new_i32(); 258 259 tcg_gen_not_tl(t1, Rd); /* t1 = ~Rd */ 260 tcg_gen_and_tl(t2, t1, Rr); /* t2 = ~Rd & Rr */ 261 tcg_gen_or_tl(t3, t1, Rr); /* t3 = (~Rd | Rr) & R */ 262 tcg_gen_and_tl(t3, t3, R); 263 tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */ 264 265 tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */ 266 tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */ 267 tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1); 268 269 tcg_temp_free_i32(t3); 270 tcg_temp_free_i32(t2); 271 tcg_temp_free_i32(t1); 272 } 273 274 static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr) 275 { 276 TCGv t1 = tcg_temp_new_i32(); 277 TCGv t2 = tcg_temp_new_i32(); 278 279 /* t1 = Rd & ~Rr & ~R | ~Rd & Rr & R */ 280 /* = (Rd ^ R) & (Rd ^ R) */ 281 tcg_gen_xor_tl(t1, Rd, R); 282 tcg_gen_xor_tl(t2, Rd, Rr); 283 tcg_gen_and_tl(t1, t1, t2); 284 285 tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */ 286 287 tcg_temp_free_i32(t2); 288 tcg_temp_free_i32(t1); 289 } 290 291 static void gen_NSf(TCGv R) 292 { 293 tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 294 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 295 } 296 297 static void gen_ZNSf(TCGv R) 298 { 299 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 300 301 /* update status register */ 302 tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 303 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 304 } 305 306 /* 307 * Adds two registers without the C Flag and places the result in the 308 * destination register Rd. 309 */ 310 static bool trans_ADD(DisasContext *ctx, arg_ADD *a) 311 { 312 TCGv Rd = cpu_r[a->rd]; 313 TCGv Rr = cpu_r[a->rr]; 314 TCGv R = tcg_temp_new_i32(); 315 316 tcg_gen_add_tl(R, Rd, Rr); /* Rd = Rd + Rr */ 317 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 318 319 /* update status register */ 320 gen_add_CHf(R, Rd, Rr); 321 gen_add_Vf(R, Rd, Rr); 322 gen_ZNSf(R); 323 324 /* update output registers */ 325 tcg_gen_mov_tl(Rd, R); 326 327 tcg_temp_free_i32(R); 328 329 return true; 330 } 331 332 /* 333 * Adds two registers and the contents of the C Flag and places the result in 334 * the destination register Rd. 335 */ 336 static bool trans_ADC(DisasContext *ctx, arg_ADC *a) 337 { 338 TCGv Rd = cpu_r[a->rd]; 339 TCGv Rr = cpu_r[a->rr]; 340 TCGv R = tcg_temp_new_i32(); 341 342 tcg_gen_add_tl(R, Rd, Rr); /* R = Rd + Rr + Cf */ 343 tcg_gen_add_tl(R, R, cpu_Cf); 344 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 345 346 /* update status register */ 347 gen_add_CHf(R, Rd, Rr); 348 gen_add_Vf(R, Rd, Rr); 349 gen_ZNSf(R); 350 351 /* update output registers */ 352 tcg_gen_mov_tl(Rd, R); 353 354 tcg_temp_free_i32(R); 355 356 return true; 357 } 358 359 /* 360 * Adds an immediate value (0 - 63) to a register pair and places the result 361 * in the register pair. This instruction operates on the upper four register 362 * pairs, and is well suited for operations on the pointer registers. This 363 * instruction is not available in all devices. Refer to the device specific 364 * instruction set summary. 365 */ 366 static bool trans_ADIW(DisasContext *ctx, arg_ADIW *a) 367 { 368 if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) { 369 return true; 370 } 371 372 TCGv RdL = cpu_r[a->rd]; 373 TCGv RdH = cpu_r[a->rd + 1]; 374 int Imm = (a->imm); 375 TCGv R = tcg_temp_new_i32(); 376 TCGv Rd = tcg_temp_new_i32(); 377 378 tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */ 379 tcg_gen_addi_tl(R, Rd, Imm); /* R = Rd + Imm */ 380 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 381 382 /* update status register */ 383 tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */ 384 tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15); 385 tcg_gen_andc_tl(cpu_Vf, R, Rd); /* Vf = R & ~Rd */ 386 tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15); 387 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 388 tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */ 389 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf);/* Sf = Nf ^ Vf */ 390 391 /* update output registers */ 392 tcg_gen_andi_tl(RdL, R, 0xff); 393 tcg_gen_shri_tl(RdH, R, 8); 394 395 tcg_temp_free_i32(Rd); 396 tcg_temp_free_i32(R); 397 398 return true; 399 } 400 401 /* 402 * Subtracts two registers and places the result in the destination 403 * register Rd. 404 */ 405 static bool trans_SUB(DisasContext *ctx, arg_SUB *a) 406 { 407 TCGv Rd = cpu_r[a->rd]; 408 TCGv Rr = cpu_r[a->rr]; 409 TCGv R = tcg_temp_new_i32(); 410 411 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 412 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 413 414 /* update status register */ 415 tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */ 416 gen_sub_CHf(R, Rd, Rr); 417 gen_sub_Vf(R, Rd, Rr); 418 gen_ZNSf(R); 419 420 /* update output registers */ 421 tcg_gen_mov_tl(Rd, R); 422 423 tcg_temp_free_i32(R); 424 425 return true; 426 } 427 428 /* 429 * Subtracts a register and a constant and places the result in the 430 * destination register Rd. This instruction is working on Register R16 to R31 431 * and is very well suited for operations on the X, Y, and Z-pointers. 432 */ 433 static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a) 434 { 435 TCGv Rd = cpu_r[a->rd]; 436 TCGv Rr = tcg_const_i32(a->imm); 437 TCGv R = tcg_temp_new_i32(); 438 439 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */ 440 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 441 442 /* update status register */ 443 gen_sub_CHf(R, Rd, Rr); 444 gen_sub_Vf(R, Rd, Rr); 445 gen_ZNSf(R); 446 447 /* update output registers */ 448 tcg_gen_mov_tl(Rd, R); 449 450 tcg_temp_free_i32(R); 451 tcg_temp_free_i32(Rr); 452 453 return true; 454 } 455 456 /* 457 * Subtracts two registers and subtracts with the C Flag and places the 458 * result in the destination register Rd. 459 */ 460 static bool trans_SBC(DisasContext *ctx, arg_SBC *a) 461 { 462 TCGv Rd = cpu_r[a->rd]; 463 TCGv Rr = cpu_r[a->rr]; 464 TCGv R = tcg_temp_new_i32(); 465 TCGv zero = tcg_const_i32(0); 466 467 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 468 tcg_gen_sub_tl(R, R, cpu_Cf); 469 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 470 471 /* update status register */ 472 gen_sub_CHf(R, Rd, Rr); 473 gen_sub_Vf(R, Rd, Rr); 474 gen_NSf(R); 475 476 /* 477 * Previous value remains unchanged when the result is zero; 478 * cleared otherwise. 479 */ 480 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 481 482 /* update output registers */ 483 tcg_gen_mov_tl(Rd, R); 484 485 tcg_temp_free_i32(zero); 486 tcg_temp_free_i32(R); 487 488 return true; 489 } 490 491 /* 492 * SBCI -- Subtract Immediate with Carry 493 */ 494 static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a) 495 { 496 TCGv Rd = cpu_r[a->rd]; 497 TCGv Rr = tcg_const_i32(a->imm); 498 TCGv R = tcg_temp_new_i32(); 499 TCGv zero = tcg_const_i32(0); 500 501 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 502 tcg_gen_sub_tl(R, R, cpu_Cf); 503 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 504 505 /* update status register */ 506 gen_sub_CHf(R, Rd, Rr); 507 gen_sub_Vf(R, Rd, Rr); 508 gen_NSf(R); 509 510 /* 511 * Previous value remains unchanged when the result is zero; 512 * cleared otherwise. 513 */ 514 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 515 516 /* update output registers */ 517 tcg_gen_mov_tl(Rd, R); 518 519 tcg_temp_free_i32(zero); 520 tcg_temp_free_i32(R); 521 tcg_temp_free_i32(Rr); 522 523 return true; 524 } 525 526 /* 527 * Subtracts an immediate value (0-63) from a register pair and places the 528 * result in the register pair. This instruction operates on the upper four 529 * register pairs, and is well suited for operations on the Pointer Registers. 530 * This instruction is not available in all devices. Refer to the device 531 * specific instruction set summary. 532 */ 533 static bool trans_SBIW(DisasContext *ctx, arg_SBIW *a) 534 { 535 if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) { 536 return true; 537 } 538 539 TCGv RdL = cpu_r[a->rd]; 540 TCGv RdH = cpu_r[a->rd + 1]; 541 int Imm = (a->imm); 542 TCGv R = tcg_temp_new_i32(); 543 TCGv Rd = tcg_temp_new_i32(); 544 545 tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */ 546 tcg_gen_subi_tl(R, Rd, Imm); /* R = Rd - Imm */ 547 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 548 549 /* update status register */ 550 tcg_gen_andc_tl(cpu_Cf, R, Rd); 551 tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15); /* Cf = R & ~Rd */ 552 tcg_gen_andc_tl(cpu_Vf, Rd, R); 553 tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15); /* Vf = Rd & ~R */ 554 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 555 tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */ 556 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 557 558 /* update output registers */ 559 tcg_gen_andi_tl(RdL, R, 0xff); 560 tcg_gen_shri_tl(RdH, R, 8); 561 562 tcg_temp_free_i32(Rd); 563 tcg_temp_free_i32(R); 564 565 return true; 566 } 567 568 /* 569 * Performs the logical AND between the contents of register Rd and register 570 * Rr and places the result in the destination register Rd. 571 */ 572 static bool trans_AND(DisasContext *ctx, arg_AND *a) 573 { 574 TCGv Rd = cpu_r[a->rd]; 575 TCGv Rr = cpu_r[a->rr]; 576 TCGv R = tcg_temp_new_i32(); 577 578 tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */ 579 580 /* update status register */ 581 tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */ 582 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 583 gen_ZNSf(R); 584 585 /* update output registers */ 586 tcg_gen_mov_tl(Rd, R); 587 588 tcg_temp_free_i32(R); 589 590 return true; 591 } 592 593 /* 594 * Performs the logical AND between the contents of register Rd and a constant 595 * and places the result in the destination register Rd. 596 */ 597 static bool trans_ANDI(DisasContext *ctx, arg_ANDI *a) 598 { 599 TCGv Rd = cpu_r[a->rd]; 600 int Imm = (a->imm); 601 602 tcg_gen_andi_tl(Rd, Rd, Imm); /* Rd = Rd & Imm */ 603 604 /* update status register */ 605 tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */ 606 gen_ZNSf(Rd); 607 608 return true; 609 } 610 611 /* 612 * Performs the logical OR between the contents of register Rd and register 613 * Rr and places the result in the destination register Rd. 614 */ 615 static bool trans_OR(DisasContext *ctx, arg_OR *a) 616 { 617 TCGv Rd = cpu_r[a->rd]; 618 TCGv Rr = cpu_r[a->rr]; 619 TCGv R = tcg_temp_new_i32(); 620 621 tcg_gen_or_tl(R, Rd, Rr); 622 623 /* update status register */ 624 tcg_gen_movi_tl(cpu_Vf, 0); 625 gen_ZNSf(R); 626 627 /* update output registers */ 628 tcg_gen_mov_tl(Rd, R); 629 630 tcg_temp_free_i32(R); 631 632 return true; 633 } 634 635 /* 636 * Performs the logical OR between the contents of register Rd and a 637 * constant and places the result in the destination register Rd. 638 */ 639 static bool trans_ORI(DisasContext *ctx, arg_ORI *a) 640 { 641 TCGv Rd = cpu_r[a->rd]; 642 int Imm = (a->imm); 643 644 tcg_gen_ori_tl(Rd, Rd, Imm); /* Rd = Rd | Imm */ 645 646 /* update status register */ 647 tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */ 648 gen_ZNSf(Rd); 649 650 return true; 651 } 652 653 /* 654 * Performs the logical EOR between the contents of register Rd and 655 * register Rr and places the result in the destination register Rd. 656 */ 657 static bool trans_EOR(DisasContext *ctx, arg_EOR *a) 658 { 659 TCGv Rd = cpu_r[a->rd]; 660 TCGv Rr = cpu_r[a->rr]; 661 662 tcg_gen_xor_tl(Rd, Rd, Rr); 663 664 /* update status register */ 665 tcg_gen_movi_tl(cpu_Vf, 0); 666 gen_ZNSf(Rd); 667 668 return true; 669 } 670 671 /* 672 * Clears the specified bits in register Rd. Performs the logical AND 673 * between the contents of register Rd and the complement of the constant mask 674 * K. The result will be placed in register Rd. 675 */ 676 static bool trans_COM(DisasContext *ctx, arg_COM *a) 677 { 678 TCGv Rd = cpu_r[a->rd]; 679 TCGv R = tcg_temp_new_i32(); 680 681 tcg_gen_xori_tl(Rd, Rd, 0xff); 682 683 /* update status register */ 684 tcg_gen_movi_tl(cpu_Cf, 1); /* Cf = 1 */ 685 tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */ 686 gen_ZNSf(Rd); 687 688 tcg_temp_free_i32(R); 689 690 return true; 691 } 692 693 /* 694 * Replaces the contents of register Rd with its two's complement; the 695 * value $80 is left unchanged. 696 */ 697 static bool trans_NEG(DisasContext *ctx, arg_NEG *a) 698 { 699 TCGv Rd = cpu_r[a->rd]; 700 TCGv t0 = tcg_const_i32(0); 701 TCGv R = tcg_temp_new_i32(); 702 703 tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */ 704 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 705 706 /* update status register */ 707 gen_sub_CHf(R, t0, Rd); 708 gen_sub_Vf(R, t0, Rd); 709 gen_ZNSf(R); 710 711 /* update output registers */ 712 tcg_gen_mov_tl(Rd, R); 713 714 tcg_temp_free_i32(t0); 715 tcg_temp_free_i32(R); 716 717 return true; 718 } 719 720 /* 721 * Adds one -1- to the contents of register Rd and places the result in the 722 * destination register Rd. The C Flag in SREG is not affected by the 723 * operation, thus allowing the INC instruction to be used on a loop counter in 724 * multiple-precision computations. When operating on unsigned numbers, only 725 * BREQ and BRNE branches can be expected to perform consistently. When 726 * operating on two's complement values, all signed branches are available. 727 */ 728 static bool trans_INC(DisasContext *ctx, arg_INC *a) 729 { 730 TCGv Rd = cpu_r[a->rd]; 731 732 tcg_gen_addi_tl(Rd, Rd, 1); 733 tcg_gen_andi_tl(Rd, Rd, 0xff); 734 735 /* update status register */ 736 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x80); /* Vf = Rd == 0x80 */ 737 gen_ZNSf(Rd); 738 739 return true; 740 } 741 742 /* 743 * Subtracts one -1- from the contents of register Rd and places the result 744 * in the destination register Rd. The C Flag in SREG is not affected by the 745 * operation, thus allowing the DEC instruction to be used on a loop counter in 746 * multiple-precision computations. When operating on unsigned values, only 747 * BREQ and BRNE branches can be expected to perform consistently. When 748 * operating on two's complement values, all signed branches are available. 749 */ 750 static bool trans_DEC(DisasContext *ctx, arg_DEC *a) 751 { 752 TCGv Rd = cpu_r[a->rd]; 753 754 tcg_gen_subi_tl(Rd, Rd, 1); /* Rd = Rd - 1 */ 755 tcg_gen_andi_tl(Rd, Rd, 0xff); /* make it 8 bits */ 756 757 /* update status register */ 758 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x7f); /* Vf = Rd == 0x7f */ 759 gen_ZNSf(Rd); 760 761 return true; 762 } 763 764 /* 765 * This instruction performs 8-bit x 8-bit -> 16-bit unsigned multiplication. 766 */ 767 static bool trans_MUL(DisasContext *ctx, arg_MUL *a) 768 { 769 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 770 return true; 771 } 772 773 TCGv R0 = cpu_r[0]; 774 TCGv R1 = cpu_r[1]; 775 TCGv Rd = cpu_r[a->rd]; 776 TCGv Rr = cpu_r[a->rr]; 777 TCGv R = tcg_temp_new_i32(); 778 779 tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd * Rr */ 780 tcg_gen_andi_tl(R0, R, 0xff); 781 tcg_gen_shri_tl(R1, R, 8); 782 783 /* update status register */ 784 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 785 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 786 787 tcg_temp_free_i32(R); 788 789 return true; 790 } 791 792 /* 793 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication. 794 */ 795 static bool trans_MULS(DisasContext *ctx, arg_MULS *a) 796 { 797 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 798 return true; 799 } 800 801 TCGv R0 = cpu_r[0]; 802 TCGv R1 = cpu_r[1]; 803 TCGv Rd = cpu_r[a->rd]; 804 TCGv Rr = cpu_r[a->rr]; 805 TCGv R = tcg_temp_new_i32(); 806 TCGv t0 = tcg_temp_new_i32(); 807 TCGv t1 = tcg_temp_new_i32(); 808 809 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 810 tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */ 811 tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */ 812 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 813 tcg_gen_andi_tl(R0, R, 0xff); 814 tcg_gen_shri_tl(R1, R, 8); 815 816 /* update status register */ 817 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 818 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 819 820 tcg_temp_free_i32(t1); 821 tcg_temp_free_i32(t0); 822 tcg_temp_free_i32(R); 823 824 return true; 825 } 826 827 /* 828 * This instruction performs 8-bit x 8-bit -> 16-bit multiplication of a 829 * signed and an unsigned number. 830 */ 831 static bool trans_MULSU(DisasContext *ctx, arg_MULSU *a) 832 { 833 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 834 return true; 835 } 836 837 TCGv R0 = cpu_r[0]; 838 TCGv R1 = cpu_r[1]; 839 TCGv Rd = cpu_r[a->rd]; 840 TCGv Rr = cpu_r[a->rr]; 841 TCGv R = tcg_temp_new_i32(); 842 TCGv t0 = tcg_temp_new_i32(); 843 844 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 845 tcg_gen_mul_tl(R, t0, Rr); /* R = Rd * Rr */ 846 tcg_gen_andi_tl(R, R, 0xffff); /* make R 16 bits */ 847 tcg_gen_andi_tl(R0, R, 0xff); 848 tcg_gen_shri_tl(R1, R, 8); 849 850 /* update status register */ 851 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 852 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 853 854 tcg_temp_free_i32(t0); 855 tcg_temp_free_i32(R); 856 857 return true; 858 } 859 860 /* 861 * This instruction performs 8-bit x 8-bit -> 16-bit unsigned 862 * multiplication and shifts the result one bit left. 863 */ 864 static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a) 865 { 866 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 867 return true; 868 } 869 870 TCGv R0 = cpu_r[0]; 871 TCGv R1 = cpu_r[1]; 872 TCGv Rd = cpu_r[a->rd]; 873 TCGv Rr = cpu_r[a->rr]; 874 TCGv R = tcg_temp_new_i32(); 875 876 tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd * Rr */ 877 878 /* update status register */ 879 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 880 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 881 882 /* update output registers */ 883 tcg_gen_shli_tl(R, R, 1); 884 tcg_gen_andi_tl(R0, R, 0xff); 885 tcg_gen_shri_tl(R1, R, 8); 886 tcg_gen_andi_tl(R1, R1, 0xff); 887 888 889 tcg_temp_free_i32(R); 890 891 return true; 892 } 893 894 /* 895 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication 896 * and shifts the result one bit left. 897 */ 898 static bool trans_FMULS(DisasContext *ctx, arg_FMULS *a) 899 { 900 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 901 return true; 902 } 903 904 TCGv R0 = cpu_r[0]; 905 TCGv R1 = cpu_r[1]; 906 TCGv Rd = cpu_r[a->rd]; 907 TCGv Rr = cpu_r[a->rr]; 908 TCGv R = tcg_temp_new_i32(); 909 TCGv t0 = tcg_temp_new_i32(); 910 TCGv t1 = tcg_temp_new_i32(); 911 912 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 913 tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */ 914 tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */ 915 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 916 917 /* update status register */ 918 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 919 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 920 921 /* update output registers */ 922 tcg_gen_shli_tl(R, R, 1); 923 tcg_gen_andi_tl(R0, R, 0xff); 924 tcg_gen_shri_tl(R1, R, 8); 925 tcg_gen_andi_tl(R1, R1, 0xff); 926 927 tcg_temp_free_i32(t1); 928 tcg_temp_free_i32(t0); 929 tcg_temp_free_i32(R); 930 931 return true; 932 } 933 934 /* 935 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication 936 * and shifts the result one bit left. 937 */ 938 static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU *a) 939 { 940 if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 941 return true; 942 } 943 944 TCGv R0 = cpu_r[0]; 945 TCGv R1 = cpu_r[1]; 946 TCGv Rd = cpu_r[a->rd]; 947 TCGv Rr = cpu_r[a->rr]; 948 TCGv R = tcg_temp_new_i32(); 949 TCGv t0 = tcg_temp_new_i32(); 950 951 tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 952 tcg_gen_mul_tl(R, t0, Rr); /* R = Rd * Rr */ 953 tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 954 955 /* update status register */ 956 tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 957 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 958 959 /* update output registers */ 960 tcg_gen_shli_tl(R, R, 1); 961 tcg_gen_andi_tl(R0, R, 0xff); 962 tcg_gen_shri_tl(R1, R, 8); 963 tcg_gen_andi_tl(R1, R1, 0xff); 964 965 tcg_temp_free_i32(t0); 966 tcg_temp_free_i32(R); 967 968 return true; 969 } 970 971 /* 972 * The module is an instruction set extension to the AVR CPU, performing 973 * DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in 974 * the CPU register file, registers R0-R7, where LSB of data is placed in LSB 975 * of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (including 976 * parity bits) is placed in registers R8- R15, organized in the register file 977 * with LSB of key in LSB of R8 and MSB of key in MSB of R15. Executing one DES 978 * instruction performs one round in the DES algorithm. Sixteen rounds must be 979 * executed in increasing order to form the correct DES ciphertext or 980 * plaintext. Intermediate results are stored in the register file (R0-R15) 981 * after each DES instruction. The instruction's operand (K) determines which 982 * round is executed, and the half carry flag (H) determines whether encryption 983 * or decryption is performed. The DES algorithm is described in 984 * "Specifications for the Data Encryption Standard" (Federal Information 985 * Processing Standards Publication 46). Intermediate results in this 986 * implementation differ from the standard because the initial permutation and 987 * the inverse initial permutation are performed each iteration. This does not 988 * affect the result in the final ciphertext or plaintext, but reduces 989 * execution time. 990 */ 991 static bool trans_DES(DisasContext *ctx, arg_DES *a) 992 { 993 /* TODO */ 994 if (!avr_have_feature(ctx, AVR_FEATURE_DES)) { 995 return true; 996 } 997 998 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); 999 1000 return true; 1001 } 1002 1003 /* 1004 * Branch Instructions 1005 */ 1006 static void gen_jmp_ez(DisasContext *ctx) 1007 { 1008 tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8); 1009 tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind); 1010 ctx->base.is_jmp = DISAS_LOOKUP; 1011 } 1012 1013 static void gen_jmp_z(DisasContext *ctx) 1014 { 1015 tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8); 1016 ctx->base.is_jmp = DISAS_LOOKUP; 1017 } 1018 1019 static void gen_push_ret(DisasContext *ctx, int ret) 1020 { 1021 if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { 1022 1023 TCGv t0 = tcg_const_i32((ret & 0x0000ff)); 1024 1025 tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB); 1026 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1027 1028 tcg_temp_free_i32(t0); 1029 } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { 1030 1031 TCGv t0 = tcg_const_i32((ret & 0x00ffff)); 1032 1033 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1034 tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1035 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1036 1037 tcg_temp_free_i32(t0); 1038 1039 } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { 1040 1041 TCGv lo = tcg_const_i32((ret & 0x0000ff)); 1042 TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8); 1043 1044 tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); 1045 tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); 1046 tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1047 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 1048 1049 tcg_temp_free_i32(lo); 1050 tcg_temp_free_i32(hi); 1051 } 1052 } 1053 1054 static void gen_pop_ret(DisasContext *ctx, TCGv ret) 1055 { 1056 if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { 1057 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1058 tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB); 1059 } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { 1060 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1061 tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1062 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1063 } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { 1064 TCGv lo = tcg_temp_new_i32(); 1065 TCGv hi = tcg_temp_new_i32(); 1066 1067 tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 1068 tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); 1069 1070 tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); 1071 tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); 1072 1073 tcg_gen_deposit_tl(ret, lo, hi, 8, 16); 1074 1075 tcg_temp_free_i32(lo); 1076 tcg_temp_free_i32(hi); 1077 } 1078 } 1079 1080 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 1081 { 1082 const TranslationBlock *tb = ctx->base.tb; 1083 1084 if (translator_use_goto_tb(&ctx->base, dest)) { 1085 tcg_gen_goto_tb(n); 1086 tcg_gen_movi_i32(cpu_pc, dest); 1087 tcg_gen_exit_tb(tb, n); 1088 } else { 1089 tcg_gen_movi_i32(cpu_pc, dest); 1090 if (ctx->base.singlestep_enabled) { 1091 gen_helper_debug(cpu_env); 1092 } else { 1093 tcg_gen_lookup_and_goto_ptr(); 1094 } 1095 } 1096 ctx->base.is_jmp = DISAS_NORETURN; 1097 } 1098 1099 /* 1100 * Relative jump to an address within PC - 2K +1 and PC + 2K (words). For 1101 * AVR microcontrollers with Program memory not exceeding 4K words (8KB) this 1102 * instruction can address the entire memory from every address location. See 1103 * also JMP. 1104 */ 1105 static bool trans_RJMP(DisasContext *ctx, arg_RJMP *a) 1106 { 1107 int dst = ctx->npc + a->imm; 1108 1109 gen_goto_tb(ctx, 0, dst); 1110 1111 return true; 1112 } 1113 1114 /* 1115 * Indirect jump to the address pointed to by the Z (16 bits) Pointer 1116 * Register in the Register File. The Z-pointer Register is 16 bits wide and 1117 * allows jump within the lowest 64K words (128KB) section of Program memory. 1118 * This instruction is not available in all devices. Refer to the device 1119 * specific instruction set summary. 1120 */ 1121 static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a) 1122 { 1123 if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) { 1124 return true; 1125 } 1126 1127 gen_jmp_z(ctx); 1128 1129 return true; 1130 } 1131 1132 /* 1133 * Indirect jump to the address pointed to by the Z (16 bits) Pointer 1134 * Register in the Register File and the EIND Register in the I/O space. This 1135 * instruction allows for indirect jumps to the entire 4M (words) Program 1136 * memory space. See also IJMP. This instruction is not available in all 1137 * devices. Refer to the device specific instruction set summary. 1138 */ 1139 static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a) 1140 { 1141 if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) { 1142 return true; 1143 } 1144 1145 gen_jmp_ez(ctx); 1146 return true; 1147 } 1148 1149 /* 1150 * Jump to an address within the entire 4M (words) Program memory. See also 1151 * RJMP. This instruction is not available in all devices. Refer to the device 1152 * specific instruction set summary.0 1153 */ 1154 static bool trans_JMP(DisasContext *ctx, arg_JMP *a) 1155 { 1156 if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) { 1157 return true; 1158 } 1159 1160 gen_goto_tb(ctx, 0, a->imm); 1161 1162 return true; 1163 } 1164 1165 /* 1166 * Relative call to an address within PC - 2K + 1 and PC + 2K (words). The 1167 * return address (the instruction after the RCALL) is stored onto the Stack. 1168 * See also CALL. For AVR microcontrollers with Program memory not exceeding 4K 1169 * words (8KB) this instruction can address the entire memory from every 1170 * address location. The Stack Pointer uses a post-decrement scheme during 1171 * RCALL. 1172 */ 1173 static bool trans_RCALL(DisasContext *ctx, arg_RCALL *a) 1174 { 1175 int ret = ctx->npc; 1176 int dst = ctx->npc + a->imm; 1177 1178 gen_push_ret(ctx, ret); 1179 gen_goto_tb(ctx, 0, dst); 1180 1181 return true; 1182 } 1183 1184 /* 1185 * Calls to a subroutine within the entire 4M (words) Program memory. The 1186 * return address (to the instruction after the CALL) will be stored onto the 1187 * Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during 1188 * CALL. This instruction is not available in all devices. Refer to the device 1189 * specific instruction set summary. 1190 */ 1191 static bool trans_ICALL(DisasContext *ctx, arg_ICALL *a) 1192 { 1193 if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) { 1194 return true; 1195 } 1196 1197 int ret = ctx->npc; 1198 1199 gen_push_ret(ctx, ret); 1200 gen_jmp_z(ctx); 1201 1202 return true; 1203 } 1204 1205 /* 1206 * Indirect call of a subroutine pointed to by the Z (16 bits) Pointer 1207 * Register in the Register File and the EIND Register in the I/O space. This 1208 * instruction allows for indirect calls to the entire 4M (words) Program 1209 * memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme 1210 * during EICALL. This instruction is not available in all devices. Refer to 1211 * the device specific instruction set summary. 1212 */ 1213 static bool trans_EICALL(DisasContext *ctx, arg_EICALL *a) 1214 { 1215 if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) { 1216 return true; 1217 } 1218 1219 int ret = ctx->npc; 1220 1221 gen_push_ret(ctx, ret); 1222 gen_jmp_ez(ctx); 1223 return true; 1224 } 1225 1226 /* 1227 * Calls to a subroutine within the entire Program memory. The return 1228 * address (to the instruction after the CALL) will be stored onto the Stack. 1229 * (See also RCALL). The Stack Pointer uses a post-decrement scheme during 1230 * CALL. This instruction is not available in all devices. Refer to the device 1231 * specific instruction set summary. 1232 */ 1233 static bool trans_CALL(DisasContext *ctx, arg_CALL *a) 1234 { 1235 if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) { 1236 return true; 1237 } 1238 1239 int Imm = a->imm; 1240 int ret = ctx->npc; 1241 1242 gen_push_ret(ctx, ret); 1243 gen_goto_tb(ctx, 0, Imm); 1244 1245 return true; 1246 } 1247 1248 /* 1249 * Returns from subroutine. The return address is loaded from the STACK. 1250 * The Stack Pointer uses a preincrement scheme during RET. 1251 */ 1252 static bool trans_RET(DisasContext *ctx, arg_RET *a) 1253 { 1254 gen_pop_ret(ctx, cpu_pc); 1255 1256 ctx->base.is_jmp = DISAS_LOOKUP; 1257 return true; 1258 } 1259 1260 /* 1261 * Returns from interrupt. The return address is loaded from the STACK and 1262 * the Global Interrupt Flag is set. Note that the Status Register is not 1263 * automatically stored when entering an interrupt routine, and it is not 1264 * restored when returning from an interrupt routine. This must be handled by 1265 * the application program. The Stack Pointer uses a pre-increment scheme 1266 * during RETI. 1267 */ 1268 static bool trans_RETI(DisasContext *ctx, arg_RETI *a) 1269 { 1270 gen_pop_ret(ctx, cpu_pc); 1271 tcg_gen_movi_tl(cpu_If, 1); 1272 1273 /* Need to return to main loop to re-evaluate interrupts. */ 1274 ctx->base.is_jmp = DISAS_EXIT; 1275 return true; 1276 } 1277 1278 /* 1279 * This instruction performs a compare between two registers Rd and Rr, and 1280 * skips the next instruction if Rd = Rr. 1281 */ 1282 static bool trans_CPSE(DisasContext *ctx, arg_CPSE *a) 1283 { 1284 ctx->skip_cond = TCG_COND_EQ; 1285 ctx->skip_var0 = cpu_r[a->rd]; 1286 ctx->skip_var1 = cpu_r[a->rr]; 1287 return true; 1288 } 1289 1290 /* 1291 * This instruction performs a compare between two registers Rd and Rr. 1292 * None of the registers are changed. All conditional branches can be used 1293 * after this instruction. 1294 */ 1295 static bool trans_CP(DisasContext *ctx, arg_CP *a) 1296 { 1297 TCGv Rd = cpu_r[a->rd]; 1298 TCGv Rr = cpu_r[a->rr]; 1299 TCGv R = tcg_temp_new_i32(); 1300 1301 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 1302 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 1303 1304 /* update status register */ 1305 gen_sub_CHf(R, Rd, Rr); 1306 gen_sub_Vf(R, Rd, Rr); 1307 gen_ZNSf(R); 1308 1309 tcg_temp_free_i32(R); 1310 1311 return true; 1312 } 1313 1314 /* 1315 * This instruction performs a compare between two registers Rd and Rr and 1316 * also takes into account the previous carry. None of the registers are 1317 * changed. All conditional branches can be used after this instruction. 1318 */ 1319 static bool trans_CPC(DisasContext *ctx, arg_CPC *a) 1320 { 1321 TCGv Rd = cpu_r[a->rd]; 1322 TCGv Rr = cpu_r[a->rr]; 1323 TCGv R = tcg_temp_new_i32(); 1324 TCGv zero = tcg_const_i32(0); 1325 1326 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 1327 tcg_gen_sub_tl(R, R, cpu_Cf); 1328 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 1329 /* update status register */ 1330 gen_sub_CHf(R, Rd, Rr); 1331 gen_sub_Vf(R, Rd, Rr); 1332 gen_NSf(R); 1333 1334 /* 1335 * Previous value remains unchanged when the result is zero; 1336 * cleared otherwise. 1337 */ 1338 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 1339 1340 tcg_temp_free_i32(zero); 1341 tcg_temp_free_i32(R); 1342 1343 return true; 1344 } 1345 1346 /* 1347 * This instruction performs a compare between register Rd and a constant. 1348 * The register is not changed. All conditional branches can be used after this 1349 * instruction. 1350 */ 1351 static bool trans_CPI(DisasContext *ctx, arg_CPI *a) 1352 { 1353 TCGv Rd = cpu_r[a->rd]; 1354 int Imm = a->imm; 1355 TCGv Rr = tcg_const_i32(Imm); 1356 TCGv R = tcg_temp_new_i32(); 1357 1358 tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 1359 tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 1360 1361 /* update status register */ 1362 gen_sub_CHf(R, Rd, Rr); 1363 gen_sub_Vf(R, Rd, Rr); 1364 gen_ZNSf(R); 1365 1366 tcg_temp_free_i32(R); 1367 tcg_temp_free_i32(Rr); 1368 1369 return true; 1370 } 1371 1372 /* 1373 * This instruction tests a single bit in a register and skips the next 1374 * instruction if the bit is cleared. 1375 */ 1376 static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a) 1377 { 1378 TCGv Rr = cpu_r[a->rr]; 1379 1380 ctx->skip_cond = TCG_COND_EQ; 1381 ctx->skip_var0 = tcg_temp_new(); 1382 ctx->free_skip_var0 = true; 1383 1384 tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); 1385 return true; 1386 } 1387 1388 /* 1389 * This instruction tests a single bit in a register and skips the next 1390 * instruction if the bit is set. 1391 */ 1392 static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) 1393 { 1394 TCGv Rr = cpu_r[a->rr]; 1395 1396 ctx->skip_cond = TCG_COND_NE; 1397 ctx->skip_var0 = tcg_temp_new(); 1398 ctx->free_skip_var0 = true; 1399 1400 tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); 1401 return true; 1402 } 1403 1404 /* 1405 * This instruction tests a single bit in an I/O Register and skips the 1406 * next instruction if the bit is cleared. This instruction operates on the 1407 * lower 32 I/O Registers -- addresses 0-31. 1408 */ 1409 static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) 1410 { 1411 TCGv temp = tcg_const_i32(a->reg); 1412 1413 gen_helper_inb(temp, cpu_env, temp); 1414 tcg_gen_andi_tl(temp, temp, 1 << a->bit); 1415 ctx->skip_cond = TCG_COND_EQ; 1416 ctx->skip_var0 = temp; 1417 ctx->free_skip_var0 = true; 1418 1419 return true; 1420 } 1421 1422 /* 1423 * This instruction tests a single bit in an I/O Register and skips the 1424 * next instruction if the bit is set. This instruction operates on the lower 1425 * 32 I/O Registers -- addresses 0-31. 1426 */ 1427 static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) 1428 { 1429 TCGv temp = tcg_const_i32(a->reg); 1430 1431 gen_helper_inb(temp, cpu_env, temp); 1432 tcg_gen_andi_tl(temp, temp, 1 << a->bit); 1433 ctx->skip_cond = TCG_COND_NE; 1434 ctx->skip_var0 = temp; 1435 ctx->free_skip_var0 = true; 1436 1437 return true; 1438 } 1439 1440 /* 1441 * Conditional relative branch. Tests a single bit in SREG and branches 1442 * relatively to PC if the bit is cleared. This instruction branches relatively 1443 * to PC in either direction (PC - 63 < = destination <= PC + 64). The 1444 * parameter k is the offset from PC and is represented in two's complement 1445 * form. 1446 */ 1447 static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a) 1448 { 1449 TCGLabel *not_taken = gen_new_label(); 1450 1451 TCGv var; 1452 1453 switch (a->bit) { 1454 case 0x00: 1455 var = cpu_Cf; 1456 break; 1457 case 0x01: 1458 var = cpu_Zf; 1459 break; 1460 case 0x02: 1461 var = cpu_Nf; 1462 break; 1463 case 0x03: 1464 var = cpu_Vf; 1465 break; 1466 case 0x04: 1467 var = cpu_Sf; 1468 break; 1469 case 0x05: 1470 var = cpu_Hf; 1471 break; 1472 case 0x06: 1473 var = cpu_Tf; 1474 break; 1475 case 0x07: 1476 var = cpu_If; 1477 break; 1478 default: 1479 g_assert_not_reached(); 1480 } 1481 1482 tcg_gen_brcondi_i32(TCG_COND_NE, var, 0, not_taken); 1483 gen_goto_tb(ctx, 0, ctx->npc + a->imm); 1484 gen_set_label(not_taken); 1485 1486 ctx->base.is_jmp = DISAS_CHAIN; 1487 return true; 1488 } 1489 1490 /* 1491 * Conditional relative branch. Tests a single bit in SREG and branches 1492 * relatively to PC if the bit is set. This instruction branches relatively to 1493 * PC in either direction (PC - 63 < = destination <= PC + 64). The parameter k 1494 * is the offset from PC and is represented in two's complement form. 1495 */ 1496 static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a) 1497 { 1498 TCGLabel *not_taken = gen_new_label(); 1499 1500 TCGv var; 1501 1502 switch (a->bit) { 1503 case 0x00: 1504 var = cpu_Cf; 1505 break; 1506 case 0x01: 1507 var = cpu_Zf; 1508 break; 1509 case 0x02: 1510 var = cpu_Nf; 1511 break; 1512 case 0x03: 1513 var = cpu_Vf; 1514 break; 1515 case 0x04: 1516 var = cpu_Sf; 1517 break; 1518 case 0x05: 1519 var = cpu_Hf; 1520 break; 1521 case 0x06: 1522 var = cpu_Tf; 1523 break; 1524 case 0x07: 1525 var = cpu_If; 1526 break; 1527 default: 1528 g_assert_not_reached(); 1529 } 1530 1531 tcg_gen_brcondi_i32(TCG_COND_EQ, var, 0, not_taken); 1532 gen_goto_tb(ctx, 0, ctx->npc + a->imm); 1533 gen_set_label(not_taken); 1534 1535 ctx->base.is_jmp = DISAS_CHAIN; 1536 return true; 1537 } 1538 1539 /* 1540 * Data Transfer Instructions 1541 */ 1542 1543 /* 1544 * in the gen_set_addr & gen_get_addr functions 1545 * H assumed to be in 0x00ff0000 format 1546 * M assumed to be in 0x000000ff format 1547 * L assumed to be in 0x000000ff format 1548 */ 1549 static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L) 1550 { 1551 1552 tcg_gen_andi_tl(L, addr, 0x000000ff); 1553 1554 tcg_gen_andi_tl(M, addr, 0x0000ff00); 1555 tcg_gen_shri_tl(M, M, 8); 1556 1557 tcg_gen_andi_tl(H, addr, 0x00ff0000); 1558 } 1559 1560 static void gen_set_xaddr(TCGv addr) 1561 { 1562 gen_set_addr(addr, cpu_rampX, cpu_r[27], cpu_r[26]); 1563 } 1564 1565 static void gen_set_yaddr(TCGv addr) 1566 { 1567 gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]); 1568 } 1569 1570 static void gen_set_zaddr(TCGv addr) 1571 { 1572 gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]); 1573 } 1574 1575 static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L) 1576 { 1577 TCGv addr = tcg_temp_new_i32(); 1578 1579 tcg_gen_deposit_tl(addr, M, H, 8, 8); 1580 tcg_gen_deposit_tl(addr, L, addr, 8, 16); 1581 1582 return addr; 1583 } 1584 1585 static TCGv gen_get_xaddr(void) 1586 { 1587 return gen_get_addr(cpu_rampX, cpu_r[27], cpu_r[26]); 1588 } 1589 1590 static TCGv gen_get_yaddr(void) 1591 { 1592 return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]); 1593 } 1594 1595 static TCGv gen_get_zaddr(void) 1596 { 1597 return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]); 1598 } 1599 1600 /* 1601 * Load one byte indirect from data space to register and stores an clear 1602 * the bits in data space specified by the register. The instruction can only 1603 * be used towards internal SRAM. The data location is pointed to by the Z (16 1604 * bits) Pointer Register in the Register File. Memory access is limited to the 1605 * current data segment of 64KB. To access another data segment in devices with 1606 * more than 64KB data space, the RAMPZ in register in the I/O area has to be 1607 * changed. The Z-pointer Register is left unchanged by the operation. This 1608 * instruction is especially suited for clearing status bits stored in SRAM. 1609 */ 1610 static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) 1611 { 1612 if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { 1613 gen_helper_fullwr(cpu_env, data, addr); 1614 } else { 1615 tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */ 1616 } 1617 } 1618 1619 static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) 1620 { 1621 if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { 1622 gen_helper_fullrd(data, cpu_env, addr); 1623 } else { 1624 tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */ 1625 } 1626 } 1627 1628 /* 1629 * This instruction makes a copy of one register into another. The source 1630 * register Rr is left unchanged, while the destination register Rd is loaded 1631 * with a copy of Rr. 1632 */ 1633 static bool trans_MOV(DisasContext *ctx, arg_MOV *a) 1634 { 1635 TCGv Rd = cpu_r[a->rd]; 1636 TCGv Rr = cpu_r[a->rr]; 1637 1638 tcg_gen_mov_tl(Rd, Rr); 1639 1640 return true; 1641 } 1642 1643 /* 1644 * This instruction makes a copy of one register pair into another register 1645 * pair. The source register pair Rr+1:Rr is left unchanged, while the 1646 * destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr. This 1647 * instruction is not available in all devices. Refer to the device specific 1648 * instruction set summary. 1649 */ 1650 static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a) 1651 { 1652 if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) { 1653 return true; 1654 } 1655 1656 TCGv RdL = cpu_r[a->rd]; 1657 TCGv RdH = cpu_r[a->rd + 1]; 1658 TCGv RrL = cpu_r[a->rr]; 1659 TCGv RrH = cpu_r[a->rr + 1]; 1660 1661 tcg_gen_mov_tl(RdH, RrH); 1662 tcg_gen_mov_tl(RdL, RrL); 1663 1664 return true; 1665 } 1666 1667 /* 1668 * Loads an 8 bit constant directly to register 16 to 31. 1669 */ 1670 static bool trans_LDI(DisasContext *ctx, arg_LDI *a) 1671 { 1672 TCGv Rd = cpu_r[a->rd]; 1673 int imm = a->imm; 1674 1675 tcg_gen_movi_tl(Rd, imm); 1676 1677 return true; 1678 } 1679 1680 /* 1681 * Loads one byte from the data space to a register. For parts with SRAM, 1682 * the data space consists of the Register File, I/O memory and internal SRAM 1683 * (and external SRAM if applicable). For parts without SRAM, the data space 1684 * consists of the register file only. The EEPROM has a separate address space. 1685 * A 16-bit address must be supplied. Memory access is limited to the current 1686 * data segment of 64KB. The LDS instruction uses the RAMPD Register to access 1687 * memory above 64KB. To access another data segment in devices with more than 1688 * 64KB data space, the RAMPD in register in the I/O area has to be changed. 1689 * This instruction is not available in all devices. Refer to the device 1690 * specific instruction set summary. 1691 */ 1692 static bool trans_LDS(DisasContext *ctx, arg_LDS *a) 1693 { 1694 TCGv Rd = cpu_r[a->rd]; 1695 TCGv addr = tcg_temp_new_i32(); 1696 TCGv H = cpu_rampD; 1697 a->imm = next_word(ctx); 1698 1699 tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ 1700 tcg_gen_shli_tl(addr, addr, 16); 1701 tcg_gen_ori_tl(addr, addr, a->imm); 1702 1703 gen_data_load(ctx, Rd, addr); 1704 1705 tcg_temp_free_i32(addr); 1706 1707 return true; 1708 } 1709 1710 /* 1711 * Loads one byte indirect from the data space to a register. For parts 1712 * with SRAM, the data space consists of the Register File, I/O memory and 1713 * internal SRAM (and external SRAM if applicable). For parts without SRAM, the 1714 * data space consists of the Register File only. In some parts the Flash 1715 * Memory has been mapped to the data space and can be read using this command. 1716 * The EEPROM has a separate address space. The data location is pointed to by 1717 * the X (16 bits) Pointer Register in the Register File. Memory access is 1718 * limited to the current data segment of 64KB. To access another data segment 1719 * in devices with more than 64KB data space, the RAMPX in register in the I/O 1720 * area has to be changed. The X-pointer Register can either be left unchanged 1721 * by the operation, or it can be post-incremented or predecremented. These 1722 * features are especially suited for accessing arrays, tables, and Stack 1723 * Pointer usage of the X-pointer Register. Note that only the low byte of the 1724 * X-pointer is updated in devices with no more than 256 bytes data space. For 1725 * such devices, the high byte of the pointer is not used by this instruction 1726 * and can be used for other purposes. The RAMPX Register in the I/O area is 1727 * updated in parts with more than 64KB data space or more than 64KB Program 1728 * memory, and the increment/decrement is added to the entire 24-bit address on 1729 * such devices. Not all variants of this instruction is available in all 1730 * devices. Refer to the device specific instruction set summary. In the 1731 * Reduced Core tinyAVR the LD instruction can be used to achieve the same 1732 * operation as LPM since the program memory is mapped to the data memory 1733 * space. 1734 */ 1735 static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a) 1736 { 1737 TCGv Rd = cpu_r[a->rd]; 1738 TCGv addr = gen_get_xaddr(); 1739 1740 gen_data_load(ctx, Rd, addr); 1741 1742 tcg_temp_free_i32(addr); 1743 1744 return true; 1745 } 1746 1747 static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a) 1748 { 1749 TCGv Rd = cpu_r[a->rd]; 1750 TCGv addr = gen_get_xaddr(); 1751 1752 gen_data_load(ctx, Rd, addr); 1753 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1754 1755 gen_set_xaddr(addr); 1756 1757 tcg_temp_free_i32(addr); 1758 1759 return true; 1760 } 1761 1762 static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a) 1763 { 1764 TCGv Rd = cpu_r[a->rd]; 1765 TCGv addr = gen_get_xaddr(); 1766 1767 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1768 gen_data_load(ctx, Rd, addr); 1769 gen_set_xaddr(addr); 1770 1771 tcg_temp_free_i32(addr); 1772 1773 return true; 1774 } 1775 1776 /* 1777 * Loads one byte indirect with or without displacement from the data space 1778 * to a register. For parts with SRAM, the data space consists of the Register 1779 * File, I/O memory and internal SRAM (and external SRAM if applicable). For 1780 * parts without SRAM, the data space consists of the Register File only. In 1781 * some parts the Flash Memory has been mapped to the data space and can be 1782 * read using this command. The EEPROM has a separate address space. The data 1783 * location is pointed to by the Y (16 bits) Pointer Register in the Register 1784 * File. Memory access is limited to the current data segment of 64KB. To 1785 * access another data segment in devices with more than 64KB data space, the 1786 * RAMPY in register in the I/O area has to be changed. The Y-pointer Register 1787 * can either be left unchanged by the operation, or it can be post-incremented 1788 * or predecremented. These features are especially suited for accessing 1789 * arrays, tables, and Stack Pointer usage of the Y-pointer Register. Note that 1790 * only the low byte of the Y-pointer is updated in devices with no more than 1791 * 256 bytes data space. For such devices, the high byte of the pointer is not 1792 * used by this instruction and can be used for other purposes. The RAMPY 1793 * Register in the I/O area is updated in parts with more than 64KB data space 1794 * or more than 64KB Program memory, and the increment/decrement/displacement 1795 * is added to the entire 24-bit address on such devices. Not all variants of 1796 * this instruction is available in all devices. Refer to the device specific 1797 * instruction set summary. In the Reduced Core tinyAVR the LD instruction can 1798 * be used to achieve the same operation as LPM since the program memory is 1799 * mapped to the data memory space. 1800 */ 1801 static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a) 1802 { 1803 TCGv Rd = cpu_r[a->rd]; 1804 TCGv addr = gen_get_yaddr(); 1805 1806 gen_data_load(ctx, Rd, addr); 1807 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1808 1809 gen_set_yaddr(addr); 1810 1811 tcg_temp_free_i32(addr); 1812 1813 return true; 1814 } 1815 1816 static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a) 1817 { 1818 TCGv Rd = cpu_r[a->rd]; 1819 TCGv addr = gen_get_yaddr(); 1820 1821 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1822 gen_data_load(ctx, Rd, addr); 1823 gen_set_yaddr(addr); 1824 1825 tcg_temp_free_i32(addr); 1826 1827 return true; 1828 } 1829 1830 static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a) 1831 { 1832 TCGv Rd = cpu_r[a->rd]; 1833 TCGv addr = gen_get_yaddr(); 1834 1835 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 1836 gen_data_load(ctx, Rd, addr); 1837 1838 tcg_temp_free_i32(addr); 1839 1840 return true; 1841 } 1842 1843 /* 1844 * Loads one byte indirect with or without displacement from the data space 1845 * to a register. For parts with SRAM, the data space consists of the Register 1846 * File, I/O memory and internal SRAM (and external SRAM if applicable). For 1847 * parts without SRAM, the data space consists of the Register File only. In 1848 * some parts the Flash Memory has been mapped to the data space and can be 1849 * read using this command. The EEPROM has a separate address space. The data 1850 * location is pointed to by the Z (16 bits) Pointer Register in the Register 1851 * File. Memory access is limited to the current data segment of 64KB. To 1852 * access another data segment in devices with more than 64KB data space, the 1853 * RAMPZ in register in the I/O area has to be changed. The Z-pointer Register 1854 * can either be left unchanged by the operation, or it can be post-incremented 1855 * or predecremented. These features are especially suited for Stack Pointer 1856 * usage of the Z-pointer Register, however because the Z-pointer Register can 1857 * be used for indirect subroutine calls, indirect jumps and table lookup, it 1858 * is often more convenient to use the X or Y-pointer as a dedicated Stack 1859 * Pointer. Note that only the low byte of the Z-pointer is updated in devices 1860 * with no more than 256 bytes data space. For such devices, the high byte of 1861 * the pointer is not used by this instruction and can be used for other 1862 * purposes. The RAMPZ Register in the I/O area is updated in parts with more 1863 * than 64KB data space or more than 64KB Program memory, and the 1864 * increment/decrement/displacement is added to the entire 24-bit address on 1865 * such devices. Not all variants of this instruction is available in all 1866 * devices. Refer to the device specific instruction set summary. In the 1867 * Reduced Core tinyAVR the LD instruction can be used to achieve the same 1868 * operation as LPM since the program memory is mapped to the data memory 1869 * space. For using the Z-pointer for table lookup in Program memory see the 1870 * LPM and ELPM instructions. 1871 */ 1872 static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a) 1873 { 1874 TCGv Rd = cpu_r[a->rd]; 1875 TCGv addr = gen_get_zaddr(); 1876 1877 gen_data_load(ctx, Rd, addr); 1878 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1879 1880 gen_set_zaddr(addr); 1881 1882 tcg_temp_free_i32(addr); 1883 1884 return true; 1885 } 1886 1887 static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a) 1888 { 1889 TCGv Rd = cpu_r[a->rd]; 1890 TCGv addr = gen_get_zaddr(); 1891 1892 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1893 gen_data_load(ctx, Rd, addr); 1894 1895 gen_set_zaddr(addr); 1896 1897 tcg_temp_free_i32(addr); 1898 1899 return true; 1900 } 1901 1902 static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a) 1903 { 1904 TCGv Rd = cpu_r[a->rd]; 1905 TCGv addr = gen_get_zaddr(); 1906 1907 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 1908 gen_data_load(ctx, Rd, addr); 1909 1910 tcg_temp_free_i32(addr); 1911 1912 return true; 1913 } 1914 1915 /* 1916 * Stores one byte from a Register to the data space. For parts with SRAM, 1917 * the data space consists of the Register File, I/O memory and internal SRAM 1918 * (and external SRAM if applicable). For parts without SRAM, the data space 1919 * consists of the Register File only. The EEPROM has a separate address space. 1920 * A 16-bit address must be supplied. Memory access is limited to the current 1921 * data segment of 64KB. The STS instruction uses the RAMPD Register to access 1922 * memory above 64KB. To access another data segment in devices with more than 1923 * 64KB data space, the RAMPD in register in the I/O area has to be changed. 1924 * This instruction is not available in all devices. Refer to the device 1925 * specific instruction set summary. 1926 */ 1927 static bool trans_STS(DisasContext *ctx, arg_STS *a) 1928 { 1929 TCGv Rd = cpu_r[a->rd]; 1930 TCGv addr = tcg_temp_new_i32(); 1931 TCGv H = cpu_rampD; 1932 a->imm = next_word(ctx); 1933 1934 tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ 1935 tcg_gen_shli_tl(addr, addr, 16); 1936 tcg_gen_ori_tl(addr, addr, a->imm); 1937 gen_data_store(ctx, Rd, addr); 1938 1939 tcg_temp_free_i32(addr); 1940 1941 return true; 1942 } 1943 1944 /* 1945 * Stores one byte indirect from a register to data space. For parts with SRAM, 1946 * the data space consists of the Register File, I/O memory, and internal SRAM 1947 * (and external SRAM if applicable). For parts without SRAM, the data space 1948 * consists of the Register File only. The EEPROM has a separate address space. 1949 * 1950 * The data location is pointed to by the X (16 bits) Pointer Register in the 1951 * Register File. Memory access is limited to the current data segment of 64KB. 1952 * To access another data segment in devices with more than 64KB data space, the 1953 * RAMPX in register in the I/O area has to be changed. 1954 * 1955 * The X-pointer Register can either be left unchanged by the operation, or it 1956 * can be post-incremented or pre-decremented. These features are especially 1957 * suited for accessing arrays, tables, and Stack Pointer usage of the 1958 * X-pointer Register. Note that only the low byte of the X-pointer is updated 1959 * in devices with no more than 256 bytes data space. For such devices, the high 1960 * byte of the pointer is not used by this instruction and can be used for other 1961 * purposes. The RAMPX Register in the I/O area is updated in parts with more 1962 * than 64KB data space or more than 64KB Program memory, and the increment / 1963 * decrement is added to the entire 24-bit address on such devices. 1964 */ 1965 static bool trans_STX1(DisasContext *ctx, arg_STX1 *a) 1966 { 1967 TCGv Rd = cpu_r[a->rr]; 1968 TCGv addr = gen_get_xaddr(); 1969 1970 gen_data_store(ctx, Rd, addr); 1971 1972 tcg_temp_free_i32(addr); 1973 1974 return true; 1975 } 1976 1977 static bool trans_STX2(DisasContext *ctx, arg_STX2 *a) 1978 { 1979 TCGv Rd = cpu_r[a->rr]; 1980 TCGv addr = gen_get_xaddr(); 1981 1982 gen_data_store(ctx, Rd, addr); 1983 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 1984 gen_set_xaddr(addr); 1985 1986 tcg_temp_free_i32(addr); 1987 1988 return true; 1989 } 1990 1991 static bool trans_STX3(DisasContext *ctx, arg_STX3 *a) 1992 { 1993 TCGv Rd = cpu_r[a->rr]; 1994 TCGv addr = gen_get_xaddr(); 1995 1996 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 1997 gen_data_store(ctx, Rd, addr); 1998 gen_set_xaddr(addr); 1999 2000 tcg_temp_free_i32(addr); 2001 2002 return true; 2003 } 2004 2005 /* 2006 * Stores one byte indirect with or without displacement from a register to data 2007 * space. For parts with SRAM, the data space consists of the Register File, I/O 2008 * memory, and internal SRAM (and external SRAM if applicable). For parts 2009 * without SRAM, the data space consists of the Register File only. The EEPROM 2010 * has a separate address space. 2011 * 2012 * The data location is pointed to by the Y (16 bits) Pointer Register in the 2013 * Register File. Memory access is limited to the current data segment of 64KB. 2014 * To access another data segment in devices with more than 64KB data space, the 2015 * RAMPY in register in the I/O area has to be changed. 2016 * 2017 * The Y-pointer Register can either be left unchanged by the operation, or it 2018 * can be post-incremented or pre-decremented. These features are especially 2019 * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer 2020 * Register. Note that only the low byte of the Y-pointer is updated in devices 2021 * with no more than 256 bytes data space. For such devices, the high byte of 2022 * the pointer is not used by this instruction and can be used for other 2023 * purposes. The RAMPY Register in the I/O area is updated in parts with more 2024 * than 64KB data space or more than 64KB Program memory, and the increment / 2025 * decrement / displacement is added to the entire 24-bit address on such 2026 * devices. 2027 */ 2028 static bool trans_STY2(DisasContext *ctx, arg_STY2 *a) 2029 { 2030 TCGv Rd = cpu_r[a->rd]; 2031 TCGv addr = gen_get_yaddr(); 2032 2033 gen_data_store(ctx, Rd, addr); 2034 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2035 gen_set_yaddr(addr); 2036 2037 tcg_temp_free_i32(addr); 2038 2039 return true; 2040 } 2041 2042 static bool trans_STY3(DisasContext *ctx, arg_STY3 *a) 2043 { 2044 TCGv Rd = cpu_r[a->rd]; 2045 TCGv addr = gen_get_yaddr(); 2046 2047 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 2048 gen_data_store(ctx, Rd, addr); 2049 gen_set_yaddr(addr); 2050 2051 tcg_temp_free_i32(addr); 2052 2053 return true; 2054 } 2055 2056 static bool trans_STDY(DisasContext *ctx, arg_STDY *a) 2057 { 2058 TCGv Rd = cpu_r[a->rd]; 2059 TCGv addr = gen_get_yaddr(); 2060 2061 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 2062 gen_data_store(ctx, Rd, addr); 2063 2064 tcg_temp_free_i32(addr); 2065 2066 return true; 2067 } 2068 2069 /* 2070 * Stores one byte indirect with or without displacement from a register to data 2071 * space. For parts with SRAM, the data space consists of the Register File, I/O 2072 * memory, and internal SRAM (and external SRAM if applicable). For parts 2073 * without SRAM, the data space consists of the Register File only. The EEPROM 2074 * has a separate address space. 2075 * 2076 * The data location is pointed to by the Y (16 bits) Pointer Register in the 2077 * Register File. Memory access is limited to the current data segment of 64KB. 2078 * To access another data segment in devices with more than 64KB data space, the 2079 * RAMPY in register in the I/O area has to be changed. 2080 * 2081 * The Y-pointer Register can either be left unchanged by the operation, or it 2082 * can be post-incremented or pre-decremented. These features are especially 2083 * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer 2084 * Register. Note that only the low byte of the Y-pointer is updated in devices 2085 * with no more than 256 bytes data space. For such devices, the high byte of 2086 * the pointer is not used by this instruction and can be used for other 2087 * purposes. The RAMPY Register in the I/O area is updated in parts with more 2088 * than 64KB data space or more than 64KB Program memory, and the increment / 2089 * decrement / displacement is added to the entire 24-bit address on such 2090 * devices. 2091 */ 2092 static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a) 2093 { 2094 TCGv Rd = cpu_r[a->rd]; 2095 TCGv addr = gen_get_zaddr(); 2096 2097 gen_data_store(ctx, Rd, addr); 2098 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2099 2100 gen_set_zaddr(addr); 2101 2102 tcg_temp_free_i32(addr); 2103 2104 return true; 2105 } 2106 2107 static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a) 2108 { 2109 TCGv Rd = cpu_r[a->rd]; 2110 TCGv addr = gen_get_zaddr(); 2111 2112 tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 2113 gen_data_store(ctx, Rd, addr); 2114 2115 gen_set_zaddr(addr); 2116 2117 tcg_temp_free_i32(addr); 2118 2119 return true; 2120 } 2121 2122 static bool trans_STDZ(DisasContext *ctx, arg_STDZ *a) 2123 { 2124 TCGv Rd = cpu_r[a->rd]; 2125 TCGv addr = gen_get_zaddr(); 2126 2127 tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 2128 gen_data_store(ctx, Rd, addr); 2129 2130 tcg_temp_free_i32(addr); 2131 2132 return true; 2133 } 2134 2135 /* 2136 * Loads one byte pointed to by the Z-register into the destination 2137 * register Rd. This instruction features a 100% space effective constant 2138 * initialization or constant data fetch. The Program memory is organized in 2139 * 16-bit words while the Z-pointer is a byte address. Thus, the least 2140 * significant bit of the Z-pointer selects either low byte (ZLSB = 0) or high 2141 * byte (ZLSB = 1). This instruction can address the first 64KB (32K words) of 2142 * Program memory. The Zpointer Register can either be left unchanged by the 2143 * operation, or it can be incremented. The incrementation does not apply to 2144 * the RAMPZ Register. 2145 * 2146 * Devices with Self-Programming capability can use the LPM instruction to read 2147 * the Fuse and Lock bit values. 2148 */ 2149 static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a) 2150 { 2151 if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) { 2152 return true; 2153 } 2154 2155 TCGv Rd = cpu_r[0]; 2156 TCGv addr = tcg_temp_new_i32(); 2157 TCGv H = cpu_r[31]; 2158 TCGv L = cpu_r[30]; 2159 2160 tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 2161 tcg_gen_or_tl(addr, addr, L); 2162 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2163 2164 tcg_temp_free_i32(addr); 2165 2166 return true; 2167 } 2168 2169 static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a) 2170 { 2171 if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) { 2172 return true; 2173 } 2174 2175 TCGv Rd = cpu_r[a->rd]; 2176 TCGv addr = tcg_temp_new_i32(); 2177 TCGv H = cpu_r[31]; 2178 TCGv L = cpu_r[30]; 2179 2180 tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 2181 tcg_gen_or_tl(addr, addr, L); 2182 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2183 2184 tcg_temp_free_i32(addr); 2185 2186 return true; 2187 } 2188 2189 static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a) 2190 { 2191 if (!avr_have_feature(ctx, AVR_FEATURE_LPMX)) { 2192 return true; 2193 } 2194 2195 TCGv Rd = cpu_r[a->rd]; 2196 TCGv addr = tcg_temp_new_i32(); 2197 TCGv H = cpu_r[31]; 2198 TCGv L = cpu_r[30]; 2199 2200 tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 2201 tcg_gen_or_tl(addr, addr, L); 2202 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2203 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2204 tcg_gen_andi_tl(L, addr, 0xff); 2205 tcg_gen_shri_tl(addr, addr, 8); 2206 tcg_gen_andi_tl(H, addr, 0xff); 2207 2208 tcg_temp_free_i32(addr); 2209 2210 return true; 2211 } 2212 2213 /* 2214 * Loads one byte pointed to by the Z-register and the RAMPZ Register in 2215 * the I/O space, and places this byte in the destination register Rd. This 2216 * instruction features a 100% space effective constant initialization or 2217 * constant data fetch. The Program memory is organized in 16-bit words while 2218 * the Z-pointer is a byte address. Thus, the least significant bit of the 2219 * Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This 2220 * instruction can address the entire Program memory space. The Z-pointer 2221 * Register can either be left unchanged by the operation, or it can be 2222 * incremented. The incrementation applies to the entire 24-bit concatenation 2223 * of the RAMPZ and Z-pointer Registers. 2224 * 2225 * Devices with Self-Programming capability can use the ELPM instruction to 2226 * read the Fuse and Lock bit value. 2227 */ 2228 static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a) 2229 { 2230 if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) { 2231 return true; 2232 } 2233 2234 TCGv Rd = cpu_r[0]; 2235 TCGv addr = gen_get_zaddr(); 2236 2237 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2238 2239 tcg_temp_free_i32(addr); 2240 2241 return true; 2242 } 2243 2244 static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a) 2245 { 2246 if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) { 2247 return true; 2248 } 2249 2250 TCGv Rd = cpu_r[a->rd]; 2251 TCGv addr = gen_get_zaddr(); 2252 2253 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2254 2255 tcg_temp_free_i32(addr); 2256 2257 return true; 2258 } 2259 2260 static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a) 2261 { 2262 if (!avr_have_feature(ctx, AVR_FEATURE_ELPMX)) { 2263 return true; 2264 } 2265 2266 TCGv Rd = cpu_r[a->rd]; 2267 TCGv addr = gen_get_zaddr(); 2268 2269 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ 2270 tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 2271 gen_set_zaddr(addr); 2272 2273 tcg_temp_free_i32(addr); 2274 2275 return true; 2276 } 2277 2278 /* 2279 * SPM can be used to erase a page in the Program memory, to write a page 2280 * in the Program memory (that is already erased), and to set Boot Loader Lock 2281 * bits. In some devices, the Program memory can be written one word at a time, 2282 * in other devices an entire page can be programmed simultaneously after first 2283 * filling a temporary page buffer. In all cases, the Program memory must be 2284 * erased one page at a time. When erasing the Program memory, the RAMPZ and 2285 * Z-register are used as page address. When writing the Program memory, the 2286 * RAMPZ and Z-register are used as page or word address, and the R1:R0 2287 * register pair is used as data(1). When setting the Boot Loader Lock bits, 2288 * the R1:R0 register pair is used as data. Refer to the device documentation 2289 * for detailed description of SPM usage. This instruction can address the 2290 * entire Program memory. 2291 * 2292 * The SPM instruction is not available in all devices. Refer to the device 2293 * specific instruction set summary. 2294 * 2295 * Note: 1. R1 determines the instruction high byte, and R0 determines the 2296 * instruction low byte. 2297 */ 2298 static bool trans_SPM(DisasContext *ctx, arg_SPM *a) 2299 { 2300 /* TODO */ 2301 if (!avr_have_feature(ctx, AVR_FEATURE_SPM)) { 2302 return true; 2303 } 2304 2305 return true; 2306 } 2307 2308 static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) 2309 { 2310 /* TODO */ 2311 if (!avr_have_feature(ctx, AVR_FEATURE_SPMX)) { 2312 return true; 2313 } 2314 2315 return true; 2316 } 2317 2318 /* 2319 * Loads data from the I/O Space (Ports, Timers, Configuration Registers, 2320 * etc.) into register Rd in the Register File. 2321 */ 2322 static bool trans_IN(DisasContext *ctx, arg_IN *a) 2323 { 2324 TCGv Rd = cpu_r[a->rd]; 2325 TCGv port = tcg_const_i32(a->imm); 2326 2327 gen_helper_inb(Rd, cpu_env, port); 2328 2329 tcg_temp_free_i32(port); 2330 2331 return true; 2332 } 2333 2334 /* 2335 * Stores data from register Rr in the Register File to I/O Space (Ports, 2336 * Timers, Configuration Registers, etc.). 2337 */ 2338 static bool trans_OUT(DisasContext *ctx, arg_OUT *a) 2339 { 2340 TCGv Rd = cpu_r[a->rd]; 2341 TCGv port = tcg_const_i32(a->imm); 2342 2343 gen_helper_outb(cpu_env, port, Rd); 2344 2345 tcg_temp_free_i32(port); 2346 2347 return true; 2348 } 2349 2350 /* 2351 * This instruction stores the contents of register Rr on the STACK. The 2352 * Stack Pointer is post-decremented by 1 after the PUSH. This instruction is 2353 * not available in all devices. Refer to the device specific instruction set 2354 * summary. 2355 */ 2356 static bool trans_PUSH(DisasContext *ctx, arg_PUSH *a) 2357 { 2358 TCGv Rd = cpu_r[a->rd]; 2359 2360 gen_data_store(ctx, Rd, cpu_sp); 2361 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 2362 2363 return true; 2364 } 2365 2366 /* 2367 * This instruction loads register Rd with a byte from the STACK. The Stack 2368 * Pointer is pre-incremented by 1 before the POP. This instruction is not 2369 * available in all devices. Refer to the device specific instruction set 2370 * summary. 2371 */ 2372 static bool trans_POP(DisasContext *ctx, arg_POP *a) 2373 { 2374 /* 2375 * Using a temp to work around some strange behaviour: 2376 * tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 2377 * gen_data_load(ctx, Rd, cpu_sp); 2378 * seems to cause the add to happen twice. 2379 * This doesn't happen if either the add or the load is removed. 2380 */ 2381 TCGv t1 = tcg_temp_new_i32(); 2382 TCGv Rd = cpu_r[a->rd]; 2383 2384 tcg_gen_addi_tl(t1, cpu_sp, 1); 2385 gen_data_load(ctx, Rd, t1); 2386 tcg_gen_mov_tl(cpu_sp, t1); 2387 2388 return true; 2389 } 2390 2391 /* 2392 * Exchanges one byte indirect between register and data space. The data 2393 * location is pointed to by the Z (16 bits) Pointer Register in the Register 2394 * File. Memory access is limited to the current data segment of 64KB. To 2395 * access another data segment in devices with more than 64KB data space, the 2396 * RAMPZ in register in the I/O area has to be changed. 2397 * 2398 * The Z-pointer Register is left unchanged by the operation. This instruction 2399 * is especially suited for writing/reading status bits stored in SRAM. 2400 */ 2401 static bool trans_XCH(DisasContext *ctx, arg_XCH *a) 2402 { 2403 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2404 return true; 2405 } 2406 2407 TCGv Rd = cpu_r[a->rd]; 2408 TCGv t0 = tcg_temp_new_i32(); 2409 TCGv addr = gen_get_zaddr(); 2410 2411 gen_data_load(ctx, t0, addr); 2412 gen_data_store(ctx, Rd, addr); 2413 tcg_gen_mov_tl(Rd, t0); 2414 2415 tcg_temp_free_i32(t0); 2416 tcg_temp_free_i32(addr); 2417 2418 return true; 2419 } 2420 2421 /* 2422 * Load one byte indirect from data space to register and set bits in data 2423 * space specified by the register. The instruction can only be used towards 2424 * internal SRAM. The data location is pointed to by the Z (16 bits) Pointer 2425 * Register in the Register File. Memory access is limited to the current data 2426 * segment of 64KB. To access another data segment in devices with more than 2427 * 64KB data space, the RAMPZ in register in the I/O area has to be changed. 2428 * 2429 * The Z-pointer Register is left unchanged by the operation. This instruction 2430 * is especially suited for setting status bits stored in SRAM. 2431 */ 2432 static bool trans_LAS(DisasContext *ctx, arg_LAS *a) 2433 { 2434 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2435 return true; 2436 } 2437 2438 TCGv Rr = cpu_r[a->rd]; 2439 TCGv addr = gen_get_zaddr(); 2440 TCGv t0 = tcg_temp_new_i32(); 2441 TCGv t1 = tcg_temp_new_i32(); 2442 2443 gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 2444 tcg_gen_or_tl(t1, t0, Rr); 2445 tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */ 2446 gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 2447 2448 tcg_temp_free_i32(t1); 2449 tcg_temp_free_i32(t0); 2450 tcg_temp_free_i32(addr); 2451 2452 return true; 2453 } 2454 2455 /* 2456 * Load one byte indirect from data space to register and stores and clear 2457 * the bits in data space specified by the register. The instruction can 2458 * only be used towards internal SRAM. The data location is pointed to by 2459 * the Z (16 bits) Pointer Register in the Register File. Memory access is 2460 * limited to the current data segment of 64KB. To access another data 2461 * segment in devices with more than 64KB data space, the RAMPZ in register 2462 * in the I/O area has to be changed. 2463 * 2464 * The Z-pointer Register is left unchanged by the operation. This instruction 2465 * is especially suited for clearing status bits stored in SRAM. 2466 */ 2467 static bool trans_LAC(DisasContext *ctx, arg_LAC *a) 2468 { 2469 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2470 return true; 2471 } 2472 2473 TCGv Rr = cpu_r[a->rd]; 2474 TCGv addr = gen_get_zaddr(); 2475 TCGv t0 = tcg_temp_new_i32(); 2476 TCGv t1 = tcg_temp_new_i32(); 2477 2478 gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 2479 tcg_gen_andc_tl(t1, t0, Rr); /* t1 = t0 & (0xff - Rr) = t0 & ~Rr */ 2480 tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */ 2481 gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 2482 2483 tcg_temp_free_i32(t1); 2484 tcg_temp_free_i32(t0); 2485 tcg_temp_free_i32(addr); 2486 2487 return true; 2488 } 2489 2490 2491 /* 2492 * Load one byte indirect from data space to register and toggles bits in 2493 * the data space specified by the register. The instruction can only be used 2494 * towards SRAM. The data location is pointed to by the Z (16 bits) Pointer 2495 * Register in the Register File. Memory access is limited to the current data 2496 * segment of 64KB. To access another data segment in devices with more than 2497 * 64KB data space, the RAMPZ in register in the I/O area has to be changed. 2498 * 2499 * The Z-pointer Register is left unchanged by the operation. This instruction 2500 * is especially suited for changing status bits stored in SRAM. 2501 */ 2502 static bool trans_LAT(DisasContext *ctx, arg_LAT *a) 2503 { 2504 if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 2505 return true; 2506 } 2507 2508 TCGv Rd = cpu_r[a->rd]; 2509 TCGv addr = gen_get_zaddr(); 2510 TCGv t0 = tcg_temp_new_i32(); 2511 TCGv t1 = tcg_temp_new_i32(); 2512 2513 gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 2514 tcg_gen_xor_tl(t1, t0, Rd); 2515 tcg_gen_mov_tl(Rd, t0); /* Rd = t0 */ 2516 gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 2517 2518 tcg_temp_free_i32(t1); 2519 tcg_temp_free_i32(t0); 2520 tcg_temp_free_i32(addr); 2521 2522 return true; 2523 } 2524 2525 /* 2526 * Bit and Bit-test Instructions 2527 */ 2528 static void gen_rshift_ZNVSf(TCGv R) 2529 { 2530 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 2531 tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 2532 tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf); 2533 tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 2534 } 2535 2536 /* 2537 * Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is 2538 * loaded into the C Flag of the SREG. This operation effectively divides an 2539 * unsigned value by two. The C Flag can be used to round the result. 2540 */ 2541 static bool trans_LSR(DisasContext *ctx, arg_LSR *a) 2542 { 2543 TCGv Rd = cpu_r[a->rd]; 2544 2545 tcg_gen_andi_tl(cpu_Cf, Rd, 1); 2546 tcg_gen_shri_tl(Rd, Rd, 1); 2547 2548 /* update status register */ 2549 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, Rd, 0); /* Zf = Rd == 0 */ 2550 tcg_gen_movi_tl(cpu_Nf, 0); 2551 tcg_gen_mov_tl(cpu_Vf, cpu_Cf); 2552 tcg_gen_mov_tl(cpu_Sf, cpu_Vf); 2553 2554 return true; 2555 } 2556 2557 /* 2558 * Shifts all bits in Rd one place to the right. The C Flag is shifted into 2559 * bit 7 of Rd. Bit 0 is shifted into the C Flag. This operation, combined 2560 * with ASR, effectively divides multi-byte signed values by two. Combined with 2561 * LSR it effectively divides multi-byte unsigned values by two. The Carry Flag 2562 * can be used to round the result. 2563 */ 2564 static bool trans_ROR(DisasContext *ctx, arg_ROR *a) 2565 { 2566 TCGv Rd = cpu_r[a->rd]; 2567 TCGv t0 = tcg_temp_new_i32(); 2568 2569 tcg_gen_shli_tl(t0, cpu_Cf, 7); 2570 2571 /* update status register */ 2572 tcg_gen_andi_tl(cpu_Cf, Rd, 1); 2573 2574 /* update output register */ 2575 tcg_gen_shri_tl(Rd, Rd, 1); 2576 tcg_gen_or_tl(Rd, Rd, t0); 2577 2578 /* update status register */ 2579 gen_rshift_ZNVSf(Rd); 2580 2581 tcg_temp_free_i32(t0); 2582 2583 return true; 2584 } 2585 2586 /* 2587 * Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 2588 * is loaded into the C Flag of the SREG. This operation effectively divides a 2589 * signed value by two without changing its sign. The Carry Flag can be used to 2590 * round the result. 2591 */ 2592 static bool trans_ASR(DisasContext *ctx, arg_ASR *a) 2593 { 2594 TCGv Rd = cpu_r[a->rd]; 2595 TCGv t0 = tcg_temp_new_i32(); 2596 2597 /* update status register */ 2598 tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf = Rd(0) */ 2599 2600 /* update output register */ 2601 tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd = (Rd & 0x80) | (Rd >> 1) */ 2602 tcg_gen_shri_tl(Rd, Rd, 1); 2603 tcg_gen_or_tl(Rd, Rd, t0); 2604 2605 /* update status register */ 2606 gen_rshift_ZNVSf(Rd); 2607 2608 tcg_temp_free_i32(t0); 2609 2610 return true; 2611 } 2612 2613 /* 2614 * Swaps high and low nibbles in a register. 2615 */ 2616 static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a) 2617 { 2618 TCGv Rd = cpu_r[a->rd]; 2619 TCGv t0 = tcg_temp_new_i32(); 2620 TCGv t1 = tcg_temp_new_i32(); 2621 2622 tcg_gen_andi_tl(t0, Rd, 0x0f); 2623 tcg_gen_shli_tl(t0, t0, 4); 2624 tcg_gen_andi_tl(t1, Rd, 0xf0); 2625 tcg_gen_shri_tl(t1, t1, 4); 2626 tcg_gen_or_tl(Rd, t0, t1); 2627 2628 tcg_temp_free_i32(t1); 2629 tcg_temp_free_i32(t0); 2630 2631 return true; 2632 } 2633 2634 /* 2635 * Sets a specified bit in an I/O Register. This instruction operates on 2636 * the lower 32 I/O Registers -- addresses 0-31. 2637 */ 2638 static bool trans_SBI(DisasContext *ctx, arg_SBI *a) 2639 { 2640 TCGv data = tcg_temp_new_i32(); 2641 TCGv port = tcg_const_i32(a->reg); 2642 2643 gen_helper_inb(data, cpu_env, port); 2644 tcg_gen_ori_tl(data, data, 1 << a->bit); 2645 gen_helper_outb(cpu_env, port, data); 2646 2647 tcg_temp_free_i32(port); 2648 tcg_temp_free_i32(data); 2649 2650 return true; 2651 } 2652 2653 /* 2654 * Clears a specified bit in an I/O Register. This instruction operates on 2655 * the lower 32 I/O Registers -- addresses 0-31. 2656 */ 2657 static bool trans_CBI(DisasContext *ctx, arg_CBI *a) 2658 { 2659 TCGv data = tcg_temp_new_i32(); 2660 TCGv port = tcg_const_i32(a->reg); 2661 2662 gen_helper_inb(data, cpu_env, port); 2663 tcg_gen_andi_tl(data, data, ~(1 << a->bit)); 2664 gen_helper_outb(cpu_env, port, data); 2665 2666 tcg_temp_free_i32(data); 2667 tcg_temp_free_i32(port); 2668 2669 return true; 2670 } 2671 2672 /* 2673 * Stores bit b from Rd to the T Flag in SREG (Status Register). 2674 */ 2675 static bool trans_BST(DisasContext *ctx, arg_BST *a) 2676 { 2677 TCGv Rd = cpu_r[a->rd]; 2678 2679 tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit); 2680 tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit); 2681 2682 return true; 2683 } 2684 2685 /* 2686 * Copies the T Flag in the SREG (Status Register) to bit b in register Rd. 2687 */ 2688 static bool trans_BLD(DisasContext *ctx, arg_BLD *a) 2689 { 2690 TCGv Rd = cpu_r[a->rd]; 2691 TCGv t1 = tcg_temp_new_i32(); 2692 2693 tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear bit */ 2694 tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */ 2695 tcg_gen_or_tl(Rd, Rd, t1); 2696 2697 tcg_temp_free_i32(t1); 2698 2699 return true; 2700 } 2701 2702 /* 2703 * Sets a single Flag or bit in SREG. 2704 */ 2705 static bool trans_BSET(DisasContext *ctx, arg_BSET *a) 2706 { 2707 switch (a->bit) { 2708 case 0x00: 2709 tcg_gen_movi_tl(cpu_Cf, 0x01); 2710 break; 2711 case 0x01: 2712 tcg_gen_movi_tl(cpu_Zf, 0x01); 2713 break; 2714 case 0x02: 2715 tcg_gen_movi_tl(cpu_Nf, 0x01); 2716 break; 2717 case 0x03: 2718 tcg_gen_movi_tl(cpu_Vf, 0x01); 2719 break; 2720 case 0x04: 2721 tcg_gen_movi_tl(cpu_Sf, 0x01); 2722 break; 2723 case 0x05: 2724 tcg_gen_movi_tl(cpu_Hf, 0x01); 2725 break; 2726 case 0x06: 2727 tcg_gen_movi_tl(cpu_Tf, 0x01); 2728 break; 2729 case 0x07: 2730 tcg_gen_movi_tl(cpu_If, 0x01); 2731 break; 2732 } 2733 2734 return true; 2735 } 2736 2737 /* 2738 * Clears a single Flag in SREG. 2739 */ 2740 static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a) 2741 { 2742 switch (a->bit) { 2743 case 0x00: 2744 tcg_gen_movi_tl(cpu_Cf, 0x00); 2745 break; 2746 case 0x01: 2747 tcg_gen_movi_tl(cpu_Zf, 0x00); 2748 break; 2749 case 0x02: 2750 tcg_gen_movi_tl(cpu_Nf, 0x00); 2751 break; 2752 case 0x03: 2753 tcg_gen_movi_tl(cpu_Vf, 0x00); 2754 break; 2755 case 0x04: 2756 tcg_gen_movi_tl(cpu_Sf, 0x00); 2757 break; 2758 case 0x05: 2759 tcg_gen_movi_tl(cpu_Hf, 0x00); 2760 break; 2761 case 0x06: 2762 tcg_gen_movi_tl(cpu_Tf, 0x00); 2763 break; 2764 case 0x07: 2765 tcg_gen_movi_tl(cpu_If, 0x00); 2766 break; 2767 } 2768 2769 return true; 2770 } 2771 2772 /* 2773 * MCU Control Instructions 2774 */ 2775 2776 /* 2777 * The BREAK instruction is used by the On-chip Debug system, and is 2778 * normally not used in the application software. When the BREAK instruction is 2779 * executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip 2780 * Debugger access to internal resources. If any Lock bits are set, or either 2781 * the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK 2782 * instruction as a NOP and will not enter the Stopped mode. This instruction 2783 * is not available in all devices. Refer to the device specific instruction 2784 * set summary. 2785 */ 2786 static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a) 2787 { 2788 if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) { 2789 return true; 2790 } 2791 2792 #ifdef BREAKPOINT_ON_BREAK 2793 tcg_gen_movi_tl(cpu_pc, ctx->npc - 1); 2794 gen_helper_debug(cpu_env); 2795 ctx->base.is_jmp = DISAS_EXIT; 2796 #else 2797 /* NOP */ 2798 #endif 2799 2800 return true; 2801 } 2802 2803 /* 2804 * This instruction performs a single cycle No Operation. 2805 */ 2806 static bool trans_NOP(DisasContext *ctx, arg_NOP *a) 2807 { 2808 2809 /* NOP */ 2810 2811 return true; 2812 } 2813 2814 /* 2815 * This instruction sets the circuit in sleep mode defined by the MCU 2816 * Control Register. 2817 */ 2818 static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a) 2819 { 2820 gen_helper_sleep(cpu_env); 2821 ctx->base.is_jmp = DISAS_NORETURN; 2822 return true; 2823 } 2824 2825 /* 2826 * This instruction resets the Watchdog Timer. This instruction must be 2827 * executed within a limited time given by the WD prescaler. See the Watchdog 2828 * Timer hardware specification. 2829 */ 2830 static bool trans_WDR(DisasContext *ctx, arg_WDR *a) 2831 { 2832 gen_helper_wdr(cpu_env); 2833 2834 return true; 2835 } 2836 2837 /* 2838 * Core translation mechanism functions: 2839 * 2840 * - translate() 2841 * - canonicalize_skip() 2842 * - gen_intermediate_code() 2843 * - restore_state_to_opc() 2844 * 2845 */ 2846 static void translate(DisasContext *ctx) 2847 { 2848 uint32_t opcode = next_word(ctx); 2849 2850 if (!decode_insn(ctx, opcode)) { 2851 gen_helper_unsupported(cpu_env); 2852 ctx->base.is_jmp = DISAS_NORETURN; 2853 } 2854 } 2855 2856 /* Standardize the cpu_skip condition to NE. */ 2857 static bool canonicalize_skip(DisasContext *ctx) 2858 { 2859 switch (ctx->skip_cond) { 2860 case TCG_COND_NEVER: 2861 /* Normal case: cpu_skip is known to be false. */ 2862 return false; 2863 2864 case TCG_COND_ALWAYS: 2865 /* 2866 * Breakpoint case: cpu_skip is known to be true, via TB_FLAGS_SKIP. 2867 * The breakpoint is on the instruction being skipped, at the start 2868 * of the TranslationBlock. No need to update. 2869 */ 2870 return false; 2871 2872 case TCG_COND_NE: 2873 if (ctx->skip_var1 == NULL) { 2874 tcg_gen_mov_tl(cpu_skip, ctx->skip_var0); 2875 } else { 2876 tcg_gen_xor_tl(cpu_skip, ctx->skip_var0, ctx->skip_var1); 2877 ctx->skip_var1 = NULL; 2878 } 2879 break; 2880 2881 default: 2882 /* Convert to a NE condition vs 0. */ 2883 if (ctx->skip_var1 == NULL) { 2884 tcg_gen_setcondi_tl(ctx->skip_cond, cpu_skip, ctx->skip_var0, 0); 2885 } else { 2886 tcg_gen_setcond_tl(ctx->skip_cond, cpu_skip, 2887 ctx->skip_var0, ctx->skip_var1); 2888 ctx->skip_var1 = NULL; 2889 } 2890 ctx->skip_cond = TCG_COND_NE; 2891 break; 2892 } 2893 if (ctx->free_skip_var0) { 2894 tcg_temp_free(ctx->skip_var0); 2895 ctx->free_skip_var0 = false; 2896 } 2897 ctx->skip_var0 = cpu_skip; 2898 return true; 2899 } 2900 2901 static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 2902 { 2903 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2904 CPUAVRState *env = cs->env_ptr; 2905 uint32_t tb_flags = ctx->base.tb->flags; 2906 2907 ctx->cs = cs; 2908 ctx->env = env; 2909 ctx->npc = ctx->base.pc_first / 2; 2910 2911 ctx->skip_cond = TCG_COND_NEVER; 2912 if (tb_flags & TB_FLAGS_SKIP) { 2913 ctx->skip_cond = TCG_COND_ALWAYS; 2914 ctx->skip_var0 = cpu_skip; 2915 } 2916 2917 if (tb_flags & TB_FLAGS_FULL_ACCESS) { 2918 /* 2919 * This flag is set by ST/LD instruction we will regenerate it ONLY 2920 * with mem/cpu memory access instead of mem access 2921 */ 2922 ctx->base.max_insns = 1; 2923 } 2924 } 2925 2926 static void avr_tr_tb_start(DisasContextBase *db, CPUState *cs) 2927 { 2928 } 2929 2930 static void avr_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 2931 { 2932 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2933 2934 tcg_gen_insn_start(ctx->npc); 2935 } 2936 2937 static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 2938 { 2939 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2940 TCGLabel *skip_label = NULL; 2941 2942 /* Conditionally skip the next instruction, if indicated. */ 2943 if (ctx->skip_cond != TCG_COND_NEVER) { 2944 skip_label = gen_new_label(); 2945 if (ctx->skip_var0 == cpu_skip) { 2946 /* 2947 * Copy cpu_skip so that we may zero it before the branch. 2948 * This ensures that cpu_skip is non-zero after the label 2949 * if and only if the skipped insn itself sets a skip. 2950 */ 2951 ctx->free_skip_var0 = true; 2952 ctx->skip_var0 = tcg_temp_new(); 2953 tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); 2954 tcg_gen_movi_tl(cpu_skip, 0); 2955 } 2956 if (ctx->skip_var1 == NULL) { 2957 tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0, 0, skip_label); 2958 } else { 2959 tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0, 2960 ctx->skip_var1, skip_label); 2961 ctx->skip_var1 = NULL; 2962 } 2963 if (ctx->free_skip_var0) { 2964 tcg_temp_free(ctx->skip_var0); 2965 ctx->free_skip_var0 = false; 2966 } 2967 ctx->skip_cond = TCG_COND_NEVER; 2968 ctx->skip_var0 = NULL; 2969 } 2970 2971 translate(ctx); 2972 2973 ctx->base.pc_next = ctx->npc * 2; 2974 2975 if (skip_label) { 2976 canonicalize_skip(ctx); 2977 gen_set_label(skip_label); 2978 if (ctx->base.is_jmp == DISAS_NORETURN) { 2979 ctx->base.is_jmp = DISAS_CHAIN; 2980 } 2981 } 2982 2983 if (ctx->base.is_jmp == DISAS_NEXT) { 2984 target_ulong page_first = ctx->base.pc_first & TARGET_PAGE_MASK; 2985 2986 if ((ctx->base.pc_next - page_first) >= TARGET_PAGE_SIZE - 4) { 2987 ctx->base.is_jmp = DISAS_TOO_MANY; 2988 } 2989 } 2990 } 2991 2992 static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 2993 { 2994 DisasContext *ctx = container_of(dcbase, DisasContext, base); 2995 bool nonconst_skip = canonicalize_skip(ctx); 2996 2997 switch (ctx->base.is_jmp) { 2998 case DISAS_NORETURN: 2999 assert(!nonconst_skip); 3000 break; 3001 case DISAS_NEXT: 3002 case DISAS_TOO_MANY: 3003 case DISAS_CHAIN: 3004 if (!nonconst_skip) { 3005 /* Note gen_goto_tb checks singlestep. */ 3006 gen_goto_tb(ctx, 1, ctx->npc); 3007 break; 3008 } 3009 tcg_gen_movi_tl(cpu_pc, ctx->npc); 3010 /* fall through */ 3011 case DISAS_LOOKUP: 3012 if (!ctx->base.singlestep_enabled) { 3013 tcg_gen_lookup_and_goto_ptr(); 3014 break; 3015 } 3016 /* fall through */ 3017 case DISAS_EXIT: 3018 if (ctx->base.singlestep_enabled) { 3019 gen_helper_debug(cpu_env); 3020 } else { 3021 tcg_gen_exit_tb(NULL, 0); 3022 } 3023 break; 3024 default: 3025 g_assert_not_reached(); 3026 } 3027 } 3028 3029 static void avr_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 3030 { 3031 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 3032 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 3033 } 3034 3035 static const TranslatorOps avr_tr_ops = { 3036 .init_disas_context = avr_tr_init_disas_context, 3037 .tb_start = avr_tr_tb_start, 3038 .insn_start = avr_tr_insn_start, 3039 .translate_insn = avr_tr_translate_insn, 3040 .tb_stop = avr_tr_tb_stop, 3041 .disas_log = avr_tr_disas_log, 3042 }; 3043 3044 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 3045 { 3046 DisasContext dc = { }; 3047 translator_loop(&avr_tr_ops, &dc.base, cs, tb, max_insns); 3048 } 3049 3050 void restore_state_to_opc(CPUAVRState *env, TranslationBlock *tb, 3051 target_ulong *data) 3052 { 3053 env->pc_w = data[0]; 3054 } 3055