1e03feba0SMichael Rolnik /* 2e03feba0SMichael Rolnik * QEMU AVR CPU 3e03feba0SMichael Rolnik * 4e03feba0SMichael Rolnik * Copyright (c) 2019-2020 Michael Rolnik 5e03feba0SMichael Rolnik * 6e03feba0SMichael Rolnik * This library is free software; you can redistribute it and/or 7e03feba0SMichael Rolnik * modify it under the terms of the GNU Lesser General Public 8e03feba0SMichael Rolnik * License as published by the Free Software Foundation; either 9e03feba0SMichael Rolnik * version 2.1 of the License, or (at your option) any later version. 10e03feba0SMichael Rolnik * 11e03feba0SMichael Rolnik * This library is distributed in the hope that it will be useful, 12e03feba0SMichael Rolnik * but WITHOUT ANY WARRANTY; without even the implied warranty of 13e03feba0SMichael Rolnik * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14e03feba0SMichael Rolnik * Lesser General Public License for more details. 15e03feba0SMichael Rolnik * 16e03feba0SMichael Rolnik * You should have received a copy of the GNU Lesser General Public 17e03feba0SMichael Rolnik * License along with this library; if not, see 18e03feba0SMichael Rolnik * <http://www.gnu.org/licenses/lgpl-2.1.html> 19e03feba0SMichael Rolnik */ 20e03feba0SMichael Rolnik 21e03feba0SMichael Rolnik #include "qemu/osdep.h" 22e03feba0SMichael Rolnik #include "qemu/qemu-print.h" 23e03feba0SMichael Rolnik #include "tcg/tcg.h" 24e03feba0SMichael Rolnik #include "cpu.h" 25e03feba0SMichael Rolnik #include "exec/exec-all.h" 26e03feba0SMichael Rolnik #include "tcg/tcg-op.h" 27e03feba0SMichael Rolnik #include "exec/cpu_ldst.h" 28e03feba0SMichael Rolnik #include "exec/helper-proto.h" 29e03feba0SMichael Rolnik #include "exec/helper-gen.h" 30e03feba0SMichael Rolnik #include "exec/log.h" 31e03feba0SMichael Rolnik #include "exec/translator.h" 32e03feba0SMichael Rolnik #include "exec/gen-icount.h" 33e03feba0SMichael Rolnik 34e03feba0SMichael Rolnik /* 35e03feba0SMichael Rolnik * Define if you want a BREAK instruction translated to a breakpoint 36e03feba0SMichael Rolnik * Active debugging connection is assumed 37e03feba0SMichael Rolnik * This is for 38e03feba0SMichael Rolnik * https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests 39e03feba0SMichael Rolnik * tests 40e03feba0SMichael Rolnik */ 41e03feba0SMichael Rolnik #undef BREAKPOINT_ON_BREAK 42e03feba0SMichael Rolnik 43e03feba0SMichael Rolnik static TCGv cpu_pc; 44e03feba0SMichael Rolnik 45e03feba0SMichael Rolnik static TCGv cpu_Cf; 46e03feba0SMichael Rolnik static TCGv cpu_Zf; 47e03feba0SMichael Rolnik static TCGv cpu_Nf; 48e03feba0SMichael Rolnik static TCGv cpu_Vf; 49e03feba0SMichael Rolnik static TCGv cpu_Sf; 50e03feba0SMichael Rolnik static TCGv cpu_Hf; 51e03feba0SMichael Rolnik static TCGv cpu_Tf; 52e03feba0SMichael Rolnik static TCGv cpu_If; 53e03feba0SMichael Rolnik 54e03feba0SMichael Rolnik static TCGv cpu_rampD; 55e03feba0SMichael Rolnik static TCGv cpu_rampX; 56e03feba0SMichael Rolnik static TCGv cpu_rampY; 57e03feba0SMichael Rolnik static TCGv cpu_rampZ; 58e03feba0SMichael Rolnik 59e03feba0SMichael Rolnik static TCGv cpu_r[NUMBER_OF_CPU_REGISTERS]; 60e03feba0SMichael Rolnik static TCGv cpu_eind; 61e03feba0SMichael Rolnik static TCGv cpu_sp; 62e03feba0SMichael Rolnik 63e03feba0SMichael Rolnik static TCGv cpu_skip; 64e03feba0SMichael Rolnik 65e03feba0SMichael Rolnik static const char reg_names[NUMBER_OF_CPU_REGISTERS][8] = { 66e03feba0SMichael Rolnik "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 67e03feba0SMichael Rolnik "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 68e03feba0SMichael Rolnik "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 69e03feba0SMichael Rolnik "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 70e03feba0SMichael Rolnik }; 71e03feba0SMichael Rolnik #define REG(x) (cpu_r[x]) 72e03feba0SMichael Rolnik 73eba6814aSStefan Weil #define DISAS_EXIT DISAS_TARGET_0 /* We want return to the cpu main loop. */ 74eba6814aSStefan Weil #define DISAS_LOOKUP DISAS_TARGET_1 /* We have a variable condition exit. */ 75eba6814aSStefan Weil #define DISAS_CHAIN DISAS_TARGET_2 /* We have a single condition exit. */ 76e03feba0SMichael Rolnik 77e03feba0SMichael Rolnik typedef struct DisasContext DisasContext; 78e03feba0SMichael Rolnik 79e03feba0SMichael Rolnik /* This is the state at translation time. */ 80e03feba0SMichael Rolnik struct DisasContext { 8193d4d5e4SRichard Henderson DisasContextBase base; 82e03feba0SMichael Rolnik 83e03feba0SMichael Rolnik CPUAVRState *env; 84e03feba0SMichael Rolnik CPUState *cs; 85e03feba0SMichael Rolnik 86e03feba0SMichael Rolnik target_long npc; 87e03feba0SMichael Rolnik uint32_t opcode; 88e03feba0SMichael Rolnik 89e03feba0SMichael Rolnik /* Routine used to access memory */ 90e03feba0SMichael Rolnik int memidx; 91e03feba0SMichael Rolnik 92e03feba0SMichael Rolnik /* 93e03feba0SMichael Rolnik * some AVR instructions can make the following instruction to be skipped 94e03feba0SMichael Rolnik * Let's name those instructions 95e03feba0SMichael Rolnik * A - instruction that can skip the next one 96e03feba0SMichael Rolnik * B - instruction that can be skipped. this depends on execution of A 97e03feba0SMichael Rolnik * there are two scenarios 98e03feba0SMichael Rolnik * 1. A and B belong to the same translation block 99e03feba0SMichael Rolnik * 2. A is the last instruction in the translation block and B is the last 100e03feba0SMichael Rolnik * 101e03feba0SMichael Rolnik * following variables are used to simplify the skipping logic, they are 102e03feba0SMichael Rolnik * used in the following manner (sketch) 103e03feba0SMichael Rolnik * 104e03feba0SMichael Rolnik * TCGLabel *skip_label = NULL; 105bcef6d76SRichard Henderson * if (ctx->skip_cond != TCG_COND_NEVER) { 106e03feba0SMichael Rolnik * skip_label = gen_new_label(); 107e03feba0SMichael Rolnik * tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label); 108e03feba0SMichael Rolnik * } 109e03feba0SMichael Rolnik * 110bcef6d76SRichard Henderson * translate(ctx); 111e03feba0SMichael Rolnik * 112e03feba0SMichael Rolnik * if (skip_label) { 113e03feba0SMichael Rolnik * gen_set_label(skip_label); 114e03feba0SMichael Rolnik * } 115e03feba0SMichael Rolnik */ 116e03feba0SMichael Rolnik TCGv skip_var0; 117e03feba0SMichael Rolnik TCGv skip_var1; 118e03feba0SMichael Rolnik TCGCond skip_cond; 119e03feba0SMichael Rolnik }; 120e03feba0SMichael Rolnik 121a107fdb0SMichael Rolnik void avr_cpu_tcg_init(void) 122a107fdb0SMichael Rolnik { 123a107fdb0SMichael Rolnik int i; 124a107fdb0SMichael Rolnik 125a107fdb0SMichael Rolnik #define AVR_REG_OFFS(x) offsetof(CPUAVRState, x) 126a107fdb0SMichael Rolnik cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc"); 127a107fdb0SMichael Rolnik cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf"); 128a107fdb0SMichael Rolnik cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf"); 129a107fdb0SMichael Rolnik cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf"); 130a107fdb0SMichael Rolnik cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf"); 131a107fdb0SMichael Rolnik cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf"); 132a107fdb0SMichael Rolnik cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf"); 133a107fdb0SMichael Rolnik cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf"); 134a107fdb0SMichael Rolnik cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If"); 135a107fdb0SMichael Rolnik cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "rampD"); 136a107fdb0SMichael Rolnik cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "rampX"); 137a107fdb0SMichael Rolnik cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "rampY"); 138a107fdb0SMichael Rolnik cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "rampZ"); 139a107fdb0SMichael Rolnik cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind"); 140a107fdb0SMichael Rolnik cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp"); 141a107fdb0SMichael Rolnik cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip"); 142a107fdb0SMichael Rolnik 143a107fdb0SMichael Rolnik for (i = 0; i < NUMBER_OF_CPU_REGISTERS; i++) { 144a107fdb0SMichael Rolnik cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]), 145a107fdb0SMichael Rolnik reg_names[i]); 146a107fdb0SMichael Rolnik } 147a107fdb0SMichael Rolnik #undef AVR_REG_OFFS 148a107fdb0SMichael Rolnik } 149a107fdb0SMichael Rolnik 150865f3bb9SMichael Rolnik static int to_regs_16_31_by_one(DisasContext *ctx, int indx) 151865f3bb9SMichael Rolnik { 152865f3bb9SMichael Rolnik return 16 + (indx % 16); 153865f3bb9SMichael Rolnik } 154865f3bb9SMichael Rolnik 155865f3bb9SMichael Rolnik static int to_regs_16_23_by_one(DisasContext *ctx, int indx) 156865f3bb9SMichael Rolnik { 157865f3bb9SMichael Rolnik return 16 + (indx % 8); 158865f3bb9SMichael Rolnik } 159865f3bb9SMichael Rolnik 160865f3bb9SMichael Rolnik static int to_regs_24_30_by_two(DisasContext *ctx, int indx) 161865f3bb9SMichael Rolnik { 162865f3bb9SMichael Rolnik return 24 + (indx % 4) * 2; 163865f3bb9SMichael Rolnik } 164865f3bb9SMichael Rolnik 1659732b024SMichael Rolnik static int to_regs_00_30_by_two(DisasContext *ctx, int indx) 1669732b024SMichael Rolnik { 1679732b024SMichael Rolnik return (indx % 16) * 2; 1689732b024SMichael Rolnik } 169865f3bb9SMichael Rolnik 1709d316c75SMichael Rolnik static uint16_t next_word(DisasContext *ctx) 1719d316c75SMichael Rolnik { 1729d316c75SMichael Rolnik return cpu_lduw_code(ctx->env, ctx->npc++ * 2); 1739d316c75SMichael Rolnik } 1749d316c75SMichael Rolnik 1759d316c75SMichael Rolnik static int append_16(DisasContext *ctx, int x) 1769d316c75SMichael Rolnik { 1779d316c75SMichael Rolnik return x << 16 | next_word(ctx); 1789d316c75SMichael Rolnik } 1799d316c75SMichael Rolnik 180e03feba0SMichael Rolnik static bool avr_have_feature(DisasContext *ctx, int feature) 181e03feba0SMichael Rolnik { 182e03feba0SMichael Rolnik if (!avr_feature(ctx->env, feature)) { 183e03feba0SMichael Rolnik gen_helper_unsupported(cpu_env); 18493d4d5e4SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 185e03feba0SMichael Rolnik return false; 186e03feba0SMichael Rolnik } 187e03feba0SMichael Rolnik return true; 188e03feba0SMichael Rolnik } 189e03feba0SMichael Rolnik 190e03feba0SMichael Rolnik static bool decode_insn(DisasContext *ctx, uint16_t insn); 191abff1abfSPaolo Bonzini #include "decode-insn.c.inc" 192865f3bb9SMichael Rolnik 193865f3bb9SMichael Rolnik /* 194865f3bb9SMichael Rolnik * Arithmetic Instructions 195865f3bb9SMichael Rolnik */ 196865f3bb9SMichael Rolnik 197865f3bb9SMichael Rolnik /* 198865f3bb9SMichael Rolnik * Utility functions for updating status registers: 199865f3bb9SMichael Rolnik * 200865f3bb9SMichael Rolnik * - gen_add_CHf() 201865f3bb9SMichael Rolnik * - gen_add_Vf() 202865f3bb9SMichael Rolnik * - gen_sub_CHf() 203865f3bb9SMichael Rolnik * - gen_sub_Vf() 204865f3bb9SMichael Rolnik * - gen_NSf() 205865f3bb9SMichael Rolnik * - gen_ZNSf() 206865f3bb9SMichael Rolnik * 207865f3bb9SMichael Rolnik */ 208865f3bb9SMichael Rolnik 209865f3bb9SMichael Rolnik static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr) 210865f3bb9SMichael Rolnik { 211865f3bb9SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 212865f3bb9SMichael Rolnik TCGv t2 = tcg_temp_new_i32(); 213865f3bb9SMichael Rolnik TCGv t3 = tcg_temp_new_i32(); 214865f3bb9SMichael Rolnik 215865f3bb9SMichael Rolnik tcg_gen_and_tl(t1, Rd, Rr); /* t1 = Rd & Rr */ 216865f3bb9SMichael Rolnik tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd & ~R */ 217865f3bb9SMichael Rolnik tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr & ~R */ 218865f3bb9SMichael Rolnik tcg_gen_or_tl(t1, t1, t2); /* t1 = t1 | t2 | t3 */ 219865f3bb9SMichael Rolnik tcg_gen_or_tl(t1, t1, t3); 220865f3bb9SMichael Rolnik 221865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf = t1(7) */ 222865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf = t1(3) */ 223865f3bb9SMichael Rolnik tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1); 224865f3bb9SMichael Rolnik } 225865f3bb9SMichael Rolnik 226865f3bb9SMichael Rolnik static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr) 227865f3bb9SMichael Rolnik { 228865f3bb9SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 229865f3bb9SMichael Rolnik TCGv t2 = tcg_temp_new_i32(); 230865f3bb9SMichael Rolnik 231865f3bb9SMichael Rolnik /* t1 = Rd & Rr & ~R | ~Rd & ~Rr & R */ 232865f3bb9SMichael Rolnik /* = (Rd ^ R) & ~(Rd ^ Rr) */ 233865f3bb9SMichael Rolnik tcg_gen_xor_tl(t1, Rd, R); 234865f3bb9SMichael Rolnik tcg_gen_xor_tl(t2, Rd, Rr); 235865f3bb9SMichael Rolnik tcg_gen_andc_tl(t1, t1, t2); 236865f3bb9SMichael Rolnik 237865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */ 238865f3bb9SMichael Rolnik } 239865f3bb9SMichael Rolnik 240865f3bb9SMichael Rolnik static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr) 241865f3bb9SMichael Rolnik { 242865f3bb9SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 243865f3bb9SMichael Rolnik TCGv t2 = tcg_temp_new_i32(); 244865f3bb9SMichael Rolnik TCGv t3 = tcg_temp_new_i32(); 245865f3bb9SMichael Rolnik 246865f3bb9SMichael Rolnik tcg_gen_not_tl(t1, Rd); /* t1 = ~Rd */ 247865f3bb9SMichael Rolnik tcg_gen_and_tl(t2, t1, Rr); /* t2 = ~Rd & Rr */ 248865f3bb9SMichael Rolnik tcg_gen_or_tl(t3, t1, Rr); /* t3 = (~Rd | Rr) & R */ 249865f3bb9SMichael Rolnik tcg_gen_and_tl(t3, t3, R); 250865f3bb9SMichael Rolnik tcg_gen_or_tl(t2, t2, t3); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */ 251865f3bb9SMichael Rolnik 252865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf = t2(7) */ 253865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf = t2(3) */ 254865f3bb9SMichael Rolnik tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1); 255865f3bb9SMichael Rolnik } 256865f3bb9SMichael Rolnik 257865f3bb9SMichael Rolnik static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr) 258865f3bb9SMichael Rolnik { 259865f3bb9SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 260865f3bb9SMichael Rolnik TCGv t2 = tcg_temp_new_i32(); 261865f3bb9SMichael Rolnik 262865f3bb9SMichael Rolnik /* t1 = Rd & ~Rr & ~R | ~Rd & Rr & R */ 263865f3bb9SMichael Rolnik /* = (Rd ^ R) & (Rd ^ R) */ 264865f3bb9SMichael Rolnik tcg_gen_xor_tl(t1, Rd, R); 265865f3bb9SMichael Rolnik tcg_gen_xor_tl(t2, Rd, Rr); 266865f3bb9SMichael Rolnik tcg_gen_and_tl(t1, t1, t2); 267865f3bb9SMichael Rolnik 268865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf = t1(7) */ 269865f3bb9SMichael Rolnik } 270865f3bb9SMichael Rolnik 271865f3bb9SMichael Rolnik static void gen_NSf(TCGv R) 272865f3bb9SMichael Rolnik { 273865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 274865f3bb9SMichael Rolnik tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 275865f3bb9SMichael Rolnik } 276865f3bb9SMichael Rolnik 277865f3bb9SMichael Rolnik static void gen_ZNSf(TCGv R) 278865f3bb9SMichael Rolnik { 279865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 280865f3bb9SMichael Rolnik 281865f3bb9SMichael Rolnik /* update status register */ 282865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 283865f3bb9SMichael Rolnik tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 284865f3bb9SMichael Rolnik } 285865f3bb9SMichael Rolnik 286865f3bb9SMichael Rolnik /* 287865f3bb9SMichael Rolnik * Adds two registers without the C Flag and places the result in the 288865f3bb9SMichael Rolnik * destination register Rd. 289865f3bb9SMichael Rolnik */ 290865f3bb9SMichael Rolnik static bool trans_ADD(DisasContext *ctx, arg_ADD *a) 291865f3bb9SMichael Rolnik { 292865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 293865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 294865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 295865f3bb9SMichael Rolnik 296865f3bb9SMichael Rolnik tcg_gen_add_tl(R, Rd, Rr); /* Rd = Rd + Rr */ 297865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 298865f3bb9SMichael Rolnik 299865f3bb9SMichael Rolnik /* update status register */ 300865f3bb9SMichael Rolnik gen_add_CHf(R, Rd, Rr); 301865f3bb9SMichael Rolnik gen_add_Vf(R, Rd, Rr); 302865f3bb9SMichael Rolnik gen_ZNSf(R); 303865f3bb9SMichael Rolnik 304865f3bb9SMichael Rolnik /* update output registers */ 305865f3bb9SMichael Rolnik tcg_gen_mov_tl(Rd, R); 306865f3bb9SMichael Rolnik return true; 307865f3bb9SMichael Rolnik } 308865f3bb9SMichael Rolnik 309865f3bb9SMichael Rolnik /* 310865f3bb9SMichael Rolnik * Adds two registers and the contents of the C Flag and places the result in 311865f3bb9SMichael Rolnik * the destination register Rd. 312865f3bb9SMichael Rolnik */ 313865f3bb9SMichael Rolnik static bool trans_ADC(DisasContext *ctx, arg_ADC *a) 314865f3bb9SMichael Rolnik { 315865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 316865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 317865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 318865f3bb9SMichael Rolnik 319865f3bb9SMichael Rolnik tcg_gen_add_tl(R, Rd, Rr); /* R = Rd + Rr + Cf */ 320865f3bb9SMichael Rolnik tcg_gen_add_tl(R, R, cpu_Cf); 321865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 322865f3bb9SMichael Rolnik 323865f3bb9SMichael Rolnik /* update status register */ 324865f3bb9SMichael Rolnik gen_add_CHf(R, Rd, Rr); 325865f3bb9SMichael Rolnik gen_add_Vf(R, Rd, Rr); 326865f3bb9SMichael Rolnik gen_ZNSf(R); 327865f3bb9SMichael Rolnik 328865f3bb9SMichael Rolnik /* update output registers */ 329865f3bb9SMichael Rolnik tcg_gen_mov_tl(Rd, R); 330865f3bb9SMichael Rolnik return true; 331865f3bb9SMichael Rolnik } 332865f3bb9SMichael Rolnik 333865f3bb9SMichael Rolnik /* 334865f3bb9SMichael Rolnik * Adds an immediate value (0 - 63) to a register pair and places the result 335865f3bb9SMichael Rolnik * in the register pair. This instruction operates on the upper four register 336865f3bb9SMichael Rolnik * pairs, and is well suited for operations on the pointer registers. This 337865f3bb9SMichael Rolnik * instruction is not available in all devices. Refer to the device specific 338865f3bb9SMichael Rolnik * instruction set summary. 339865f3bb9SMichael Rolnik */ 340865f3bb9SMichael Rolnik static bool trans_ADIW(DisasContext *ctx, arg_ADIW *a) 341865f3bb9SMichael Rolnik { 342865f3bb9SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) { 343865f3bb9SMichael Rolnik return true; 344865f3bb9SMichael Rolnik } 345865f3bb9SMichael Rolnik 346865f3bb9SMichael Rolnik TCGv RdL = cpu_r[a->rd]; 347865f3bb9SMichael Rolnik TCGv RdH = cpu_r[a->rd + 1]; 348865f3bb9SMichael Rolnik int Imm = (a->imm); 349865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 350865f3bb9SMichael Rolnik TCGv Rd = tcg_temp_new_i32(); 351865f3bb9SMichael Rolnik 352865f3bb9SMichael Rolnik tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */ 353865f3bb9SMichael Rolnik tcg_gen_addi_tl(R, Rd, Imm); /* R = Rd + Imm */ 354865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 355865f3bb9SMichael Rolnik 356865f3bb9SMichael Rolnik /* update status register */ 357865f3bb9SMichael Rolnik tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */ 358865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15); 359865f3bb9SMichael Rolnik tcg_gen_andc_tl(cpu_Vf, R, Rd); /* Vf = R & ~Rd */ 360865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15); 361865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 362865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */ 363865f3bb9SMichael Rolnik tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf);/* Sf = Nf ^ Vf */ 364865f3bb9SMichael Rolnik 365865f3bb9SMichael Rolnik /* update output registers */ 366865f3bb9SMichael Rolnik tcg_gen_andi_tl(RdL, R, 0xff); 367865f3bb9SMichael Rolnik tcg_gen_shri_tl(RdH, R, 8); 368865f3bb9SMichael Rolnik return true; 369865f3bb9SMichael Rolnik } 370865f3bb9SMichael Rolnik 371865f3bb9SMichael Rolnik /* 372865f3bb9SMichael Rolnik * Subtracts two registers and places the result in the destination 373865f3bb9SMichael Rolnik * register Rd. 374865f3bb9SMichael Rolnik */ 375865f3bb9SMichael Rolnik static bool trans_SUB(DisasContext *ctx, arg_SUB *a) 376865f3bb9SMichael Rolnik { 377865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 378865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 379865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 380865f3bb9SMichael Rolnik 381865f3bb9SMichael Rolnik tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 382865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 383865f3bb9SMichael Rolnik 384865f3bb9SMichael Rolnik /* update status register */ 385865f3bb9SMichael Rolnik tcg_gen_andc_tl(cpu_Cf, Rd, R); /* Cf = Rd & ~R */ 386865f3bb9SMichael Rolnik gen_sub_CHf(R, Rd, Rr); 387865f3bb9SMichael Rolnik gen_sub_Vf(R, Rd, Rr); 388865f3bb9SMichael Rolnik gen_ZNSf(R); 389865f3bb9SMichael Rolnik 390865f3bb9SMichael Rolnik /* update output registers */ 391865f3bb9SMichael Rolnik tcg_gen_mov_tl(Rd, R); 392865f3bb9SMichael Rolnik return true; 393865f3bb9SMichael Rolnik } 394865f3bb9SMichael Rolnik 395865f3bb9SMichael Rolnik /* 396865f3bb9SMichael Rolnik * Subtracts a register and a constant and places the result in the 397865f3bb9SMichael Rolnik * destination register Rd. This instruction is working on Register R16 to R31 398865f3bb9SMichael Rolnik * and is very well suited for operations on the X, Y, and Z-pointers. 399865f3bb9SMichael Rolnik */ 400865f3bb9SMichael Rolnik static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a) 401865f3bb9SMichael Rolnik { 402865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 4036d27bb55SRichard Henderson TCGv Rr = tcg_constant_i32(a->imm); 404865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 405865f3bb9SMichael Rolnik 406865f3bb9SMichael Rolnik tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */ 407865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 408865f3bb9SMichael Rolnik 409865f3bb9SMichael Rolnik /* update status register */ 410865f3bb9SMichael Rolnik gen_sub_CHf(R, Rd, Rr); 411865f3bb9SMichael Rolnik gen_sub_Vf(R, Rd, Rr); 412865f3bb9SMichael Rolnik gen_ZNSf(R); 413865f3bb9SMichael Rolnik 414865f3bb9SMichael Rolnik /* update output registers */ 415865f3bb9SMichael Rolnik tcg_gen_mov_tl(Rd, R); 416865f3bb9SMichael Rolnik return true; 417865f3bb9SMichael Rolnik } 418865f3bb9SMichael Rolnik 419865f3bb9SMichael Rolnik /* 420865f3bb9SMichael Rolnik * Subtracts two registers and subtracts with the C Flag and places the 421865f3bb9SMichael Rolnik * result in the destination register Rd. 422865f3bb9SMichael Rolnik */ 423865f3bb9SMichael Rolnik static bool trans_SBC(DisasContext *ctx, arg_SBC *a) 424865f3bb9SMichael Rolnik { 425865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 426865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 427865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 4286d27bb55SRichard Henderson TCGv zero = tcg_constant_i32(0); 429865f3bb9SMichael Rolnik 430865f3bb9SMichael Rolnik tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 431865f3bb9SMichael Rolnik tcg_gen_sub_tl(R, R, cpu_Cf); 432865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 433865f3bb9SMichael Rolnik 434865f3bb9SMichael Rolnik /* update status register */ 435865f3bb9SMichael Rolnik gen_sub_CHf(R, Rd, Rr); 436865f3bb9SMichael Rolnik gen_sub_Vf(R, Rd, Rr); 437865f3bb9SMichael Rolnik gen_NSf(R); 438865f3bb9SMichael Rolnik 439865f3bb9SMichael Rolnik /* 440865f3bb9SMichael Rolnik * Previous value remains unchanged when the result is zero; 441865f3bb9SMichael Rolnik * cleared otherwise. 442865f3bb9SMichael Rolnik */ 443865f3bb9SMichael Rolnik tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 444865f3bb9SMichael Rolnik 445865f3bb9SMichael Rolnik /* update output registers */ 446865f3bb9SMichael Rolnik tcg_gen_mov_tl(Rd, R); 447865f3bb9SMichael Rolnik return true; 448865f3bb9SMichael Rolnik } 449865f3bb9SMichael Rolnik 450865f3bb9SMichael Rolnik /* 451865f3bb9SMichael Rolnik * SBCI -- Subtract Immediate with Carry 452865f3bb9SMichael Rolnik */ 453865f3bb9SMichael Rolnik static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a) 454865f3bb9SMichael Rolnik { 455865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 4566d27bb55SRichard Henderson TCGv Rr = tcg_constant_i32(a->imm); 457865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 4586d27bb55SRichard Henderson TCGv zero = tcg_constant_i32(0); 459865f3bb9SMichael Rolnik 460865f3bb9SMichael Rolnik tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 461865f3bb9SMichael Rolnik tcg_gen_sub_tl(R, R, cpu_Cf); 462865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 463865f3bb9SMichael Rolnik 464865f3bb9SMichael Rolnik /* update status register */ 465865f3bb9SMichael Rolnik gen_sub_CHf(R, Rd, Rr); 466865f3bb9SMichael Rolnik gen_sub_Vf(R, Rd, Rr); 467865f3bb9SMichael Rolnik gen_NSf(R); 468865f3bb9SMichael Rolnik 469865f3bb9SMichael Rolnik /* 470865f3bb9SMichael Rolnik * Previous value remains unchanged when the result is zero; 471865f3bb9SMichael Rolnik * cleared otherwise. 472865f3bb9SMichael Rolnik */ 473865f3bb9SMichael Rolnik tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 474865f3bb9SMichael Rolnik 475865f3bb9SMichael Rolnik /* update output registers */ 476865f3bb9SMichael Rolnik tcg_gen_mov_tl(Rd, R); 477865f3bb9SMichael Rolnik return true; 478865f3bb9SMichael Rolnik } 479865f3bb9SMichael Rolnik 480865f3bb9SMichael Rolnik /* 481865f3bb9SMichael Rolnik * Subtracts an immediate value (0-63) from a register pair and places the 482865f3bb9SMichael Rolnik * result in the register pair. This instruction operates on the upper four 483865f3bb9SMichael Rolnik * register pairs, and is well suited for operations on the Pointer Registers. 484865f3bb9SMichael Rolnik * This instruction is not available in all devices. Refer to the device 485865f3bb9SMichael Rolnik * specific instruction set summary. 486865f3bb9SMichael Rolnik */ 487865f3bb9SMichael Rolnik static bool trans_SBIW(DisasContext *ctx, arg_SBIW *a) 488865f3bb9SMichael Rolnik { 489865f3bb9SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_ADIW_SBIW)) { 490865f3bb9SMichael Rolnik return true; 491865f3bb9SMichael Rolnik } 492865f3bb9SMichael Rolnik 493865f3bb9SMichael Rolnik TCGv RdL = cpu_r[a->rd]; 494865f3bb9SMichael Rolnik TCGv RdH = cpu_r[a->rd + 1]; 495865f3bb9SMichael Rolnik int Imm = (a->imm); 496865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 497865f3bb9SMichael Rolnik TCGv Rd = tcg_temp_new_i32(); 498865f3bb9SMichael Rolnik 499865f3bb9SMichael Rolnik tcg_gen_deposit_tl(Rd, RdL, RdH, 8, 8); /* Rd = RdH:RdL */ 500865f3bb9SMichael Rolnik tcg_gen_subi_tl(R, Rd, Imm); /* R = Rd - Imm */ 501865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 502865f3bb9SMichael Rolnik 503865f3bb9SMichael Rolnik /* update status register */ 504865f3bb9SMichael Rolnik tcg_gen_andc_tl(cpu_Cf, R, Rd); 505865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Cf, cpu_Cf, 15); /* Cf = R & ~Rd */ 506865f3bb9SMichael Rolnik tcg_gen_andc_tl(cpu_Vf, Rd, R); 507865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Vf, cpu_Vf, 15); /* Vf = Rd & ~R */ 508865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 509865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Nf, R, 15); /* Nf = R(15) */ 510865f3bb9SMichael Rolnik tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 511865f3bb9SMichael Rolnik 512865f3bb9SMichael Rolnik /* update output registers */ 513865f3bb9SMichael Rolnik tcg_gen_andi_tl(RdL, R, 0xff); 514865f3bb9SMichael Rolnik tcg_gen_shri_tl(RdH, R, 8); 515865f3bb9SMichael Rolnik return true; 516865f3bb9SMichael Rolnik } 517865f3bb9SMichael Rolnik 518865f3bb9SMichael Rolnik /* 519865f3bb9SMichael Rolnik * Performs the logical AND between the contents of register Rd and register 520865f3bb9SMichael Rolnik * Rr and places the result in the destination register Rd. 521865f3bb9SMichael Rolnik */ 522865f3bb9SMichael Rolnik static bool trans_AND(DisasContext *ctx, arg_AND *a) 523865f3bb9SMichael Rolnik { 524865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 525865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 526865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 527865f3bb9SMichael Rolnik 528865f3bb9SMichael Rolnik tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */ 529865f3bb9SMichael Rolnik 530865f3bb9SMichael Rolnik /* update status register */ 531865f3bb9SMichael Rolnik tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */ 532865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 533865f3bb9SMichael Rolnik gen_ZNSf(R); 534865f3bb9SMichael Rolnik 535865f3bb9SMichael Rolnik /* update output registers */ 536865f3bb9SMichael Rolnik tcg_gen_mov_tl(Rd, R); 537865f3bb9SMichael Rolnik return true; 538865f3bb9SMichael Rolnik } 539865f3bb9SMichael Rolnik 540865f3bb9SMichael Rolnik /* 541865f3bb9SMichael Rolnik * Performs the logical AND between the contents of register Rd and a constant 542865f3bb9SMichael Rolnik * and places the result in the destination register Rd. 543865f3bb9SMichael Rolnik */ 544865f3bb9SMichael Rolnik static bool trans_ANDI(DisasContext *ctx, arg_ANDI *a) 545865f3bb9SMichael Rolnik { 546865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 547865f3bb9SMichael Rolnik int Imm = (a->imm); 548865f3bb9SMichael Rolnik 549865f3bb9SMichael Rolnik tcg_gen_andi_tl(Rd, Rd, Imm); /* Rd = Rd & Imm */ 550865f3bb9SMichael Rolnik 551865f3bb9SMichael Rolnik /* update status register */ 552865f3bb9SMichael Rolnik tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */ 553865f3bb9SMichael Rolnik gen_ZNSf(Rd); 554865f3bb9SMichael Rolnik 555865f3bb9SMichael Rolnik return true; 556865f3bb9SMichael Rolnik } 557865f3bb9SMichael Rolnik 558865f3bb9SMichael Rolnik /* 559865f3bb9SMichael Rolnik * Performs the logical OR between the contents of register Rd and register 560865f3bb9SMichael Rolnik * Rr and places the result in the destination register Rd. 561865f3bb9SMichael Rolnik */ 562865f3bb9SMichael Rolnik static bool trans_OR(DisasContext *ctx, arg_OR *a) 563865f3bb9SMichael Rolnik { 564865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 565865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 566865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 567865f3bb9SMichael Rolnik 568865f3bb9SMichael Rolnik tcg_gen_or_tl(R, Rd, Rr); 569865f3bb9SMichael Rolnik 570865f3bb9SMichael Rolnik /* update status register */ 571865f3bb9SMichael Rolnik tcg_gen_movi_tl(cpu_Vf, 0); 572865f3bb9SMichael Rolnik gen_ZNSf(R); 573865f3bb9SMichael Rolnik 574865f3bb9SMichael Rolnik /* update output registers */ 575865f3bb9SMichael Rolnik tcg_gen_mov_tl(Rd, R); 576865f3bb9SMichael Rolnik return true; 577865f3bb9SMichael Rolnik } 578865f3bb9SMichael Rolnik 579865f3bb9SMichael Rolnik /* 580865f3bb9SMichael Rolnik * Performs the logical OR between the contents of register Rd and a 581865f3bb9SMichael Rolnik * constant and places the result in the destination register Rd. 582865f3bb9SMichael Rolnik */ 583865f3bb9SMichael Rolnik static bool trans_ORI(DisasContext *ctx, arg_ORI *a) 584865f3bb9SMichael Rolnik { 585865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 586865f3bb9SMichael Rolnik int Imm = (a->imm); 587865f3bb9SMichael Rolnik 588865f3bb9SMichael Rolnik tcg_gen_ori_tl(Rd, Rd, Imm); /* Rd = Rd | Imm */ 589865f3bb9SMichael Rolnik 590865f3bb9SMichael Rolnik /* update status register */ 591865f3bb9SMichael Rolnik tcg_gen_movi_tl(cpu_Vf, 0x00); /* Vf = 0 */ 592865f3bb9SMichael Rolnik gen_ZNSf(Rd); 593865f3bb9SMichael Rolnik 594865f3bb9SMichael Rolnik return true; 595865f3bb9SMichael Rolnik } 596865f3bb9SMichael Rolnik 597865f3bb9SMichael Rolnik /* 598865f3bb9SMichael Rolnik * Performs the logical EOR between the contents of register Rd and 599865f3bb9SMichael Rolnik * register Rr and places the result in the destination register Rd. 600865f3bb9SMichael Rolnik */ 601865f3bb9SMichael Rolnik static bool trans_EOR(DisasContext *ctx, arg_EOR *a) 602865f3bb9SMichael Rolnik { 603865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 604865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 605865f3bb9SMichael Rolnik 606865f3bb9SMichael Rolnik tcg_gen_xor_tl(Rd, Rd, Rr); 607865f3bb9SMichael Rolnik 608865f3bb9SMichael Rolnik /* update status register */ 609865f3bb9SMichael Rolnik tcg_gen_movi_tl(cpu_Vf, 0); 610865f3bb9SMichael Rolnik gen_ZNSf(Rd); 611865f3bb9SMichael Rolnik 612865f3bb9SMichael Rolnik return true; 613865f3bb9SMichael Rolnik } 614865f3bb9SMichael Rolnik 615865f3bb9SMichael Rolnik /* 616865f3bb9SMichael Rolnik * Clears the specified bits in register Rd. Performs the logical AND 617865f3bb9SMichael Rolnik * between the contents of register Rd and the complement of the constant mask 618865f3bb9SMichael Rolnik * K. The result will be placed in register Rd. 619865f3bb9SMichael Rolnik */ 620865f3bb9SMichael Rolnik static bool trans_COM(DisasContext *ctx, arg_COM *a) 621865f3bb9SMichael Rolnik { 622865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 623865f3bb9SMichael Rolnik 624865f3bb9SMichael Rolnik tcg_gen_xori_tl(Rd, Rd, 0xff); 625865f3bb9SMichael Rolnik 626865f3bb9SMichael Rolnik /* update status register */ 627865f3bb9SMichael Rolnik tcg_gen_movi_tl(cpu_Cf, 1); /* Cf = 1 */ 628865f3bb9SMichael Rolnik tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */ 629865f3bb9SMichael Rolnik gen_ZNSf(Rd); 630865f3bb9SMichael Rolnik return true; 631865f3bb9SMichael Rolnik } 632865f3bb9SMichael Rolnik 633865f3bb9SMichael Rolnik /* 634865f3bb9SMichael Rolnik * Replaces the contents of register Rd with its two's complement; the 635865f3bb9SMichael Rolnik * value $80 is left unchanged. 636865f3bb9SMichael Rolnik */ 637865f3bb9SMichael Rolnik static bool trans_NEG(DisasContext *ctx, arg_NEG *a) 638865f3bb9SMichael Rolnik { 639865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 6406d27bb55SRichard Henderson TCGv t0 = tcg_constant_i32(0); 641865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 642865f3bb9SMichael Rolnik 643865f3bb9SMichael Rolnik tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */ 644865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 645865f3bb9SMichael Rolnik 646865f3bb9SMichael Rolnik /* update status register */ 647865f3bb9SMichael Rolnik gen_sub_CHf(R, t0, Rd); 648865f3bb9SMichael Rolnik gen_sub_Vf(R, t0, Rd); 649865f3bb9SMichael Rolnik gen_ZNSf(R); 650865f3bb9SMichael Rolnik 651865f3bb9SMichael Rolnik /* update output registers */ 652865f3bb9SMichael Rolnik tcg_gen_mov_tl(Rd, R); 653865f3bb9SMichael Rolnik return true; 654865f3bb9SMichael Rolnik } 655865f3bb9SMichael Rolnik 656865f3bb9SMichael Rolnik /* 657865f3bb9SMichael Rolnik * Adds one -1- to the contents of register Rd and places the result in the 658865f3bb9SMichael Rolnik * destination register Rd. The C Flag in SREG is not affected by the 659865f3bb9SMichael Rolnik * operation, thus allowing the INC instruction to be used on a loop counter in 660865f3bb9SMichael Rolnik * multiple-precision computations. When operating on unsigned numbers, only 661865f3bb9SMichael Rolnik * BREQ and BRNE branches can be expected to perform consistently. When 662865f3bb9SMichael Rolnik * operating on two's complement values, all signed branches are available. 663865f3bb9SMichael Rolnik */ 664865f3bb9SMichael Rolnik static bool trans_INC(DisasContext *ctx, arg_INC *a) 665865f3bb9SMichael Rolnik { 666865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 667865f3bb9SMichael Rolnik 668865f3bb9SMichael Rolnik tcg_gen_addi_tl(Rd, Rd, 1); 669865f3bb9SMichael Rolnik tcg_gen_andi_tl(Rd, Rd, 0xff); 670865f3bb9SMichael Rolnik 671865f3bb9SMichael Rolnik /* update status register */ 672865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x80); /* Vf = Rd == 0x80 */ 673865f3bb9SMichael Rolnik gen_ZNSf(Rd); 674865f3bb9SMichael Rolnik 675865f3bb9SMichael Rolnik return true; 676865f3bb9SMichael Rolnik } 677865f3bb9SMichael Rolnik 678865f3bb9SMichael Rolnik /* 679865f3bb9SMichael Rolnik * Subtracts one -1- from the contents of register Rd and places the result 680865f3bb9SMichael Rolnik * in the destination register Rd. The C Flag in SREG is not affected by the 681865f3bb9SMichael Rolnik * operation, thus allowing the DEC instruction to be used on a loop counter in 682865f3bb9SMichael Rolnik * multiple-precision computations. When operating on unsigned values, only 683865f3bb9SMichael Rolnik * BREQ and BRNE branches can be expected to perform consistently. When 684865f3bb9SMichael Rolnik * operating on two's complement values, all signed branches are available. 685865f3bb9SMichael Rolnik */ 686865f3bb9SMichael Rolnik static bool trans_DEC(DisasContext *ctx, arg_DEC *a) 687865f3bb9SMichael Rolnik { 688865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 689865f3bb9SMichael Rolnik 690865f3bb9SMichael Rolnik tcg_gen_subi_tl(Rd, Rd, 1); /* Rd = Rd - 1 */ 691865f3bb9SMichael Rolnik tcg_gen_andi_tl(Rd, Rd, 0xff); /* make it 8 bits */ 692865f3bb9SMichael Rolnik 693865f3bb9SMichael Rolnik /* update status register */ 694865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Vf, Rd, 0x7f); /* Vf = Rd == 0x7f */ 695865f3bb9SMichael Rolnik gen_ZNSf(Rd); 696865f3bb9SMichael Rolnik 697865f3bb9SMichael Rolnik return true; 698865f3bb9SMichael Rolnik } 699865f3bb9SMichael Rolnik 700865f3bb9SMichael Rolnik /* 701865f3bb9SMichael Rolnik * This instruction performs 8-bit x 8-bit -> 16-bit unsigned multiplication. 702865f3bb9SMichael Rolnik */ 703865f3bb9SMichael Rolnik static bool trans_MUL(DisasContext *ctx, arg_MUL *a) 704865f3bb9SMichael Rolnik { 705865f3bb9SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 706865f3bb9SMichael Rolnik return true; 707865f3bb9SMichael Rolnik } 708865f3bb9SMichael Rolnik 709865f3bb9SMichael Rolnik TCGv R0 = cpu_r[0]; 710865f3bb9SMichael Rolnik TCGv R1 = cpu_r[1]; 711865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 712865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 713865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 714865f3bb9SMichael Rolnik 715865f3bb9SMichael Rolnik tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd * Rr */ 716865f3bb9SMichael Rolnik tcg_gen_andi_tl(R0, R, 0xff); 717865f3bb9SMichael Rolnik tcg_gen_shri_tl(R1, R, 8); 718865f3bb9SMichael Rolnik 719865f3bb9SMichael Rolnik /* update status register */ 720865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 721865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 722865f3bb9SMichael Rolnik return true; 723865f3bb9SMichael Rolnik } 724865f3bb9SMichael Rolnik 725865f3bb9SMichael Rolnik /* 726865f3bb9SMichael Rolnik * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication. 727865f3bb9SMichael Rolnik */ 728865f3bb9SMichael Rolnik static bool trans_MULS(DisasContext *ctx, arg_MULS *a) 729865f3bb9SMichael Rolnik { 730865f3bb9SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 731865f3bb9SMichael Rolnik return true; 732865f3bb9SMichael Rolnik } 733865f3bb9SMichael Rolnik 734865f3bb9SMichael Rolnik TCGv R0 = cpu_r[0]; 735865f3bb9SMichael Rolnik TCGv R1 = cpu_r[1]; 736865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 737865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 738865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 739865f3bb9SMichael Rolnik TCGv t0 = tcg_temp_new_i32(); 740865f3bb9SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 741865f3bb9SMichael Rolnik 742865f3bb9SMichael Rolnik tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 743865f3bb9SMichael Rolnik tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */ 744865f3bb9SMichael Rolnik tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */ 745865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 746865f3bb9SMichael Rolnik tcg_gen_andi_tl(R0, R, 0xff); 747865f3bb9SMichael Rolnik tcg_gen_shri_tl(R1, R, 8); 748865f3bb9SMichael Rolnik 749865f3bb9SMichael Rolnik /* update status register */ 750865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 751865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 752865f3bb9SMichael Rolnik return true; 753865f3bb9SMichael Rolnik } 754865f3bb9SMichael Rolnik 755865f3bb9SMichael Rolnik /* 756865f3bb9SMichael Rolnik * This instruction performs 8-bit x 8-bit -> 16-bit multiplication of a 757865f3bb9SMichael Rolnik * signed and an unsigned number. 758865f3bb9SMichael Rolnik */ 759865f3bb9SMichael Rolnik static bool trans_MULSU(DisasContext *ctx, arg_MULSU *a) 760865f3bb9SMichael Rolnik { 761865f3bb9SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 762865f3bb9SMichael Rolnik return true; 763865f3bb9SMichael Rolnik } 764865f3bb9SMichael Rolnik 765865f3bb9SMichael Rolnik TCGv R0 = cpu_r[0]; 766865f3bb9SMichael Rolnik TCGv R1 = cpu_r[1]; 767865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 768865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 769865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 770865f3bb9SMichael Rolnik TCGv t0 = tcg_temp_new_i32(); 771865f3bb9SMichael Rolnik 772865f3bb9SMichael Rolnik tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 773865f3bb9SMichael Rolnik tcg_gen_mul_tl(R, t0, Rr); /* R = Rd * Rr */ 774865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xffff); /* make R 16 bits */ 775865f3bb9SMichael Rolnik tcg_gen_andi_tl(R0, R, 0xff); 776865f3bb9SMichael Rolnik tcg_gen_shri_tl(R1, R, 8); 777865f3bb9SMichael Rolnik 778865f3bb9SMichael Rolnik /* update status register */ 779865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 780865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 781865f3bb9SMichael Rolnik return true; 782865f3bb9SMichael Rolnik } 783865f3bb9SMichael Rolnik 784865f3bb9SMichael Rolnik /* 785865f3bb9SMichael Rolnik * This instruction performs 8-bit x 8-bit -> 16-bit unsigned 786865f3bb9SMichael Rolnik * multiplication and shifts the result one bit left. 787865f3bb9SMichael Rolnik */ 788865f3bb9SMichael Rolnik static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a) 789865f3bb9SMichael Rolnik { 790865f3bb9SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 791865f3bb9SMichael Rolnik return true; 792865f3bb9SMichael Rolnik } 793865f3bb9SMichael Rolnik 794865f3bb9SMichael Rolnik TCGv R0 = cpu_r[0]; 795865f3bb9SMichael Rolnik TCGv R1 = cpu_r[1]; 796865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 797865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 798865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 799865f3bb9SMichael Rolnik 800865f3bb9SMichael Rolnik tcg_gen_mul_tl(R, Rd, Rr); /* R = Rd * Rr */ 801865f3bb9SMichael Rolnik 802865f3bb9SMichael Rolnik /* update status register */ 803865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 804865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 805865f3bb9SMichael Rolnik 806865f3bb9SMichael Rolnik /* update output registers */ 807865f3bb9SMichael Rolnik tcg_gen_shli_tl(R, R, 1); 808865f3bb9SMichael Rolnik tcg_gen_andi_tl(R0, R, 0xff); 809865f3bb9SMichael Rolnik tcg_gen_shri_tl(R1, R, 8); 810865f3bb9SMichael Rolnik tcg_gen_andi_tl(R1, R1, 0xff); 811865f3bb9SMichael Rolnik return true; 812865f3bb9SMichael Rolnik } 813865f3bb9SMichael Rolnik 814865f3bb9SMichael Rolnik /* 815865f3bb9SMichael Rolnik * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication 816865f3bb9SMichael Rolnik * and shifts the result one bit left. 817865f3bb9SMichael Rolnik */ 818865f3bb9SMichael Rolnik static bool trans_FMULS(DisasContext *ctx, arg_FMULS *a) 819865f3bb9SMichael Rolnik { 820865f3bb9SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 821865f3bb9SMichael Rolnik return true; 822865f3bb9SMichael Rolnik } 823865f3bb9SMichael Rolnik 824865f3bb9SMichael Rolnik TCGv R0 = cpu_r[0]; 825865f3bb9SMichael Rolnik TCGv R1 = cpu_r[1]; 826865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 827865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 828865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 829865f3bb9SMichael Rolnik TCGv t0 = tcg_temp_new_i32(); 830865f3bb9SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 831865f3bb9SMichael Rolnik 832865f3bb9SMichael Rolnik tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 833865f3bb9SMichael Rolnik tcg_gen_ext8s_tl(t1, Rr); /* make Rr full 32 bit signed */ 834865f3bb9SMichael Rolnik tcg_gen_mul_tl(R, t0, t1); /* R = Rd * Rr */ 835865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 836865f3bb9SMichael Rolnik 837865f3bb9SMichael Rolnik /* update status register */ 838865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 839865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 840865f3bb9SMichael Rolnik 841865f3bb9SMichael Rolnik /* update output registers */ 842865f3bb9SMichael Rolnik tcg_gen_shli_tl(R, R, 1); 843865f3bb9SMichael Rolnik tcg_gen_andi_tl(R0, R, 0xff); 844865f3bb9SMichael Rolnik tcg_gen_shri_tl(R1, R, 8); 845865f3bb9SMichael Rolnik tcg_gen_andi_tl(R1, R1, 0xff); 846865f3bb9SMichael Rolnik return true; 847865f3bb9SMichael Rolnik } 848865f3bb9SMichael Rolnik 849865f3bb9SMichael Rolnik /* 850865f3bb9SMichael Rolnik * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication 851865f3bb9SMichael Rolnik * and shifts the result one bit left. 852865f3bb9SMichael Rolnik */ 853865f3bb9SMichael Rolnik static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU *a) 854865f3bb9SMichael Rolnik { 855865f3bb9SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_MUL)) { 856865f3bb9SMichael Rolnik return true; 857865f3bb9SMichael Rolnik } 858865f3bb9SMichael Rolnik 859865f3bb9SMichael Rolnik TCGv R0 = cpu_r[0]; 860865f3bb9SMichael Rolnik TCGv R1 = cpu_r[1]; 861865f3bb9SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 862865f3bb9SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 863865f3bb9SMichael Rolnik TCGv R = tcg_temp_new_i32(); 864865f3bb9SMichael Rolnik TCGv t0 = tcg_temp_new_i32(); 865865f3bb9SMichael Rolnik 866865f3bb9SMichael Rolnik tcg_gen_ext8s_tl(t0, Rd); /* make Rd full 32 bit signed */ 867865f3bb9SMichael Rolnik tcg_gen_mul_tl(R, t0, Rr); /* R = Rd * Rr */ 868865f3bb9SMichael Rolnik tcg_gen_andi_tl(R, R, 0xffff); /* make it 16 bits */ 869865f3bb9SMichael Rolnik 870865f3bb9SMichael Rolnik /* update status register */ 871865f3bb9SMichael Rolnik tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf = R(15) */ 872865f3bb9SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 873865f3bb9SMichael Rolnik 874865f3bb9SMichael Rolnik /* update output registers */ 875865f3bb9SMichael Rolnik tcg_gen_shli_tl(R, R, 1); 876865f3bb9SMichael Rolnik tcg_gen_andi_tl(R0, R, 0xff); 877865f3bb9SMichael Rolnik tcg_gen_shri_tl(R1, R, 8); 878865f3bb9SMichael Rolnik tcg_gen_andi_tl(R1, R1, 0xff); 879865f3bb9SMichael Rolnik return true; 880865f3bb9SMichael Rolnik } 881865f3bb9SMichael Rolnik 882865f3bb9SMichael Rolnik /* 883865f3bb9SMichael Rolnik * The module is an instruction set extension to the AVR CPU, performing 884865f3bb9SMichael Rolnik * DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in 885865f3bb9SMichael Rolnik * the CPU register file, registers R0-R7, where LSB of data is placed in LSB 886865f3bb9SMichael Rolnik * of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (including 887865f3bb9SMichael Rolnik * parity bits) is placed in registers R8- R15, organized in the register file 888865f3bb9SMichael Rolnik * with LSB of key in LSB of R8 and MSB of key in MSB of R15. Executing one DES 889865f3bb9SMichael Rolnik * instruction performs one round in the DES algorithm. Sixteen rounds must be 890865f3bb9SMichael Rolnik * executed in increasing order to form the correct DES ciphertext or 891865f3bb9SMichael Rolnik * plaintext. Intermediate results are stored in the register file (R0-R15) 892865f3bb9SMichael Rolnik * after each DES instruction. The instruction's operand (K) determines which 893865f3bb9SMichael Rolnik * round is executed, and the half carry flag (H) determines whether encryption 894865f3bb9SMichael Rolnik * or decryption is performed. The DES algorithm is described in 895865f3bb9SMichael Rolnik * "Specifications for the Data Encryption Standard" (Federal Information 896865f3bb9SMichael Rolnik * Processing Standards Publication 46). Intermediate results in this 897865f3bb9SMichael Rolnik * implementation differ from the standard because the initial permutation and 898865f3bb9SMichael Rolnik * the inverse initial permutation are performed each iteration. This does not 899865f3bb9SMichael Rolnik * affect the result in the final ciphertext or plaintext, but reduces 900865f3bb9SMichael Rolnik * execution time. 901865f3bb9SMichael Rolnik */ 902865f3bb9SMichael Rolnik static bool trans_DES(DisasContext *ctx, arg_DES *a) 903865f3bb9SMichael Rolnik { 904865f3bb9SMichael Rolnik /* TODO */ 905865f3bb9SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_DES)) { 906865f3bb9SMichael Rolnik return true; 907865f3bb9SMichael Rolnik } 908865f3bb9SMichael Rolnik 909865f3bb9SMichael Rolnik qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); 910865f3bb9SMichael Rolnik 911865f3bb9SMichael Rolnik return true; 912865f3bb9SMichael Rolnik } 9139d316c75SMichael Rolnik 9149d316c75SMichael Rolnik /* 9159d316c75SMichael Rolnik * Branch Instructions 9169d316c75SMichael Rolnik */ 9179d316c75SMichael Rolnik static void gen_jmp_ez(DisasContext *ctx) 9189d316c75SMichael Rolnik { 9199d316c75SMichael Rolnik tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8); 9209d316c75SMichael Rolnik tcg_gen_or_tl(cpu_pc, cpu_pc, cpu_eind); 92193d4d5e4SRichard Henderson ctx->base.is_jmp = DISAS_LOOKUP; 9229d316c75SMichael Rolnik } 9239d316c75SMichael Rolnik 9249d316c75SMichael Rolnik static void gen_jmp_z(DisasContext *ctx) 9259d316c75SMichael Rolnik { 9269d316c75SMichael Rolnik tcg_gen_deposit_tl(cpu_pc, cpu_r[30], cpu_r[31], 8, 8); 92793d4d5e4SRichard Henderson ctx->base.is_jmp = DISAS_LOOKUP; 9289d316c75SMichael Rolnik } 9299d316c75SMichael Rolnik 9309d316c75SMichael Rolnik static void gen_push_ret(DisasContext *ctx, int ret) 9319d316c75SMichael Rolnik { 9329d316c75SMichael Rolnik if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { 9336d27bb55SRichard Henderson TCGv t0 = tcg_constant_i32(ret & 0x0000ff); 9349d316c75SMichael Rolnik 9359d316c75SMichael Rolnik tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB); 9369d316c75SMichael Rolnik tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 9379d316c75SMichael Rolnik } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { 9386d27bb55SRichard Henderson TCGv t0 = tcg_constant_i32(ret & 0x00ffff); 9399d316c75SMichael Rolnik 9409d316c75SMichael Rolnik tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 9419d316c75SMichael Rolnik tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW); 9429d316c75SMichael Rolnik tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 9439d316c75SMichael Rolnik } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { 9446d27bb55SRichard Henderson TCGv lo = tcg_constant_i32(ret & 0x0000ff); 9456d27bb55SRichard Henderson TCGv hi = tcg_constant_i32((ret & 0xffff00) >> 8); 9469d316c75SMichael Rolnik 9479d316c75SMichael Rolnik tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); 9489d316c75SMichael Rolnik tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); 9499d316c75SMichael Rolnik tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); 9509d316c75SMichael Rolnik tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 9519d316c75SMichael Rolnik } 9529d316c75SMichael Rolnik } 9539d316c75SMichael Rolnik 9549d316c75SMichael Rolnik static void gen_pop_ret(DisasContext *ctx, TCGv ret) 9559d316c75SMichael Rolnik { 9569d316c75SMichael Rolnik if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { 9579d316c75SMichael Rolnik tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 9589d316c75SMichael Rolnik tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB); 9599d316c75SMichael Rolnik } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { 9609d316c75SMichael Rolnik tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 9619d316c75SMichael Rolnik tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW); 9629d316c75SMichael Rolnik tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 9639d316c75SMichael Rolnik } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { 9649d316c75SMichael Rolnik TCGv lo = tcg_temp_new_i32(); 9659d316c75SMichael Rolnik TCGv hi = tcg_temp_new_i32(); 9669d316c75SMichael Rolnik 9679d316c75SMichael Rolnik tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 9689d316c75SMichael Rolnik tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); 9699d316c75SMichael Rolnik 9709d316c75SMichael Rolnik tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); 9719d316c75SMichael Rolnik tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); 9729d316c75SMichael Rolnik 9739d316c75SMichael Rolnik tcg_gen_deposit_tl(ret, lo, hi, 8, 16); 9749d316c75SMichael Rolnik } 9759d316c75SMichael Rolnik } 9769d316c75SMichael Rolnik 9779d316c75SMichael Rolnik static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 9789d316c75SMichael Rolnik { 97993d4d5e4SRichard Henderson const TranslationBlock *tb = ctx->base.tb; 9809d316c75SMichael Rolnik 981a50d52bcSRichard Henderson if (translator_use_goto_tb(&ctx->base, dest)) { 9829d316c75SMichael Rolnik tcg_gen_goto_tb(n); 9839d316c75SMichael Rolnik tcg_gen_movi_i32(cpu_pc, dest); 9849d316c75SMichael Rolnik tcg_gen_exit_tb(tb, n); 9859d316c75SMichael Rolnik } else { 9869d316c75SMichael Rolnik tcg_gen_movi_i32(cpu_pc, dest); 987a50d52bcSRichard Henderson tcg_gen_lookup_and_goto_ptr(); 988a50d52bcSRichard Henderson } 98993d4d5e4SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 9909d316c75SMichael Rolnik } 9919d316c75SMichael Rolnik 9929d316c75SMichael Rolnik /* 9939d316c75SMichael Rolnik * Relative jump to an address within PC - 2K +1 and PC + 2K (words). For 9949d316c75SMichael Rolnik * AVR microcontrollers with Program memory not exceeding 4K words (8KB) this 9959d316c75SMichael Rolnik * instruction can address the entire memory from every address location. See 9969d316c75SMichael Rolnik * also JMP. 9979d316c75SMichael Rolnik */ 9989d316c75SMichael Rolnik static bool trans_RJMP(DisasContext *ctx, arg_RJMP *a) 9999d316c75SMichael Rolnik { 10009d316c75SMichael Rolnik int dst = ctx->npc + a->imm; 10019d316c75SMichael Rolnik 10029d316c75SMichael Rolnik gen_goto_tb(ctx, 0, dst); 10039d316c75SMichael Rolnik 10049d316c75SMichael Rolnik return true; 10059d316c75SMichael Rolnik } 10069d316c75SMichael Rolnik 10079d316c75SMichael Rolnik /* 10089d316c75SMichael Rolnik * Indirect jump to the address pointed to by the Z (16 bits) Pointer 10099d316c75SMichael Rolnik * Register in the Register File. The Z-pointer Register is 16 bits wide and 10109d316c75SMichael Rolnik * allows jump within the lowest 64K words (128KB) section of Program memory. 10119d316c75SMichael Rolnik * This instruction is not available in all devices. Refer to the device 10129d316c75SMichael Rolnik * specific instruction set summary. 10139d316c75SMichael Rolnik */ 10149d316c75SMichael Rolnik static bool trans_IJMP(DisasContext *ctx, arg_IJMP *a) 10159d316c75SMichael Rolnik { 10169d316c75SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) { 10179d316c75SMichael Rolnik return true; 10189d316c75SMichael Rolnik } 10199d316c75SMichael Rolnik 10209d316c75SMichael Rolnik gen_jmp_z(ctx); 10219d316c75SMichael Rolnik 10229d316c75SMichael Rolnik return true; 10239d316c75SMichael Rolnik } 10249d316c75SMichael Rolnik 10259d316c75SMichael Rolnik /* 10269d316c75SMichael Rolnik * Indirect jump to the address pointed to by the Z (16 bits) Pointer 10279d316c75SMichael Rolnik * Register in the Register File and the EIND Register in the I/O space. This 10289d316c75SMichael Rolnik * instruction allows for indirect jumps to the entire 4M (words) Program 10299d316c75SMichael Rolnik * memory space. See also IJMP. This instruction is not available in all 10309d316c75SMichael Rolnik * devices. Refer to the device specific instruction set summary. 10319d316c75SMichael Rolnik */ 10329d316c75SMichael Rolnik static bool trans_EIJMP(DisasContext *ctx, arg_EIJMP *a) 10339d316c75SMichael Rolnik { 10349d316c75SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) { 10359d316c75SMichael Rolnik return true; 10369d316c75SMichael Rolnik } 10379d316c75SMichael Rolnik 10389d316c75SMichael Rolnik gen_jmp_ez(ctx); 10399d316c75SMichael Rolnik return true; 10409d316c75SMichael Rolnik } 10419d316c75SMichael Rolnik 10429d316c75SMichael Rolnik /* 10439d316c75SMichael Rolnik * Jump to an address within the entire 4M (words) Program memory. See also 10449d316c75SMichael Rolnik * RJMP. This instruction is not available in all devices. Refer to the device 10459d316c75SMichael Rolnik * specific instruction set summary.0 10469d316c75SMichael Rolnik */ 10479d316c75SMichael Rolnik static bool trans_JMP(DisasContext *ctx, arg_JMP *a) 10489d316c75SMichael Rolnik { 10499d316c75SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) { 10509d316c75SMichael Rolnik return true; 10519d316c75SMichael Rolnik } 10529d316c75SMichael Rolnik 10539d316c75SMichael Rolnik gen_goto_tb(ctx, 0, a->imm); 10549d316c75SMichael Rolnik 10559d316c75SMichael Rolnik return true; 10569d316c75SMichael Rolnik } 10579d316c75SMichael Rolnik 10589d316c75SMichael Rolnik /* 10599d316c75SMichael Rolnik * Relative call to an address within PC - 2K + 1 and PC + 2K (words). The 10609d316c75SMichael Rolnik * return address (the instruction after the RCALL) is stored onto the Stack. 10619d316c75SMichael Rolnik * See also CALL. For AVR microcontrollers with Program memory not exceeding 4K 10629d316c75SMichael Rolnik * words (8KB) this instruction can address the entire memory from every 10639d316c75SMichael Rolnik * address location. The Stack Pointer uses a post-decrement scheme during 10649d316c75SMichael Rolnik * RCALL. 10659d316c75SMichael Rolnik */ 10669d316c75SMichael Rolnik static bool trans_RCALL(DisasContext *ctx, arg_RCALL *a) 10679d316c75SMichael Rolnik { 10689d316c75SMichael Rolnik int ret = ctx->npc; 10699d316c75SMichael Rolnik int dst = ctx->npc + a->imm; 10709d316c75SMichael Rolnik 10719d316c75SMichael Rolnik gen_push_ret(ctx, ret); 10729d316c75SMichael Rolnik gen_goto_tb(ctx, 0, dst); 10739d316c75SMichael Rolnik 10749d316c75SMichael Rolnik return true; 10759d316c75SMichael Rolnik } 10769d316c75SMichael Rolnik 10779d316c75SMichael Rolnik /* 10789d316c75SMichael Rolnik * Calls to a subroutine within the entire 4M (words) Program memory. The 10799d316c75SMichael Rolnik * return address (to the instruction after the CALL) will be stored onto the 10809d316c75SMichael Rolnik * Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during 10819d316c75SMichael Rolnik * CALL. This instruction is not available in all devices. Refer to the device 10829d316c75SMichael Rolnik * specific instruction set summary. 10839d316c75SMichael Rolnik */ 10849d316c75SMichael Rolnik static bool trans_ICALL(DisasContext *ctx, arg_ICALL *a) 10859d316c75SMichael Rolnik { 10869d316c75SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_IJMP_ICALL)) { 10879d316c75SMichael Rolnik return true; 10889d316c75SMichael Rolnik } 10899d316c75SMichael Rolnik 10909d316c75SMichael Rolnik int ret = ctx->npc; 10919d316c75SMichael Rolnik 10929d316c75SMichael Rolnik gen_push_ret(ctx, ret); 10939d316c75SMichael Rolnik gen_jmp_z(ctx); 10949d316c75SMichael Rolnik 10959d316c75SMichael Rolnik return true; 10969d316c75SMichael Rolnik } 10979d316c75SMichael Rolnik 10989d316c75SMichael Rolnik /* 10999d316c75SMichael Rolnik * Indirect call of a subroutine pointed to by the Z (16 bits) Pointer 11009d316c75SMichael Rolnik * Register in the Register File and the EIND Register in the I/O space. This 11019d316c75SMichael Rolnik * instruction allows for indirect calls to the entire 4M (words) Program 11029d316c75SMichael Rolnik * memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme 11039d316c75SMichael Rolnik * during EICALL. This instruction is not available in all devices. Refer to 11049d316c75SMichael Rolnik * the device specific instruction set summary. 11059d316c75SMichael Rolnik */ 11069d316c75SMichael Rolnik static bool trans_EICALL(DisasContext *ctx, arg_EICALL *a) 11079d316c75SMichael Rolnik { 11089d316c75SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_EIJMP_EICALL)) { 11099d316c75SMichael Rolnik return true; 11109d316c75SMichael Rolnik } 11119d316c75SMichael Rolnik 11129d316c75SMichael Rolnik int ret = ctx->npc; 11139d316c75SMichael Rolnik 11149d316c75SMichael Rolnik gen_push_ret(ctx, ret); 11159d316c75SMichael Rolnik gen_jmp_ez(ctx); 11169d316c75SMichael Rolnik return true; 11179d316c75SMichael Rolnik } 11189d316c75SMichael Rolnik 11199d316c75SMichael Rolnik /* 11209d316c75SMichael Rolnik * Calls to a subroutine within the entire Program memory. The return 11219d316c75SMichael Rolnik * address (to the instruction after the CALL) will be stored onto the Stack. 11229d316c75SMichael Rolnik * (See also RCALL). The Stack Pointer uses a post-decrement scheme during 11239d316c75SMichael Rolnik * CALL. This instruction is not available in all devices. Refer to the device 11249d316c75SMichael Rolnik * specific instruction set summary. 11259d316c75SMichael Rolnik */ 11269d316c75SMichael Rolnik static bool trans_CALL(DisasContext *ctx, arg_CALL *a) 11279d316c75SMichael Rolnik { 11289d316c75SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_JMP_CALL)) { 11299d316c75SMichael Rolnik return true; 11309d316c75SMichael Rolnik } 11319d316c75SMichael Rolnik 11329d316c75SMichael Rolnik int Imm = a->imm; 11339d316c75SMichael Rolnik int ret = ctx->npc; 11349d316c75SMichael Rolnik 11359d316c75SMichael Rolnik gen_push_ret(ctx, ret); 11369d316c75SMichael Rolnik gen_goto_tb(ctx, 0, Imm); 11379d316c75SMichael Rolnik 11389d316c75SMichael Rolnik return true; 11399d316c75SMichael Rolnik } 11409d316c75SMichael Rolnik 11419d316c75SMichael Rolnik /* 11429d316c75SMichael Rolnik * Returns from subroutine. The return address is loaded from the STACK. 11439d316c75SMichael Rolnik * The Stack Pointer uses a preincrement scheme during RET. 11449d316c75SMichael Rolnik */ 11459d316c75SMichael Rolnik static bool trans_RET(DisasContext *ctx, arg_RET *a) 11469d316c75SMichael Rolnik { 11479d316c75SMichael Rolnik gen_pop_ret(ctx, cpu_pc); 11489d316c75SMichael Rolnik 114993d4d5e4SRichard Henderson ctx->base.is_jmp = DISAS_LOOKUP; 11509d316c75SMichael Rolnik return true; 11519d316c75SMichael Rolnik } 11529d316c75SMichael Rolnik 11539d316c75SMichael Rolnik /* 11549d316c75SMichael Rolnik * Returns from interrupt. The return address is loaded from the STACK and 11559d316c75SMichael Rolnik * the Global Interrupt Flag is set. Note that the Status Register is not 11569d316c75SMichael Rolnik * automatically stored when entering an interrupt routine, and it is not 11579d316c75SMichael Rolnik * restored when returning from an interrupt routine. This must be handled by 11589d316c75SMichael Rolnik * the application program. The Stack Pointer uses a pre-increment scheme 11599d316c75SMichael Rolnik * during RETI. 11609d316c75SMichael Rolnik */ 11619d316c75SMichael Rolnik static bool trans_RETI(DisasContext *ctx, arg_RETI *a) 11629d316c75SMichael Rolnik { 11639d316c75SMichael Rolnik gen_pop_ret(ctx, cpu_pc); 11649d316c75SMichael Rolnik tcg_gen_movi_tl(cpu_If, 1); 11659d316c75SMichael Rolnik 11669d316c75SMichael Rolnik /* Need to return to main loop to re-evaluate interrupts. */ 116793d4d5e4SRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 11689d316c75SMichael Rolnik return true; 11699d316c75SMichael Rolnik } 11709d316c75SMichael Rolnik 11719d316c75SMichael Rolnik /* 11729d316c75SMichael Rolnik * This instruction performs a compare between two registers Rd and Rr, and 11739d316c75SMichael Rolnik * skips the next instruction if Rd = Rr. 11749d316c75SMichael Rolnik */ 11759d316c75SMichael Rolnik static bool trans_CPSE(DisasContext *ctx, arg_CPSE *a) 11769d316c75SMichael Rolnik { 11779d316c75SMichael Rolnik ctx->skip_cond = TCG_COND_EQ; 11789d316c75SMichael Rolnik ctx->skip_var0 = cpu_r[a->rd]; 11799d316c75SMichael Rolnik ctx->skip_var1 = cpu_r[a->rr]; 11809d316c75SMichael Rolnik return true; 11819d316c75SMichael Rolnik } 11829d316c75SMichael Rolnik 11839d316c75SMichael Rolnik /* 11849d316c75SMichael Rolnik * This instruction performs a compare between two registers Rd and Rr. 11859d316c75SMichael Rolnik * None of the registers are changed. All conditional branches can be used 11869d316c75SMichael Rolnik * after this instruction. 11879d316c75SMichael Rolnik */ 11889d316c75SMichael Rolnik static bool trans_CP(DisasContext *ctx, arg_CP *a) 11899d316c75SMichael Rolnik { 11909d316c75SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 11919d316c75SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 11929d316c75SMichael Rolnik TCGv R = tcg_temp_new_i32(); 11939d316c75SMichael Rolnik 11949d316c75SMichael Rolnik tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 11959d316c75SMichael Rolnik tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 11969d316c75SMichael Rolnik 11979d316c75SMichael Rolnik /* update status register */ 11989d316c75SMichael Rolnik gen_sub_CHf(R, Rd, Rr); 11999d316c75SMichael Rolnik gen_sub_Vf(R, Rd, Rr); 12009d316c75SMichael Rolnik gen_ZNSf(R); 12019d316c75SMichael Rolnik return true; 12029d316c75SMichael Rolnik } 12039d316c75SMichael Rolnik 12049d316c75SMichael Rolnik /* 12059d316c75SMichael Rolnik * This instruction performs a compare between two registers Rd and Rr and 12069d316c75SMichael Rolnik * also takes into account the previous carry. None of the registers are 12079d316c75SMichael Rolnik * changed. All conditional branches can be used after this instruction. 12089d316c75SMichael Rolnik */ 12099d316c75SMichael Rolnik static bool trans_CPC(DisasContext *ctx, arg_CPC *a) 12109d316c75SMichael Rolnik { 12119d316c75SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 12129d316c75SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 12139d316c75SMichael Rolnik TCGv R = tcg_temp_new_i32(); 12146d27bb55SRichard Henderson TCGv zero = tcg_constant_i32(0); 12159d316c75SMichael Rolnik 12169d316c75SMichael Rolnik tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */ 12179d316c75SMichael Rolnik tcg_gen_sub_tl(R, R, cpu_Cf); 12189d316c75SMichael Rolnik tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 12199d316c75SMichael Rolnik /* update status register */ 12209d316c75SMichael Rolnik gen_sub_CHf(R, Rd, Rr); 12219d316c75SMichael Rolnik gen_sub_Vf(R, Rd, Rr); 12229d316c75SMichael Rolnik gen_NSf(R); 12239d316c75SMichael Rolnik 12249d316c75SMichael Rolnik /* 12259d316c75SMichael Rolnik * Previous value remains unchanged when the result is zero; 12269d316c75SMichael Rolnik * cleared otherwise. 12279d316c75SMichael Rolnik */ 12289d316c75SMichael Rolnik tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); 12299d316c75SMichael Rolnik return true; 12309d316c75SMichael Rolnik } 12319d316c75SMichael Rolnik 12329d316c75SMichael Rolnik /* 12339d316c75SMichael Rolnik * This instruction performs a compare between register Rd and a constant. 12349d316c75SMichael Rolnik * The register is not changed. All conditional branches can be used after this 12359d316c75SMichael Rolnik * instruction. 12369d316c75SMichael Rolnik */ 12379d316c75SMichael Rolnik static bool trans_CPI(DisasContext *ctx, arg_CPI *a) 12389d316c75SMichael Rolnik { 12399d316c75SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 12409d316c75SMichael Rolnik int Imm = a->imm; 12416d27bb55SRichard Henderson TCGv Rr = tcg_constant_i32(Imm); 12429d316c75SMichael Rolnik TCGv R = tcg_temp_new_i32(); 12439d316c75SMichael Rolnik 12449d316c75SMichael Rolnik tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */ 12459d316c75SMichael Rolnik tcg_gen_andi_tl(R, R, 0xff); /* make it 8 bits */ 12469d316c75SMichael Rolnik 12479d316c75SMichael Rolnik /* update status register */ 12489d316c75SMichael Rolnik gen_sub_CHf(R, Rd, Rr); 12499d316c75SMichael Rolnik gen_sub_Vf(R, Rd, Rr); 12509d316c75SMichael Rolnik gen_ZNSf(R); 12519d316c75SMichael Rolnik return true; 12529d316c75SMichael Rolnik } 12539d316c75SMichael Rolnik 12549d316c75SMichael Rolnik /* 12559d316c75SMichael Rolnik * This instruction tests a single bit in a register and skips the next 12569d316c75SMichael Rolnik * instruction if the bit is cleared. 12579d316c75SMichael Rolnik */ 12589d316c75SMichael Rolnik static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a) 12599d316c75SMichael Rolnik { 12609d316c75SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 12619d316c75SMichael Rolnik 12629d316c75SMichael Rolnik ctx->skip_cond = TCG_COND_EQ; 12639d316c75SMichael Rolnik ctx->skip_var0 = tcg_temp_new(); 12649d316c75SMichael Rolnik 12659d316c75SMichael Rolnik tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); 12669d316c75SMichael Rolnik return true; 12679d316c75SMichael Rolnik } 12689d316c75SMichael Rolnik 12699d316c75SMichael Rolnik /* 12709d316c75SMichael Rolnik * This instruction tests a single bit in a register and skips the next 12719d316c75SMichael Rolnik * instruction if the bit is set. 12729d316c75SMichael Rolnik */ 12739d316c75SMichael Rolnik static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) 12749d316c75SMichael Rolnik { 12759d316c75SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 12769d316c75SMichael Rolnik 12779d316c75SMichael Rolnik ctx->skip_cond = TCG_COND_NE; 12789d316c75SMichael Rolnik ctx->skip_var0 = tcg_temp_new(); 12799d316c75SMichael Rolnik 12809d316c75SMichael Rolnik tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); 12819d316c75SMichael Rolnik return true; 12829d316c75SMichael Rolnik } 12839d316c75SMichael Rolnik 12849d316c75SMichael Rolnik /* 12859d316c75SMichael Rolnik * This instruction tests a single bit in an I/O Register and skips the 12869d316c75SMichael Rolnik * next instruction if the bit is cleared. This instruction operates on the 12879d316c75SMichael Rolnik * lower 32 I/O Registers -- addresses 0-31. 12889d316c75SMichael Rolnik */ 12899d316c75SMichael Rolnik static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) 12909d316c75SMichael Rolnik { 1291353c18dcSRichard Henderson TCGv data = tcg_temp_new_i32(); 1292353c18dcSRichard Henderson TCGv port = tcg_constant_i32(a->reg); 12939d316c75SMichael Rolnik 1294353c18dcSRichard Henderson gen_helper_inb(data, cpu_env, port); 1295353c18dcSRichard Henderson tcg_gen_andi_tl(data, data, 1 << a->bit); 12969d316c75SMichael Rolnik ctx->skip_cond = TCG_COND_EQ; 1297353c18dcSRichard Henderson ctx->skip_var0 = data; 12989d316c75SMichael Rolnik 12999d316c75SMichael Rolnik return true; 13009d316c75SMichael Rolnik } 13019d316c75SMichael Rolnik 13029d316c75SMichael Rolnik /* 13039d316c75SMichael Rolnik * This instruction tests a single bit in an I/O Register and skips the 13049d316c75SMichael Rolnik * next instruction if the bit is set. This instruction operates on the lower 13059d316c75SMichael Rolnik * 32 I/O Registers -- addresses 0-31. 13069d316c75SMichael Rolnik */ 13079d316c75SMichael Rolnik static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) 13089d316c75SMichael Rolnik { 1309353c18dcSRichard Henderson TCGv data = tcg_temp_new_i32(); 1310353c18dcSRichard Henderson TCGv port = tcg_constant_i32(a->reg); 13119d316c75SMichael Rolnik 1312353c18dcSRichard Henderson gen_helper_inb(data, cpu_env, port); 1313353c18dcSRichard Henderson tcg_gen_andi_tl(data, data, 1 << a->bit); 13149d316c75SMichael Rolnik ctx->skip_cond = TCG_COND_NE; 1315353c18dcSRichard Henderson ctx->skip_var0 = data; 13169d316c75SMichael Rolnik 13179d316c75SMichael Rolnik return true; 13189d316c75SMichael Rolnik } 13199d316c75SMichael Rolnik 13209d316c75SMichael Rolnik /* 13219d316c75SMichael Rolnik * Conditional relative branch. Tests a single bit in SREG and branches 13229d316c75SMichael Rolnik * relatively to PC if the bit is cleared. This instruction branches relatively 13239d316c75SMichael Rolnik * to PC in either direction (PC - 63 < = destination <= PC + 64). The 13249d316c75SMichael Rolnik * parameter k is the offset from PC and is represented in two's complement 13259d316c75SMichael Rolnik * form. 13269d316c75SMichael Rolnik */ 13279d316c75SMichael Rolnik static bool trans_BRBC(DisasContext *ctx, arg_BRBC *a) 13289d316c75SMichael Rolnik { 13299d316c75SMichael Rolnik TCGLabel *not_taken = gen_new_label(); 13309d316c75SMichael Rolnik 13319d316c75SMichael Rolnik TCGv var; 13329d316c75SMichael Rolnik 13339d316c75SMichael Rolnik switch (a->bit) { 13349d316c75SMichael Rolnik case 0x00: 13359d316c75SMichael Rolnik var = cpu_Cf; 13369d316c75SMichael Rolnik break; 13379d316c75SMichael Rolnik case 0x01: 13389d316c75SMichael Rolnik var = cpu_Zf; 13399d316c75SMichael Rolnik break; 13409d316c75SMichael Rolnik case 0x02: 13419d316c75SMichael Rolnik var = cpu_Nf; 13429d316c75SMichael Rolnik break; 13439d316c75SMichael Rolnik case 0x03: 13449d316c75SMichael Rolnik var = cpu_Vf; 13459d316c75SMichael Rolnik break; 13469d316c75SMichael Rolnik case 0x04: 13479d316c75SMichael Rolnik var = cpu_Sf; 13489d316c75SMichael Rolnik break; 13499d316c75SMichael Rolnik case 0x05: 13509d316c75SMichael Rolnik var = cpu_Hf; 13519d316c75SMichael Rolnik break; 13529d316c75SMichael Rolnik case 0x06: 13539d316c75SMichael Rolnik var = cpu_Tf; 13549d316c75SMichael Rolnik break; 13559d316c75SMichael Rolnik case 0x07: 13569d316c75SMichael Rolnik var = cpu_If; 13579d316c75SMichael Rolnik break; 13589d316c75SMichael Rolnik default: 13599d316c75SMichael Rolnik g_assert_not_reached(); 13609d316c75SMichael Rolnik } 13619d316c75SMichael Rolnik 13629d316c75SMichael Rolnik tcg_gen_brcondi_i32(TCG_COND_NE, var, 0, not_taken); 13639d316c75SMichael Rolnik gen_goto_tb(ctx, 0, ctx->npc + a->imm); 13649d316c75SMichael Rolnik gen_set_label(not_taken); 13659d316c75SMichael Rolnik 136693d4d5e4SRichard Henderson ctx->base.is_jmp = DISAS_CHAIN; 13679d316c75SMichael Rolnik return true; 13689d316c75SMichael Rolnik } 13699d316c75SMichael Rolnik 13709d316c75SMichael Rolnik /* 13719d316c75SMichael Rolnik * Conditional relative branch. Tests a single bit in SREG and branches 13729d316c75SMichael Rolnik * relatively to PC if the bit is set. This instruction branches relatively to 13739d316c75SMichael Rolnik * PC in either direction (PC - 63 < = destination <= PC + 64). The parameter k 13749d316c75SMichael Rolnik * is the offset from PC and is represented in two's complement form. 13759d316c75SMichael Rolnik */ 13769d316c75SMichael Rolnik static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a) 13779d316c75SMichael Rolnik { 13789d316c75SMichael Rolnik TCGLabel *not_taken = gen_new_label(); 13799d316c75SMichael Rolnik 13809d316c75SMichael Rolnik TCGv var; 13819d316c75SMichael Rolnik 13829d316c75SMichael Rolnik switch (a->bit) { 13839d316c75SMichael Rolnik case 0x00: 13849d316c75SMichael Rolnik var = cpu_Cf; 13859d316c75SMichael Rolnik break; 13869d316c75SMichael Rolnik case 0x01: 13879d316c75SMichael Rolnik var = cpu_Zf; 13889d316c75SMichael Rolnik break; 13899d316c75SMichael Rolnik case 0x02: 13909d316c75SMichael Rolnik var = cpu_Nf; 13919d316c75SMichael Rolnik break; 13929d316c75SMichael Rolnik case 0x03: 13939d316c75SMichael Rolnik var = cpu_Vf; 13949d316c75SMichael Rolnik break; 13959d316c75SMichael Rolnik case 0x04: 13969d316c75SMichael Rolnik var = cpu_Sf; 13979d316c75SMichael Rolnik break; 13989d316c75SMichael Rolnik case 0x05: 13999d316c75SMichael Rolnik var = cpu_Hf; 14009d316c75SMichael Rolnik break; 14019d316c75SMichael Rolnik case 0x06: 14029d316c75SMichael Rolnik var = cpu_Tf; 14039d316c75SMichael Rolnik break; 14049d316c75SMichael Rolnik case 0x07: 14059d316c75SMichael Rolnik var = cpu_If; 14069d316c75SMichael Rolnik break; 14079d316c75SMichael Rolnik default: 14089d316c75SMichael Rolnik g_assert_not_reached(); 14099d316c75SMichael Rolnik } 14109d316c75SMichael Rolnik 14119d316c75SMichael Rolnik tcg_gen_brcondi_i32(TCG_COND_EQ, var, 0, not_taken); 14129d316c75SMichael Rolnik gen_goto_tb(ctx, 0, ctx->npc + a->imm); 14139d316c75SMichael Rolnik gen_set_label(not_taken); 14149d316c75SMichael Rolnik 141593d4d5e4SRichard Henderson ctx->base.is_jmp = DISAS_CHAIN; 14169d316c75SMichael Rolnik return true; 14179d316c75SMichael Rolnik } 14189732b024SMichael Rolnik 14199732b024SMichael Rolnik /* 14209732b024SMichael Rolnik * Data Transfer Instructions 14219732b024SMichael Rolnik */ 14229732b024SMichael Rolnik 14239732b024SMichael Rolnik /* 14249732b024SMichael Rolnik * in the gen_set_addr & gen_get_addr functions 14259732b024SMichael Rolnik * H assumed to be in 0x00ff0000 format 14269732b024SMichael Rolnik * M assumed to be in 0x000000ff format 14279732b024SMichael Rolnik * L assumed to be in 0x000000ff format 14289732b024SMichael Rolnik */ 14299732b024SMichael Rolnik static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L) 14309732b024SMichael Rolnik { 14319732b024SMichael Rolnik 14329732b024SMichael Rolnik tcg_gen_andi_tl(L, addr, 0x000000ff); 14339732b024SMichael Rolnik 14349732b024SMichael Rolnik tcg_gen_andi_tl(M, addr, 0x0000ff00); 14359732b024SMichael Rolnik tcg_gen_shri_tl(M, M, 8); 14369732b024SMichael Rolnik 14379732b024SMichael Rolnik tcg_gen_andi_tl(H, addr, 0x00ff0000); 14389732b024SMichael Rolnik } 14399732b024SMichael Rolnik 14409732b024SMichael Rolnik static void gen_set_xaddr(TCGv addr) 14419732b024SMichael Rolnik { 14429732b024SMichael Rolnik gen_set_addr(addr, cpu_rampX, cpu_r[27], cpu_r[26]); 14439732b024SMichael Rolnik } 14449732b024SMichael Rolnik 14459732b024SMichael Rolnik static void gen_set_yaddr(TCGv addr) 14469732b024SMichael Rolnik { 14479732b024SMichael Rolnik gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]); 14489732b024SMichael Rolnik } 14499732b024SMichael Rolnik 14509732b024SMichael Rolnik static void gen_set_zaddr(TCGv addr) 14519732b024SMichael Rolnik { 14529732b024SMichael Rolnik gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]); 14539732b024SMichael Rolnik } 14549732b024SMichael Rolnik 14559732b024SMichael Rolnik static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L) 14569732b024SMichael Rolnik { 14579732b024SMichael Rolnik TCGv addr = tcg_temp_new_i32(); 14589732b024SMichael Rolnik 14599732b024SMichael Rolnik tcg_gen_deposit_tl(addr, M, H, 8, 8); 14609732b024SMichael Rolnik tcg_gen_deposit_tl(addr, L, addr, 8, 16); 14619732b024SMichael Rolnik 14629732b024SMichael Rolnik return addr; 14639732b024SMichael Rolnik } 14649732b024SMichael Rolnik 14659732b024SMichael Rolnik static TCGv gen_get_xaddr(void) 14669732b024SMichael Rolnik { 14679732b024SMichael Rolnik return gen_get_addr(cpu_rampX, cpu_r[27], cpu_r[26]); 14689732b024SMichael Rolnik } 14699732b024SMichael Rolnik 14709732b024SMichael Rolnik static TCGv gen_get_yaddr(void) 14719732b024SMichael Rolnik { 14729732b024SMichael Rolnik return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]); 14739732b024SMichael Rolnik } 14749732b024SMichael Rolnik 14759732b024SMichael Rolnik static TCGv gen_get_zaddr(void) 14769732b024SMichael Rolnik { 14779732b024SMichael Rolnik return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]); 14789732b024SMichael Rolnik } 14799732b024SMichael Rolnik 14809732b024SMichael Rolnik /* 14819732b024SMichael Rolnik * Load one byte indirect from data space to register and stores an clear 14829732b024SMichael Rolnik * the bits in data space specified by the register. The instruction can only 14839732b024SMichael Rolnik * be used towards internal SRAM. The data location is pointed to by the Z (16 14849732b024SMichael Rolnik * bits) Pointer Register in the Register File. Memory access is limited to the 14859732b024SMichael Rolnik * current data segment of 64KB. To access another data segment in devices with 14869732b024SMichael Rolnik * more than 64KB data space, the RAMPZ in register in the I/O area has to be 14879732b024SMichael Rolnik * changed. The Z-pointer Register is left unchanged by the operation. This 14889732b024SMichael Rolnik * instruction is especially suited for clearing status bits stored in SRAM. 14899732b024SMichael Rolnik */ 14909732b024SMichael Rolnik static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) 14919732b024SMichael Rolnik { 149293d4d5e4SRichard Henderson if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { 14939732b024SMichael Rolnik gen_helper_fullwr(cpu_env, data, addr); 14949732b024SMichael Rolnik } else { 1495*8b4506e5SRichard Henderson tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB); 14969732b024SMichael Rolnik } 14979732b024SMichael Rolnik } 14989732b024SMichael Rolnik 14999732b024SMichael Rolnik static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) 15009732b024SMichael Rolnik { 150193d4d5e4SRichard Henderson if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { 15029732b024SMichael Rolnik gen_helper_fullrd(data, cpu_env, addr); 15039732b024SMichael Rolnik } else { 1504*8b4506e5SRichard Henderson tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); 15059732b024SMichael Rolnik } 15069732b024SMichael Rolnik } 15079732b024SMichael Rolnik 15089732b024SMichael Rolnik /* 15099732b024SMichael Rolnik * This instruction makes a copy of one register into another. The source 15109732b024SMichael Rolnik * register Rr is left unchanged, while the destination register Rd is loaded 15119732b024SMichael Rolnik * with a copy of Rr. 15129732b024SMichael Rolnik */ 15139732b024SMichael Rolnik static bool trans_MOV(DisasContext *ctx, arg_MOV *a) 15149732b024SMichael Rolnik { 15159732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 15169732b024SMichael Rolnik TCGv Rr = cpu_r[a->rr]; 15179732b024SMichael Rolnik 15189732b024SMichael Rolnik tcg_gen_mov_tl(Rd, Rr); 15199732b024SMichael Rolnik 15209732b024SMichael Rolnik return true; 15219732b024SMichael Rolnik } 15229732b024SMichael Rolnik 15239732b024SMichael Rolnik /* 15249732b024SMichael Rolnik * This instruction makes a copy of one register pair into another register 15259732b024SMichael Rolnik * pair. The source register pair Rr+1:Rr is left unchanged, while the 15269732b024SMichael Rolnik * destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr. This 15279732b024SMichael Rolnik * instruction is not available in all devices. Refer to the device specific 15289732b024SMichael Rolnik * instruction set summary. 15299732b024SMichael Rolnik */ 15309732b024SMichael Rolnik static bool trans_MOVW(DisasContext *ctx, arg_MOVW *a) 15319732b024SMichael Rolnik { 15329732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_MOVW)) { 15339732b024SMichael Rolnik return true; 15349732b024SMichael Rolnik } 15359732b024SMichael Rolnik 15369732b024SMichael Rolnik TCGv RdL = cpu_r[a->rd]; 15379732b024SMichael Rolnik TCGv RdH = cpu_r[a->rd + 1]; 15389732b024SMichael Rolnik TCGv RrL = cpu_r[a->rr]; 15399732b024SMichael Rolnik TCGv RrH = cpu_r[a->rr + 1]; 15409732b024SMichael Rolnik 15419732b024SMichael Rolnik tcg_gen_mov_tl(RdH, RrH); 15429732b024SMichael Rolnik tcg_gen_mov_tl(RdL, RrL); 15439732b024SMichael Rolnik 15449732b024SMichael Rolnik return true; 15459732b024SMichael Rolnik } 15469732b024SMichael Rolnik 15479732b024SMichael Rolnik /* 15489732b024SMichael Rolnik * Loads an 8 bit constant directly to register 16 to 31. 15499732b024SMichael Rolnik */ 15509732b024SMichael Rolnik static bool trans_LDI(DisasContext *ctx, arg_LDI *a) 15519732b024SMichael Rolnik { 15529732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 15539732b024SMichael Rolnik int imm = a->imm; 15549732b024SMichael Rolnik 15559732b024SMichael Rolnik tcg_gen_movi_tl(Rd, imm); 15569732b024SMichael Rolnik 15579732b024SMichael Rolnik return true; 15589732b024SMichael Rolnik } 15599732b024SMichael Rolnik 15609732b024SMichael Rolnik /* 15619732b024SMichael Rolnik * Loads one byte from the data space to a register. For parts with SRAM, 15629732b024SMichael Rolnik * the data space consists of the Register File, I/O memory and internal SRAM 15639732b024SMichael Rolnik * (and external SRAM if applicable). For parts without SRAM, the data space 15649732b024SMichael Rolnik * consists of the register file only. The EEPROM has a separate address space. 15659732b024SMichael Rolnik * A 16-bit address must be supplied. Memory access is limited to the current 15669732b024SMichael Rolnik * data segment of 64KB. The LDS instruction uses the RAMPD Register to access 15679732b024SMichael Rolnik * memory above 64KB. To access another data segment in devices with more than 15689732b024SMichael Rolnik * 64KB data space, the RAMPD in register in the I/O area has to be changed. 15699732b024SMichael Rolnik * This instruction is not available in all devices. Refer to the device 15709732b024SMichael Rolnik * specific instruction set summary. 15719732b024SMichael Rolnik */ 15729732b024SMichael Rolnik static bool trans_LDS(DisasContext *ctx, arg_LDS *a) 15739732b024SMichael Rolnik { 15749732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 15759732b024SMichael Rolnik TCGv addr = tcg_temp_new_i32(); 15769732b024SMichael Rolnik TCGv H = cpu_rampD; 15779732b024SMichael Rolnik a->imm = next_word(ctx); 15789732b024SMichael Rolnik 15799732b024SMichael Rolnik tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ 15809732b024SMichael Rolnik tcg_gen_shli_tl(addr, addr, 16); 15819732b024SMichael Rolnik tcg_gen_ori_tl(addr, addr, a->imm); 15829732b024SMichael Rolnik 15839732b024SMichael Rolnik gen_data_load(ctx, Rd, addr); 15849732b024SMichael Rolnik return true; 15859732b024SMichael Rolnik } 15869732b024SMichael Rolnik 15879732b024SMichael Rolnik /* 15889732b024SMichael Rolnik * Loads one byte indirect from the data space to a register. For parts 15899732b024SMichael Rolnik * with SRAM, the data space consists of the Register File, I/O memory and 15909732b024SMichael Rolnik * internal SRAM (and external SRAM if applicable). For parts without SRAM, the 15919732b024SMichael Rolnik * data space consists of the Register File only. In some parts the Flash 15929732b024SMichael Rolnik * Memory has been mapped to the data space and can be read using this command. 15939732b024SMichael Rolnik * The EEPROM has a separate address space. The data location is pointed to by 15949732b024SMichael Rolnik * the X (16 bits) Pointer Register in the Register File. Memory access is 15959732b024SMichael Rolnik * limited to the current data segment of 64KB. To access another data segment 15969732b024SMichael Rolnik * in devices with more than 64KB data space, the RAMPX in register in the I/O 15979732b024SMichael Rolnik * area has to be changed. The X-pointer Register can either be left unchanged 15989732b024SMichael Rolnik * by the operation, or it can be post-incremented or predecremented. These 15999732b024SMichael Rolnik * features are especially suited for accessing arrays, tables, and Stack 16009732b024SMichael Rolnik * Pointer usage of the X-pointer Register. Note that only the low byte of the 16019732b024SMichael Rolnik * X-pointer is updated in devices with no more than 256 bytes data space. For 16029732b024SMichael Rolnik * such devices, the high byte of the pointer is not used by this instruction 16039732b024SMichael Rolnik * and can be used for other purposes. The RAMPX Register in the I/O area is 16049732b024SMichael Rolnik * updated in parts with more than 64KB data space or more than 64KB Program 16059732b024SMichael Rolnik * memory, and the increment/decrement is added to the entire 24-bit address on 16069732b024SMichael Rolnik * such devices. Not all variants of this instruction is available in all 16079732b024SMichael Rolnik * devices. Refer to the device specific instruction set summary. In the 16089732b024SMichael Rolnik * Reduced Core tinyAVR the LD instruction can be used to achieve the same 16099732b024SMichael Rolnik * operation as LPM since the program memory is mapped to the data memory 16109732b024SMichael Rolnik * space. 16119732b024SMichael Rolnik */ 16129732b024SMichael Rolnik static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a) 16139732b024SMichael Rolnik { 16149732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 16159732b024SMichael Rolnik TCGv addr = gen_get_xaddr(); 16169732b024SMichael Rolnik 16179732b024SMichael Rolnik gen_data_load(ctx, Rd, addr); 16189732b024SMichael Rolnik return true; 16199732b024SMichael Rolnik } 16209732b024SMichael Rolnik 16219732b024SMichael Rolnik static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a) 16229732b024SMichael Rolnik { 16239732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 16249732b024SMichael Rolnik TCGv addr = gen_get_xaddr(); 16259732b024SMichael Rolnik 16269732b024SMichael Rolnik gen_data_load(ctx, Rd, addr); 16279732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 16289732b024SMichael Rolnik 16299732b024SMichael Rolnik gen_set_xaddr(addr); 16309732b024SMichael Rolnik return true; 16319732b024SMichael Rolnik } 16329732b024SMichael Rolnik 16339732b024SMichael Rolnik static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a) 16349732b024SMichael Rolnik { 16359732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 16369732b024SMichael Rolnik TCGv addr = gen_get_xaddr(); 16379732b024SMichael Rolnik 16389732b024SMichael Rolnik tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 16399732b024SMichael Rolnik gen_data_load(ctx, Rd, addr); 16409732b024SMichael Rolnik gen_set_xaddr(addr); 16419732b024SMichael Rolnik return true; 16429732b024SMichael Rolnik } 16439732b024SMichael Rolnik 16449732b024SMichael Rolnik /* 16459732b024SMichael Rolnik * Loads one byte indirect with or without displacement from the data space 16469732b024SMichael Rolnik * to a register. For parts with SRAM, the data space consists of the Register 16479732b024SMichael Rolnik * File, I/O memory and internal SRAM (and external SRAM if applicable). For 16489732b024SMichael Rolnik * parts without SRAM, the data space consists of the Register File only. In 16499732b024SMichael Rolnik * some parts the Flash Memory has been mapped to the data space and can be 16509732b024SMichael Rolnik * read using this command. The EEPROM has a separate address space. The data 16519732b024SMichael Rolnik * location is pointed to by the Y (16 bits) Pointer Register in the Register 16529732b024SMichael Rolnik * File. Memory access is limited to the current data segment of 64KB. To 16539732b024SMichael Rolnik * access another data segment in devices with more than 64KB data space, the 16549732b024SMichael Rolnik * RAMPY in register in the I/O area has to be changed. The Y-pointer Register 16559732b024SMichael Rolnik * can either be left unchanged by the operation, or it can be post-incremented 16569732b024SMichael Rolnik * or predecremented. These features are especially suited for accessing 16579732b024SMichael Rolnik * arrays, tables, and Stack Pointer usage of the Y-pointer Register. Note that 16589732b024SMichael Rolnik * only the low byte of the Y-pointer is updated in devices with no more than 16599732b024SMichael Rolnik * 256 bytes data space. For such devices, the high byte of the pointer is not 16609732b024SMichael Rolnik * used by this instruction and can be used for other purposes. The RAMPY 16619732b024SMichael Rolnik * Register in the I/O area is updated in parts with more than 64KB data space 16629732b024SMichael Rolnik * or more than 64KB Program memory, and the increment/decrement/displacement 16639732b024SMichael Rolnik * is added to the entire 24-bit address on such devices. Not all variants of 16649732b024SMichael Rolnik * this instruction is available in all devices. Refer to the device specific 16659732b024SMichael Rolnik * instruction set summary. In the Reduced Core tinyAVR the LD instruction can 16669732b024SMichael Rolnik * be used to achieve the same operation as LPM since the program memory is 16679732b024SMichael Rolnik * mapped to the data memory space. 16689732b024SMichael Rolnik */ 16699732b024SMichael Rolnik static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a) 16709732b024SMichael Rolnik { 16719732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 16729732b024SMichael Rolnik TCGv addr = gen_get_yaddr(); 16739732b024SMichael Rolnik 16749732b024SMichael Rolnik gen_data_load(ctx, Rd, addr); 16759732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 16769732b024SMichael Rolnik 16779732b024SMichael Rolnik gen_set_yaddr(addr); 16789732b024SMichael Rolnik return true; 16799732b024SMichael Rolnik } 16809732b024SMichael Rolnik 16819732b024SMichael Rolnik static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a) 16829732b024SMichael Rolnik { 16839732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 16849732b024SMichael Rolnik TCGv addr = gen_get_yaddr(); 16859732b024SMichael Rolnik 16869732b024SMichael Rolnik tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 16879732b024SMichael Rolnik gen_data_load(ctx, Rd, addr); 16889732b024SMichael Rolnik gen_set_yaddr(addr); 16899732b024SMichael Rolnik return true; 16909732b024SMichael Rolnik } 16919732b024SMichael Rolnik 16929732b024SMichael Rolnik static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a) 16939732b024SMichael Rolnik { 16949732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 16959732b024SMichael Rolnik TCGv addr = gen_get_yaddr(); 16969732b024SMichael Rolnik 16979732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 16989732b024SMichael Rolnik gen_data_load(ctx, Rd, addr); 16999732b024SMichael Rolnik return true; 17009732b024SMichael Rolnik } 17019732b024SMichael Rolnik 17029732b024SMichael Rolnik /* 17039732b024SMichael Rolnik * Loads one byte indirect with or without displacement from the data space 17049732b024SMichael Rolnik * to a register. For parts with SRAM, the data space consists of the Register 17059732b024SMichael Rolnik * File, I/O memory and internal SRAM (and external SRAM if applicable). For 17069732b024SMichael Rolnik * parts without SRAM, the data space consists of the Register File only. In 17079732b024SMichael Rolnik * some parts the Flash Memory has been mapped to the data space and can be 17089732b024SMichael Rolnik * read using this command. The EEPROM has a separate address space. The data 17099732b024SMichael Rolnik * location is pointed to by the Z (16 bits) Pointer Register in the Register 17109732b024SMichael Rolnik * File. Memory access is limited to the current data segment of 64KB. To 17119732b024SMichael Rolnik * access another data segment in devices with more than 64KB data space, the 17129732b024SMichael Rolnik * RAMPZ in register in the I/O area has to be changed. The Z-pointer Register 17139732b024SMichael Rolnik * can either be left unchanged by the operation, or it can be post-incremented 17149732b024SMichael Rolnik * or predecremented. These features are especially suited for Stack Pointer 17159732b024SMichael Rolnik * usage of the Z-pointer Register, however because the Z-pointer Register can 17169732b024SMichael Rolnik * be used for indirect subroutine calls, indirect jumps and table lookup, it 17179732b024SMichael Rolnik * is often more convenient to use the X or Y-pointer as a dedicated Stack 17189732b024SMichael Rolnik * Pointer. Note that only the low byte of the Z-pointer is updated in devices 17199732b024SMichael Rolnik * with no more than 256 bytes data space. For such devices, the high byte of 17209732b024SMichael Rolnik * the pointer is not used by this instruction and can be used for other 17219732b024SMichael Rolnik * purposes. The RAMPZ Register in the I/O area is updated in parts with more 17229732b024SMichael Rolnik * than 64KB data space or more than 64KB Program memory, and the 17239732b024SMichael Rolnik * increment/decrement/displacement is added to the entire 24-bit address on 17249732b024SMichael Rolnik * such devices. Not all variants of this instruction is available in all 17259732b024SMichael Rolnik * devices. Refer to the device specific instruction set summary. In the 17269732b024SMichael Rolnik * Reduced Core tinyAVR the LD instruction can be used to achieve the same 17279732b024SMichael Rolnik * operation as LPM since the program memory is mapped to the data memory 17289732b024SMichael Rolnik * space. For using the Z-pointer for table lookup in Program memory see the 17299732b024SMichael Rolnik * LPM and ELPM instructions. 17309732b024SMichael Rolnik */ 17319732b024SMichael Rolnik static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a) 17329732b024SMichael Rolnik { 17339732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 17349732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 17359732b024SMichael Rolnik 17369732b024SMichael Rolnik gen_data_load(ctx, Rd, addr); 17379732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 17389732b024SMichael Rolnik 17399732b024SMichael Rolnik gen_set_zaddr(addr); 17409732b024SMichael Rolnik return true; 17419732b024SMichael Rolnik } 17429732b024SMichael Rolnik 17439732b024SMichael Rolnik static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a) 17449732b024SMichael Rolnik { 17459732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 17469732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 17479732b024SMichael Rolnik 17489732b024SMichael Rolnik tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 17499732b024SMichael Rolnik gen_data_load(ctx, Rd, addr); 17509732b024SMichael Rolnik 17519732b024SMichael Rolnik gen_set_zaddr(addr); 17529732b024SMichael Rolnik return true; 17539732b024SMichael Rolnik } 17549732b024SMichael Rolnik 17559732b024SMichael Rolnik static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a) 17569732b024SMichael Rolnik { 17579732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 17589732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 17599732b024SMichael Rolnik 17609732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 17619732b024SMichael Rolnik gen_data_load(ctx, Rd, addr); 17629732b024SMichael Rolnik return true; 17639732b024SMichael Rolnik } 17649732b024SMichael Rolnik 17659732b024SMichael Rolnik /* 17669732b024SMichael Rolnik * Stores one byte from a Register to the data space. For parts with SRAM, 17679732b024SMichael Rolnik * the data space consists of the Register File, I/O memory and internal SRAM 17689732b024SMichael Rolnik * (and external SRAM if applicable). For parts without SRAM, the data space 17699732b024SMichael Rolnik * consists of the Register File only. The EEPROM has a separate address space. 17709732b024SMichael Rolnik * A 16-bit address must be supplied. Memory access is limited to the current 17719732b024SMichael Rolnik * data segment of 64KB. The STS instruction uses the RAMPD Register to access 17729732b024SMichael Rolnik * memory above 64KB. To access another data segment in devices with more than 17739732b024SMichael Rolnik * 64KB data space, the RAMPD in register in the I/O area has to be changed. 17749732b024SMichael Rolnik * This instruction is not available in all devices. Refer to the device 17759732b024SMichael Rolnik * specific instruction set summary. 17769732b024SMichael Rolnik */ 17779732b024SMichael Rolnik static bool trans_STS(DisasContext *ctx, arg_STS *a) 17789732b024SMichael Rolnik { 17799732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 17809732b024SMichael Rolnik TCGv addr = tcg_temp_new_i32(); 17819732b024SMichael Rolnik TCGv H = cpu_rampD; 17829732b024SMichael Rolnik a->imm = next_word(ctx); 17839732b024SMichael Rolnik 17849732b024SMichael Rolnik tcg_gen_mov_tl(addr, H); /* addr = H:M:L */ 17859732b024SMichael Rolnik tcg_gen_shli_tl(addr, addr, 16); 17869732b024SMichael Rolnik tcg_gen_ori_tl(addr, addr, a->imm); 17879732b024SMichael Rolnik gen_data_store(ctx, Rd, addr); 17889732b024SMichael Rolnik return true; 17899732b024SMichael Rolnik } 17909732b024SMichael Rolnik 17919732b024SMichael Rolnik /* 17929732b024SMichael Rolnik * Stores one byte indirect from a register to data space. For parts with SRAM, 17939732b024SMichael Rolnik * the data space consists of the Register File, I/O memory, and internal SRAM 17949732b024SMichael Rolnik * (and external SRAM if applicable). For parts without SRAM, the data space 17959732b024SMichael Rolnik * consists of the Register File only. The EEPROM has a separate address space. 17969732b024SMichael Rolnik * 17979732b024SMichael Rolnik * The data location is pointed to by the X (16 bits) Pointer Register in the 17989732b024SMichael Rolnik * Register File. Memory access is limited to the current data segment of 64KB. 17999732b024SMichael Rolnik * To access another data segment in devices with more than 64KB data space, the 18009732b024SMichael Rolnik * RAMPX in register in the I/O area has to be changed. 18019732b024SMichael Rolnik * 18029732b024SMichael Rolnik * The X-pointer Register can either be left unchanged by the operation, or it 18039732b024SMichael Rolnik * can be post-incremented or pre-decremented. These features are especially 18049732b024SMichael Rolnik * suited for accessing arrays, tables, and Stack Pointer usage of the 18059732b024SMichael Rolnik * X-pointer Register. Note that only the low byte of the X-pointer is updated 18069732b024SMichael Rolnik * in devices with no more than 256 bytes data space. For such devices, the high 18079732b024SMichael Rolnik * byte of the pointer is not used by this instruction and can be used for other 18089732b024SMichael Rolnik * purposes. The RAMPX Register in the I/O area is updated in parts with more 18099732b024SMichael Rolnik * than 64KB data space or more than 64KB Program memory, and the increment / 18109732b024SMichael Rolnik * decrement is added to the entire 24-bit address on such devices. 18119732b024SMichael Rolnik */ 18129732b024SMichael Rolnik static bool trans_STX1(DisasContext *ctx, arg_STX1 *a) 18139732b024SMichael Rolnik { 18149732b024SMichael Rolnik TCGv Rd = cpu_r[a->rr]; 18159732b024SMichael Rolnik TCGv addr = gen_get_xaddr(); 18169732b024SMichael Rolnik 18179732b024SMichael Rolnik gen_data_store(ctx, Rd, addr); 18189732b024SMichael Rolnik return true; 18199732b024SMichael Rolnik } 18209732b024SMichael Rolnik 18219732b024SMichael Rolnik static bool trans_STX2(DisasContext *ctx, arg_STX2 *a) 18229732b024SMichael Rolnik { 18239732b024SMichael Rolnik TCGv Rd = cpu_r[a->rr]; 18249732b024SMichael Rolnik TCGv addr = gen_get_xaddr(); 18259732b024SMichael Rolnik 18269732b024SMichael Rolnik gen_data_store(ctx, Rd, addr); 18279732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 18289732b024SMichael Rolnik gen_set_xaddr(addr); 18299732b024SMichael Rolnik return true; 18309732b024SMichael Rolnik } 18319732b024SMichael Rolnik 18329732b024SMichael Rolnik static bool trans_STX3(DisasContext *ctx, arg_STX3 *a) 18339732b024SMichael Rolnik { 18349732b024SMichael Rolnik TCGv Rd = cpu_r[a->rr]; 18359732b024SMichael Rolnik TCGv addr = gen_get_xaddr(); 18369732b024SMichael Rolnik 18379732b024SMichael Rolnik tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 18389732b024SMichael Rolnik gen_data_store(ctx, Rd, addr); 18399732b024SMichael Rolnik gen_set_xaddr(addr); 18409732b024SMichael Rolnik return true; 18419732b024SMichael Rolnik } 18429732b024SMichael Rolnik 18439732b024SMichael Rolnik /* 18449732b024SMichael Rolnik * Stores one byte indirect with or without displacement from a register to data 18459732b024SMichael Rolnik * space. For parts with SRAM, the data space consists of the Register File, I/O 18469732b024SMichael Rolnik * memory, and internal SRAM (and external SRAM if applicable). For parts 18479732b024SMichael Rolnik * without SRAM, the data space consists of the Register File only. The EEPROM 18489732b024SMichael Rolnik * has a separate address space. 18499732b024SMichael Rolnik * 18509732b024SMichael Rolnik * The data location is pointed to by the Y (16 bits) Pointer Register in the 18519732b024SMichael Rolnik * Register File. Memory access is limited to the current data segment of 64KB. 18529732b024SMichael Rolnik * To access another data segment in devices with more than 64KB data space, the 18539732b024SMichael Rolnik * RAMPY in register in the I/O area has to be changed. 18549732b024SMichael Rolnik * 18559732b024SMichael Rolnik * The Y-pointer Register can either be left unchanged by the operation, or it 18569732b024SMichael Rolnik * can be post-incremented or pre-decremented. These features are especially 18579732b024SMichael Rolnik * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer 18589732b024SMichael Rolnik * Register. Note that only the low byte of the Y-pointer is updated in devices 18599732b024SMichael Rolnik * with no more than 256 bytes data space. For such devices, the high byte of 18609732b024SMichael Rolnik * the pointer is not used by this instruction and can be used for other 18619732b024SMichael Rolnik * purposes. The RAMPY Register in the I/O area is updated in parts with more 18629732b024SMichael Rolnik * than 64KB data space or more than 64KB Program memory, and the increment / 18639732b024SMichael Rolnik * decrement / displacement is added to the entire 24-bit address on such 18649732b024SMichael Rolnik * devices. 18659732b024SMichael Rolnik */ 18669732b024SMichael Rolnik static bool trans_STY2(DisasContext *ctx, arg_STY2 *a) 18679732b024SMichael Rolnik { 18689732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 18699732b024SMichael Rolnik TCGv addr = gen_get_yaddr(); 18709732b024SMichael Rolnik 18719732b024SMichael Rolnik gen_data_store(ctx, Rd, addr); 18729732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 18739732b024SMichael Rolnik gen_set_yaddr(addr); 18749732b024SMichael Rolnik return true; 18759732b024SMichael Rolnik } 18769732b024SMichael Rolnik 18779732b024SMichael Rolnik static bool trans_STY3(DisasContext *ctx, arg_STY3 *a) 18789732b024SMichael Rolnik { 18799732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 18809732b024SMichael Rolnik TCGv addr = gen_get_yaddr(); 18819732b024SMichael Rolnik 18829732b024SMichael Rolnik tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 18839732b024SMichael Rolnik gen_data_store(ctx, Rd, addr); 18849732b024SMichael Rolnik gen_set_yaddr(addr); 18859732b024SMichael Rolnik return true; 18869732b024SMichael Rolnik } 18879732b024SMichael Rolnik 18889732b024SMichael Rolnik static bool trans_STDY(DisasContext *ctx, arg_STDY *a) 18899732b024SMichael Rolnik { 18909732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 18919732b024SMichael Rolnik TCGv addr = gen_get_yaddr(); 18929732b024SMichael Rolnik 18939732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 18949732b024SMichael Rolnik gen_data_store(ctx, Rd, addr); 18959732b024SMichael Rolnik return true; 18969732b024SMichael Rolnik } 18979732b024SMichael Rolnik 18989732b024SMichael Rolnik /* 18999732b024SMichael Rolnik * Stores one byte indirect with or without displacement from a register to data 19009732b024SMichael Rolnik * space. For parts with SRAM, the data space consists of the Register File, I/O 19019732b024SMichael Rolnik * memory, and internal SRAM (and external SRAM if applicable). For parts 19029732b024SMichael Rolnik * without SRAM, the data space consists of the Register File only. The EEPROM 19039732b024SMichael Rolnik * has a separate address space. 19049732b024SMichael Rolnik * 19059732b024SMichael Rolnik * The data location is pointed to by the Y (16 bits) Pointer Register in the 19069732b024SMichael Rolnik * Register File. Memory access is limited to the current data segment of 64KB. 19079732b024SMichael Rolnik * To access another data segment in devices with more than 64KB data space, the 19089732b024SMichael Rolnik * RAMPY in register in the I/O area has to be changed. 19099732b024SMichael Rolnik * 19109732b024SMichael Rolnik * The Y-pointer Register can either be left unchanged by the operation, or it 19119732b024SMichael Rolnik * can be post-incremented or pre-decremented. These features are especially 19129732b024SMichael Rolnik * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer 19139732b024SMichael Rolnik * Register. Note that only the low byte of the Y-pointer is updated in devices 19149732b024SMichael Rolnik * with no more than 256 bytes data space. For such devices, the high byte of 19159732b024SMichael Rolnik * the pointer is not used by this instruction and can be used for other 19169732b024SMichael Rolnik * purposes. The RAMPY Register in the I/O area is updated in parts with more 19179732b024SMichael Rolnik * than 64KB data space or more than 64KB Program memory, and the increment / 19189732b024SMichael Rolnik * decrement / displacement is added to the entire 24-bit address on such 19199732b024SMichael Rolnik * devices. 19209732b024SMichael Rolnik */ 19219732b024SMichael Rolnik static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a) 19229732b024SMichael Rolnik { 19239732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 19249732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 19259732b024SMichael Rolnik 19269732b024SMichael Rolnik gen_data_store(ctx, Rd, addr); 19279732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 19289732b024SMichael Rolnik 19299732b024SMichael Rolnik gen_set_zaddr(addr); 19309732b024SMichael Rolnik return true; 19319732b024SMichael Rolnik } 19329732b024SMichael Rolnik 19339732b024SMichael Rolnik static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a) 19349732b024SMichael Rolnik { 19359732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 19369732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 19379732b024SMichael Rolnik 19389732b024SMichael Rolnik tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ 19399732b024SMichael Rolnik gen_data_store(ctx, Rd, addr); 19409732b024SMichael Rolnik 19419732b024SMichael Rolnik gen_set_zaddr(addr); 19429732b024SMichael Rolnik return true; 19439732b024SMichael Rolnik } 19449732b024SMichael Rolnik 19459732b024SMichael Rolnik static bool trans_STDZ(DisasContext *ctx, arg_STDZ *a) 19469732b024SMichael Rolnik { 19479732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 19489732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 19499732b024SMichael Rolnik 19509732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ 19519732b024SMichael Rolnik gen_data_store(ctx, Rd, addr); 19529732b024SMichael Rolnik return true; 19539732b024SMichael Rolnik } 19549732b024SMichael Rolnik 19559732b024SMichael Rolnik /* 19569732b024SMichael Rolnik * Loads one byte pointed to by the Z-register into the destination 19579732b024SMichael Rolnik * register Rd. This instruction features a 100% space effective constant 19589732b024SMichael Rolnik * initialization or constant data fetch. The Program memory is organized in 19599732b024SMichael Rolnik * 16-bit words while the Z-pointer is a byte address. Thus, the least 19609732b024SMichael Rolnik * significant bit of the Z-pointer selects either low byte (ZLSB = 0) or high 19619732b024SMichael Rolnik * byte (ZLSB = 1). This instruction can address the first 64KB (32K words) of 19629732b024SMichael Rolnik * Program memory. The Zpointer Register can either be left unchanged by the 19639732b024SMichael Rolnik * operation, or it can be incremented. The incrementation does not apply to 19649732b024SMichael Rolnik * the RAMPZ Register. 19659732b024SMichael Rolnik * 19669732b024SMichael Rolnik * Devices with Self-Programming capability can use the LPM instruction to read 19679732b024SMichael Rolnik * the Fuse and Lock bit values. 19689732b024SMichael Rolnik */ 19699732b024SMichael Rolnik static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a) 19709732b024SMichael Rolnik { 19719732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) { 19729732b024SMichael Rolnik return true; 19739732b024SMichael Rolnik } 19749732b024SMichael Rolnik 19759732b024SMichael Rolnik TCGv Rd = cpu_r[0]; 19769732b024SMichael Rolnik TCGv addr = tcg_temp_new_i32(); 19779732b024SMichael Rolnik TCGv H = cpu_r[31]; 19789732b024SMichael Rolnik TCGv L = cpu_r[30]; 19799732b024SMichael Rolnik 19809732b024SMichael Rolnik tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 19819732b024SMichael Rolnik tcg_gen_or_tl(addr, addr, L); 1982*8b4506e5SRichard Henderson tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); 19839732b024SMichael Rolnik return true; 19849732b024SMichael Rolnik } 19859732b024SMichael Rolnik 19869732b024SMichael Rolnik static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a) 19879732b024SMichael Rolnik { 19889732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_LPM)) { 19899732b024SMichael Rolnik return true; 19909732b024SMichael Rolnik } 19919732b024SMichael Rolnik 19929732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 19939732b024SMichael Rolnik TCGv addr = tcg_temp_new_i32(); 19949732b024SMichael Rolnik TCGv H = cpu_r[31]; 19959732b024SMichael Rolnik TCGv L = cpu_r[30]; 19969732b024SMichael Rolnik 19979732b024SMichael Rolnik tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 19989732b024SMichael Rolnik tcg_gen_or_tl(addr, addr, L); 1999*8b4506e5SRichard Henderson tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); 20009732b024SMichael Rolnik return true; 20019732b024SMichael Rolnik } 20029732b024SMichael Rolnik 20039732b024SMichael Rolnik static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a) 20049732b024SMichael Rolnik { 20059732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_LPMX)) { 20069732b024SMichael Rolnik return true; 20079732b024SMichael Rolnik } 20089732b024SMichael Rolnik 20099732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 20109732b024SMichael Rolnik TCGv addr = tcg_temp_new_i32(); 20119732b024SMichael Rolnik TCGv H = cpu_r[31]; 20129732b024SMichael Rolnik TCGv L = cpu_r[30]; 20139732b024SMichael Rolnik 20149732b024SMichael Rolnik tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */ 20159732b024SMichael Rolnik tcg_gen_or_tl(addr, addr, L); 2016*8b4506e5SRichard Henderson tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); 20179732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 20189732b024SMichael Rolnik tcg_gen_andi_tl(L, addr, 0xff); 20199732b024SMichael Rolnik tcg_gen_shri_tl(addr, addr, 8); 20209732b024SMichael Rolnik tcg_gen_andi_tl(H, addr, 0xff); 20219732b024SMichael Rolnik return true; 20229732b024SMichael Rolnik } 20239732b024SMichael Rolnik 20249732b024SMichael Rolnik /* 20259732b024SMichael Rolnik * Loads one byte pointed to by the Z-register and the RAMPZ Register in 20269732b024SMichael Rolnik * the I/O space, and places this byte in the destination register Rd. This 20279732b024SMichael Rolnik * instruction features a 100% space effective constant initialization or 20289732b024SMichael Rolnik * constant data fetch. The Program memory is organized in 16-bit words while 20299732b024SMichael Rolnik * the Z-pointer is a byte address. Thus, the least significant bit of the 20309732b024SMichael Rolnik * Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This 20319732b024SMichael Rolnik * instruction can address the entire Program memory space. The Z-pointer 20329732b024SMichael Rolnik * Register can either be left unchanged by the operation, or it can be 20339732b024SMichael Rolnik * incremented. The incrementation applies to the entire 24-bit concatenation 20349732b024SMichael Rolnik * of the RAMPZ and Z-pointer Registers. 20359732b024SMichael Rolnik * 20369732b024SMichael Rolnik * Devices with Self-Programming capability can use the ELPM instruction to 20379732b024SMichael Rolnik * read the Fuse and Lock bit value. 20389732b024SMichael Rolnik */ 20399732b024SMichael Rolnik static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a) 20409732b024SMichael Rolnik { 20419732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) { 20429732b024SMichael Rolnik return true; 20439732b024SMichael Rolnik } 20449732b024SMichael Rolnik 20459732b024SMichael Rolnik TCGv Rd = cpu_r[0]; 20469732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 20479732b024SMichael Rolnik 2048*8b4506e5SRichard Henderson tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); 20499732b024SMichael Rolnik return true; 20509732b024SMichael Rolnik } 20519732b024SMichael Rolnik 20529732b024SMichael Rolnik static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a) 20539732b024SMichael Rolnik { 20549732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_ELPM)) { 20559732b024SMichael Rolnik return true; 20569732b024SMichael Rolnik } 20579732b024SMichael Rolnik 20589732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 20599732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 20609732b024SMichael Rolnik 2061*8b4506e5SRichard Henderson tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); 20629732b024SMichael Rolnik return true; 20639732b024SMichael Rolnik } 20649732b024SMichael Rolnik 20659732b024SMichael Rolnik static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a) 20669732b024SMichael Rolnik { 20679732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_ELPMX)) { 20689732b024SMichael Rolnik return true; 20699732b024SMichael Rolnik } 20709732b024SMichael Rolnik 20719732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 20729732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 20739732b024SMichael Rolnik 2074*8b4506e5SRichard Henderson tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); 20759732b024SMichael Rolnik tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ 20769732b024SMichael Rolnik gen_set_zaddr(addr); 20779732b024SMichael Rolnik return true; 20789732b024SMichael Rolnik } 20799732b024SMichael Rolnik 20809732b024SMichael Rolnik /* 20819732b024SMichael Rolnik * SPM can be used to erase a page in the Program memory, to write a page 20829732b024SMichael Rolnik * in the Program memory (that is already erased), and to set Boot Loader Lock 20839732b024SMichael Rolnik * bits. In some devices, the Program memory can be written one word at a time, 20849732b024SMichael Rolnik * in other devices an entire page can be programmed simultaneously after first 20859732b024SMichael Rolnik * filling a temporary page buffer. In all cases, the Program memory must be 20869732b024SMichael Rolnik * erased one page at a time. When erasing the Program memory, the RAMPZ and 20879732b024SMichael Rolnik * Z-register are used as page address. When writing the Program memory, the 20889732b024SMichael Rolnik * RAMPZ and Z-register are used as page or word address, and the R1:R0 20899732b024SMichael Rolnik * register pair is used as data(1). When setting the Boot Loader Lock bits, 20909732b024SMichael Rolnik * the R1:R0 register pair is used as data. Refer to the device documentation 20919732b024SMichael Rolnik * for detailed description of SPM usage. This instruction can address the 20929732b024SMichael Rolnik * entire Program memory. 20939732b024SMichael Rolnik * 20949732b024SMichael Rolnik * The SPM instruction is not available in all devices. Refer to the device 20959732b024SMichael Rolnik * specific instruction set summary. 20969732b024SMichael Rolnik * 20979732b024SMichael Rolnik * Note: 1. R1 determines the instruction high byte, and R0 determines the 20989732b024SMichael Rolnik * instruction low byte. 20999732b024SMichael Rolnik */ 21009732b024SMichael Rolnik static bool trans_SPM(DisasContext *ctx, arg_SPM *a) 21019732b024SMichael Rolnik { 21029732b024SMichael Rolnik /* TODO */ 21039732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_SPM)) { 21049732b024SMichael Rolnik return true; 21059732b024SMichael Rolnik } 21069732b024SMichael Rolnik 21079732b024SMichael Rolnik return true; 21089732b024SMichael Rolnik } 21099732b024SMichael Rolnik 21109732b024SMichael Rolnik static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) 21119732b024SMichael Rolnik { 21129732b024SMichael Rolnik /* TODO */ 21139732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_SPMX)) { 21149732b024SMichael Rolnik return true; 21159732b024SMichael Rolnik } 21169732b024SMichael Rolnik 21179732b024SMichael Rolnik return true; 21189732b024SMichael Rolnik } 21199732b024SMichael Rolnik 21209732b024SMichael Rolnik /* 21219732b024SMichael Rolnik * Loads data from the I/O Space (Ports, Timers, Configuration Registers, 21229732b024SMichael Rolnik * etc.) into register Rd in the Register File. 21239732b024SMichael Rolnik */ 21249732b024SMichael Rolnik static bool trans_IN(DisasContext *ctx, arg_IN *a) 21259732b024SMichael Rolnik { 21269732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 21276d27bb55SRichard Henderson TCGv port = tcg_constant_i32(a->imm); 21289732b024SMichael Rolnik 21299732b024SMichael Rolnik gen_helper_inb(Rd, cpu_env, port); 21309732b024SMichael Rolnik return true; 21319732b024SMichael Rolnik } 21329732b024SMichael Rolnik 21339732b024SMichael Rolnik /* 21349732b024SMichael Rolnik * Stores data from register Rr in the Register File to I/O Space (Ports, 21359732b024SMichael Rolnik * Timers, Configuration Registers, etc.). 21369732b024SMichael Rolnik */ 21379732b024SMichael Rolnik static bool trans_OUT(DisasContext *ctx, arg_OUT *a) 21389732b024SMichael Rolnik { 21399732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 21406d27bb55SRichard Henderson TCGv port = tcg_constant_i32(a->imm); 21419732b024SMichael Rolnik 21429732b024SMichael Rolnik gen_helper_outb(cpu_env, port, Rd); 21439732b024SMichael Rolnik return true; 21449732b024SMichael Rolnik } 21459732b024SMichael Rolnik 21469732b024SMichael Rolnik /* 21479732b024SMichael Rolnik * This instruction stores the contents of register Rr on the STACK. The 21489732b024SMichael Rolnik * Stack Pointer is post-decremented by 1 after the PUSH. This instruction is 21499732b024SMichael Rolnik * not available in all devices. Refer to the device specific instruction set 21509732b024SMichael Rolnik * summary. 21519732b024SMichael Rolnik */ 21529732b024SMichael Rolnik static bool trans_PUSH(DisasContext *ctx, arg_PUSH *a) 21539732b024SMichael Rolnik { 21549732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 21559732b024SMichael Rolnik 21569732b024SMichael Rolnik gen_data_store(ctx, Rd, cpu_sp); 21579732b024SMichael Rolnik tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); 21589732b024SMichael Rolnik 21599732b024SMichael Rolnik return true; 21609732b024SMichael Rolnik } 21619732b024SMichael Rolnik 21629732b024SMichael Rolnik /* 21639732b024SMichael Rolnik * This instruction loads register Rd with a byte from the STACK. The Stack 21649732b024SMichael Rolnik * Pointer is pre-incremented by 1 before the POP. This instruction is not 21659732b024SMichael Rolnik * available in all devices. Refer to the device specific instruction set 21669732b024SMichael Rolnik * summary. 21679732b024SMichael Rolnik */ 21689732b024SMichael Rolnik static bool trans_POP(DisasContext *ctx, arg_POP *a) 21699732b024SMichael Rolnik { 21709732b024SMichael Rolnik /* 21719732b024SMichael Rolnik * Using a temp to work around some strange behaviour: 21729732b024SMichael Rolnik * tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); 21739732b024SMichael Rolnik * gen_data_load(ctx, Rd, cpu_sp); 21749732b024SMichael Rolnik * seems to cause the add to happen twice. 21759732b024SMichael Rolnik * This doesn't happen if either the add or the load is removed. 21769732b024SMichael Rolnik */ 21779732b024SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 21789732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 21799732b024SMichael Rolnik 21809732b024SMichael Rolnik tcg_gen_addi_tl(t1, cpu_sp, 1); 21819732b024SMichael Rolnik gen_data_load(ctx, Rd, t1); 21829732b024SMichael Rolnik tcg_gen_mov_tl(cpu_sp, t1); 21839732b024SMichael Rolnik 21849732b024SMichael Rolnik return true; 21859732b024SMichael Rolnik } 21869732b024SMichael Rolnik 21879732b024SMichael Rolnik /* 21889732b024SMichael Rolnik * Exchanges one byte indirect between register and data space. The data 21899732b024SMichael Rolnik * location is pointed to by the Z (16 bits) Pointer Register in the Register 21909732b024SMichael Rolnik * File. Memory access is limited to the current data segment of 64KB. To 21919732b024SMichael Rolnik * access another data segment in devices with more than 64KB data space, the 21929732b024SMichael Rolnik * RAMPZ in register in the I/O area has to be changed. 21939732b024SMichael Rolnik * 21949732b024SMichael Rolnik * The Z-pointer Register is left unchanged by the operation. This instruction 21959732b024SMichael Rolnik * is especially suited for writing/reading status bits stored in SRAM. 21969732b024SMichael Rolnik */ 21979732b024SMichael Rolnik static bool trans_XCH(DisasContext *ctx, arg_XCH *a) 21989732b024SMichael Rolnik { 21999732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 22009732b024SMichael Rolnik return true; 22019732b024SMichael Rolnik } 22029732b024SMichael Rolnik 22039732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 22049732b024SMichael Rolnik TCGv t0 = tcg_temp_new_i32(); 22059732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 22069732b024SMichael Rolnik 22079732b024SMichael Rolnik gen_data_load(ctx, t0, addr); 22089732b024SMichael Rolnik gen_data_store(ctx, Rd, addr); 22099732b024SMichael Rolnik tcg_gen_mov_tl(Rd, t0); 22109732b024SMichael Rolnik return true; 22119732b024SMichael Rolnik } 22129732b024SMichael Rolnik 22139732b024SMichael Rolnik /* 22149732b024SMichael Rolnik * Load one byte indirect from data space to register and set bits in data 22159732b024SMichael Rolnik * space specified by the register. The instruction can only be used towards 22169732b024SMichael Rolnik * internal SRAM. The data location is pointed to by the Z (16 bits) Pointer 22179732b024SMichael Rolnik * Register in the Register File. Memory access is limited to the current data 22189732b024SMichael Rolnik * segment of 64KB. To access another data segment in devices with more than 22199732b024SMichael Rolnik * 64KB data space, the RAMPZ in register in the I/O area has to be changed. 22209732b024SMichael Rolnik * 22219732b024SMichael Rolnik * The Z-pointer Register is left unchanged by the operation. This instruction 22229732b024SMichael Rolnik * is especially suited for setting status bits stored in SRAM. 22239732b024SMichael Rolnik */ 22249732b024SMichael Rolnik static bool trans_LAS(DisasContext *ctx, arg_LAS *a) 22259732b024SMichael Rolnik { 22269732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 22279732b024SMichael Rolnik return true; 22289732b024SMichael Rolnik } 22299732b024SMichael Rolnik 22309732b024SMichael Rolnik TCGv Rr = cpu_r[a->rd]; 22319732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 22329732b024SMichael Rolnik TCGv t0 = tcg_temp_new_i32(); 22339732b024SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 22349732b024SMichael Rolnik 22359732b024SMichael Rolnik gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 22369732b024SMichael Rolnik tcg_gen_or_tl(t1, t0, Rr); 22379732b024SMichael Rolnik tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */ 22389732b024SMichael Rolnik gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 22399732b024SMichael Rolnik return true; 22409732b024SMichael Rolnik } 22419732b024SMichael Rolnik 22429732b024SMichael Rolnik /* 22439732b024SMichael Rolnik * Load one byte indirect from data space to register and stores and clear 22449732b024SMichael Rolnik * the bits in data space specified by the register. The instruction can 22459732b024SMichael Rolnik * only be used towards internal SRAM. The data location is pointed to by 22469732b024SMichael Rolnik * the Z (16 bits) Pointer Register in the Register File. Memory access is 22479732b024SMichael Rolnik * limited to the current data segment of 64KB. To access another data 22489732b024SMichael Rolnik * segment in devices with more than 64KB data space, the RAMPZ in register 22499732b024SMichael Rolnik * in the I/O area has to be changed. 22509732b024SMichael Rolnik * 22519732b024SMichael Rolnik * The Z-pointer Register is left unchanged by the operation. This instruction 22529732b024SMichael Rolnik * is especially suited for clearing status bits stored in SRAM. 22539732b024SMichael Rolnik */ 22549732b024SMichael Rolnik static bool trans_LAC(DisasContext *ctx, arg_LAC *a) 22559732b024SMichael Rolnik { 22569732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 22579732b024SMichael Rolnik return true; 22589732b024SMichael Rolnik } 22599732b024SMichael Rolnik 22609732b024SMichael Rolnik TCGv Rr = cpu_r[a->rd]; 22619732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 22629732b024SMichael Rolnik TCGv t0 = tcg_temp_new_i32(); 22639732b024SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 22649732b024SMichael Rolnik 22659732b024SMichael Rolnik gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 22669732b024SMichael Rolnik tcg_gen_andc_tl(t1, t0, Rr); /* t1 = t0 & (0xff - Rr) = t0 & ~Rr */ 22679732b024SMichael Rolnik tcg_gen_mov_tl(Rr, t0); /* Rr = t0 */ 22689732b024SMichael Rolnik gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 22699732b024SMichael Rolnik return true; 22709732b024SMichael Rolnik } 22719732b024SMichael Rolnik 22729732b024SMichael Rolnik 22739732b024SMichael Rolnik /* 22749732b024SMichael Rolnik * Load one byte indirect from data space to register and toggles bits in 22759732b024SMichael Rolnik * the data space specified by the register. The instruction can only be used 22769732b024SMichael Rolnik * towards SRAM. The data location is pointed to by the Z (16 bits) Pointer 22779732b024SMichael Rolnik * Register in the Register File. Memory access is limited to the current data 22789732b024SMichael Rolnik * segment of 64KB. To access another data segment in devices with more than 22799732b024SMichael Rolnik * 64KB data space, the RAMPZ in register in the I/O area has to be changed. 22809732b024SMichael Rolnik * 22819732b024SMichael Rolnik * The Z-pointer Register is left unchanged by the operation. This instruction 22829732b024SMichael Rolnik * is especially suited for changing status bits stored in SRAM. 22839732b024SMichael Rolnik */ 22849732b024SMichael Rolnik static bool trans_LAT(DisasContext *ctx, arg_LAT *a) 22859732b024SMichael Rolnik { 22869732b024SMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_RMW)) { 22879732b024SMichael Rolnik return true; 22889732b024SMichael Rolnik } 22899732b024SMichael Rolnik 22909732b024SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 22919732b024SMichael Rolnik TCGv addr = gen_get_zaddr(); 22929732b024SMichael Rolnik TCGv t0 = tcg_temp_new_i32(); 22939732b024SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 22949732b024SMichael Rolnik 22959732b024SMichael Rolnik gen_data_load(ctx, t0, addr); /* t0 = mem[addr] */ 22969732b024SMichael Rolnik tcg_gen_xor_tl(t1, t0, Rd); 22979732b024SMichael Rolnik tcg_gen_mov_tl(Rd, t0); /* Rd = t0 */ 22989732b024SMichael Rolnik gen_data_store(ctx, t1, addr); /* mem[addr] = t1 */ 22999732b024SMichael Rolnik return true; 23009732b024SMichael Rolnik } 23015718cef0SMichael Rolnik 23025718cef0SMichael Rolnik /* 23035718cef0SMichael Rolnik * Bit and Bit-test Instructions 23045718cef0SMichael Rolnik */ 23055718cef0SMichael Rolnik static void gen_rshift_ZNVSf(TCGv R) 23065718cef0SMichael Rolnik { 23075718cef0SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */ 23085718cef0SMichael Rolnik tcg_gen_shri_tl(cpu_Nf, R, 7); /* Nf = R(7) */ 23095718cef0SMichael Rolnik tcg_gen_xor_tl(cpu_Vf, cpu_Nf, cpu_Cf); 23105718cef0SMichael Rolnik tcg_gen_xor_tl(cpu_Sf, cpu_Nf, cpu_Vf); /* Sf = Nf ^ Vf */ 23115718cef0SMichael Rolnik } 23125718cef0SMichael Rolnik 23135718cef0SMichael Rolnik /* 23145718cef0SMichael Rolnik * Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is 23155718cef0SMichael Rolnik * loaded into the C Flag of the SREG. This operation effectively divides an 23165718cef0SMichael Rolnik * unsigned value by two. The C Flag can be used to round the result. 23175718cef0SMichael Rolnik */ 23185718cef0SMichael Rolnik static bool trans_LSR(DisasContext *ctx, arg_LSR *a) 23195718cef0SMichael Rolnik { 23205718cef0SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 23215718cef0SMichael Rolnik 23225718cef0SMichael Rolnik tcg_gen_andi_tl(cpu_Cf, Rd, 1); 23235718cef0SMichael Rolnik tcg_gen_shri_tl(Rd, Rd, 1); 23245718cef0SMichael Rolnik 23255718cef0SMichael Rolnik /* update status register */ 23265718cef0SMichael Rolnik tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, Rd, 0); /* Zf = Rd == 0 */ 23275718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Nf, 0); 23285718cef0SMichael Rolnik tcg_gen_mov_tl(cpu_Vf, cpu_Cf); 23295718cef0SMichael Rolnik tcg_gen_mov_tl(cpu_Sf, cpu_Vf); 23305718cef0SMichael Rolnik 23315718cef0SMichael Rolnik return true; 23325718cef0SMichael Rolnik } 23335718cef0SMichael Rolnik 23345718cef0SMichael Rolnik /* 23355718cef0SMichael Rolnik * Shifts all bits in Rd one place to the right. The C Flag is shifted into 23365718cef0SMichael Rolnik * bit 7 of Rd. Bit 0 is shifted into the C Flag. This operation, combined 23375718cef0SMichael Rolnik * with ASR, effectively divides multi-byte signed values by two. Combined with 23385718cef0SMichael Rolnik * LSR it effectively divides multi-byte unsigned values by two. The Carry Flag 23395718cef0SMichael Rolnik * can be used to round the result. 23405718cef0SMichael Rolnik */ 23415718cef0SMichael Rolnik static bool trans_ROR(DisasContext *ctx, arg_ROR *a) 23425718cef0SMichael Rolnik { 23435718cef0SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 23445718cef0SMichael Rolnik TCGv t0 = tcg_temp_new_i32(); 23455718cef0SMichael Rolnik 23465718cef0SMichael Rolnik tcg_gen_shli_tl(t0, cpu_Cf, 7); 23475718cef0SMichael Rolnik 23485718cef0SMichael Rolnik /* update status register */ 23495718cef0SMichael Rolnik tcg_gen_andi_tl(cpu_Cf, Rd, 1); 23505718cef0SMichael Rolnik 23515718cef0SMichael Rolnik /* update output register */ 23525718cef0SMichael Rolnik tcg_gen_shri_tl(Rd, Rd, 1); 23535718cef0SMichael Rolnik tcg_gen_or_tl(Rd, Rd, t0); 23545718cef0SMichael Rolnik 23555718cef0SMichael Rolnik /* update status register */ 23565718cef0SMichael Rolnik gen_rshift_ZNVSf(Rd); 23575718cef0SMichael Rolnik return true; 23585718cef0SMichael Rolnik } 23595718cef0SMichael Rolnik 23605718cef0SMichael Rolnik /* 23615718cef0SMichael Rolnik * Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 23625718cef0SMichael Rolnik * is loaded into the C Flag of the SREG. This operation effectively divides a 23635718cef0SMichael Rolnik * signed value by two without changing its sign. The Carry Flag can be used to 23645718cef0SMichael Rolnik * round the result. 23655718cef0SMichael Rolnik */ 23665718cef0SMichael Rolnik static bool trans_ASR(DisasContext *ctx, arg_ASR *a) 23675718cef0SMichael Rolnik { 23685718cef0SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 23695718cef0SMichael Rolnik TCGv t0 = tcg_temp_new_i32(); 23705718cef0SMichael Rolnik 23715718cef0SMichael Rolnik /* update status register */ 23725718cef0SMichael Rolnik tcg_gen_andi_tl(cpu_Cf, Rd, 1); /* Cf = Rd(0) */ 23735718cef0SMichael Rolnik 23745718cef0SMichael Rolnik /* update output register */ 23755718cef0SMichael Rolnik tcg_gen_andi_tl(t0, Rd, 0x80); /* Rd = (Rd & 0x80) | (Rd >> 1) */ 23765718cef0SMichael Rolnik tcg_gen_shri_tl(Rd, Rd, 1); 23775718cef0SMichael Rolnik tcg_gen_or_tl(Rd, Rd, t0); 23785718cef0SMichael Rolnik 23795718cef0SMichael Rolnik /* update status register */ 23805718cef0SMichael Rolnik gen_rshift_ZNVSf(Rd); 23815718cef0SMichael Rolnik return true; 23825718cef0SMichael Rolnik } 23835718cef0SMichael Rolnik 23845718cef0SMichael Rolnik /* 23855718cef0SMichael Rolnik * Swaps high and low nibbles in a register. 23865718cef0SMichael Rolnik */ 23875718cef0SMichael Rolnik static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a) 23885718cef0SMichael Rolnik { 23895718cef0SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 23905718cef0SMichael Rolnik TCGv t0 = tcg_temp_new_i32(); 23915718cef0SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 23925718cef0SMichael Rolnik 23935718cef0SMichael Rolnik tcg_gen_andi_tl(t0, Rd, 0x0f); 23945718cef0SMichael Rolnik tcg_gen_shli_tl(t0, t0, 4); 23955718cef0SMichael Rolnik tcg_gen_andi_tl(t1, Rd, 0xf0); 23965718cef0SMichael Rolnik tcg_gen_shri_tl(t1, t1, 4); 23975718cef0SMichael Rolnik tcg_gen_or_tl(Rd, t0, t1); 23985718cef0SMichael Rolnik return true; 23995718cef0SMichael Rolnik } 24005718cef0SMichael Rolnik 24015718cef0SMichael Rolnik /* 24025718cef0SMichael Rolnik * Sets a specified bit in an I/O Register. This instruction operates on 24035718cef0SMichael Rolnik * the lower 32 I/O Registers -- addresses 0-31. 24045718cef0SMichael Rolnik */ 24055718cef0SMichael Rolnik static bool trans_SBI(DisasContext *ctx, arg_SBI *a) 24065718cef0SMichael Rolnik { 24075718cef0SMichael Rolnik TCGv data = tcg_temp_new_i32(); 24086d27bb55SRichard Henderson TCGv port = tcg_constant_i32(a->reg); 24095718cef0SMichael Rolnik 24105718cef0SMichael Rolnik gen_helper_inb(data, cpu_env, port); 24115718cef0SMichael Rolnik tcg_gen_ori_tl(data, data, 1 << a->bit); 24125718cef0SMichael Rolnik gen_helper_outb(cpu_env, port, data); 24135718cef0SMichael Rolnik return true; 24145718cef0SMichael Rolnik } 24155718cef0SMichael Rolnik 24165718cef0SMichael Rolnik /* 24175718cef0SMichael Rolnik * Clears a specified bit in an I/O Register. This instruction operates on 24185718cef0SMichael Rolnik * the lower 32 I/O Registers -- addresses 0-31. 24195718cef0SMichael Rolnik */ 24205718cef0SMichael Rolnik static bool trans_CBI(DisasContext *ctx, arg_CBI *a) 24215718cef0SMichael Rolnik { 24225718cef0SMichael Rolnik TCGv data = tcg_temp_new_i32(); 24236d27bb55SRichard Henderson TCGv port = tcg_constant_i32(a->reg); 24245718cef0SMichael Rolnik 24255718cef0SMichael Rolnik gen_helper_inb(data, cpu_env, port); 24265718cef0SMichael Rolnik tcg_gen_andi_tl(data, data, ~(1 << a->bit)); 24275718cef0SMichael Rolnik gen_helper_outb(cpu_env, port, data); 24285718cef0SMichael Rolnik return true; 24295718cef0SMichael Rolnik } 24305718cef0SMichael Rolnik 24315718cef0SMichael Rolnik /* 24325718cef0SMichael Rolnik * Stores bit b from Rd to the T Flag in SREG (Status Register). 24335718cef0SMichael Rolnik */ 24345718cef0SMichael Rolnik static bool trans_BST(DisasContext *ctx, arg_BST *a) 24355718cef0SMichael Rolnik { 24365718cef0SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 24375718cef0SMichael Rolnik 24385718cef0SMichael Rolnik tcg_gen_andi_tl(cpu_Tf, Rd, 1 << a->bit); 24395718cef0SMichael Rolnik tcg_gen_shri_tl(cpu_Tf, cpu_Tf, a->bit); 24405718cef0SMichael Rolnik 24415718cef0SMichael Rolnik return true; 24425718cef0SMichael Rolnik } 24435718cef0SMichael Rolnik 24445718cef0SMichael Rolnik /* 24455718cef0SMichael Rolnik * Copies the T Flag in the SREG (Status Register) to bit b in register Rd. 24465718cef0SMichael Rolnik */ 24475718cef0SMichael Rolnik static bool trans_BLD(DisasContext *ctx, arg_BLD *a) 24485718cef0SMichael Rolnik { 24495718cef0SMichael Rolnik TCGv Rd = cpu_r[a->rd]; 24505718cef0SMichael Rolnik TCGv t1 = tcg_temp_new_i32(); 24515718cef0SMichael Rolnik 24525718cef0SMichael Rolnik tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear bit */ 24535718cef0SMichael Rolnik tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */ 24545718cef0SMichael Rolnik tcg_gen_or_tl(Rd, Rd, t1); 24555718cef0SMichael Rolnik return true; 24565718cef0SMichael Rolnik } 24575718cef0SMichael Rolnik 24585718cef0SMichael Rolnik /* 24595718cef0SMichael Rolnik * Sets a single Flag or bit in SREG. 24605718cef0SMichael Rolnik */ 24615718cef0SMichael Rolnik static bool trans_BSET(DisasContext *ctx, arg_BSET *a) 24625718cef0SMichael Rolnik { 24635718cef0SMichael Rolnik switch (a->bit) { 24645718cef0SMichael Rolnik case 0x00: 24655718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Cf, 0x01); 24665718cef0SMichael Rolnik break; 24675718cef0SMichael Rolnik case 0x01: 24685718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Zf, 0x01); 24695718cef0SMichael Rolnik break; 24705718cef0SMichael Rolnik case 0x02: 24715718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Nf, 0x01); 24725718cef0SMichael Rolnik break; 24735718cef0SMichael Rolnik case 0x03: 24745718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Vf, 0x01); 24755718cef0SMichael Rolnik break; 24765718cef0SMichael Rolnik case 0x04: 24775718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Sf, 0x01); 24785718cef0SMichael Rolnik break; 24795718cef0SMichael Rolnik case 0x05: 24805718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Hf, 0x01); 24815718cef0SMichael Rolnik break; 24825718cef0SMichael Rolnik case 0x06: 24835718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Tf, 0x01); 24845718cef0SMichael Rolnik break; 24855718cef0SMichael Rolnik case 0x07: 24865718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_If, 0x01); 24875718cef0SMichael Rolnik break; 24885718cef0SMichael Rolnik } 24895718cef0SMichael Rolnik 24905718cef0SMichael Rolnik return true; 24915718cef0SMichael Rolnik } 24925718cef0SMichael Rolnik 24935718cef0SMichael Rolnik /* 24945718cef0SMichael Rolnik * Clears a single Flag in SREG. 24955718cef0SMichael Rolnik */ 24965718cef0SMichael Rolnik static bool trans_BCLR(DisasContext *ctx, arg_BCLR *a) 24975718cef0SMichael Rolnik { 24985718cef0SMichael Rolnik switch (a->bit) { 24995718cef0SMichael Rolnik case 0x00: 25005718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Cf, 0x00); 25015718cef0SMichael Rolnik break; 25025718cef0SMichael Rolnik case 0x01: 25035718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Zf, 0x00); 25045718cef0SMichael Rolnik break; 25055718cef0SMichael Rolnik case 0x02: 25065718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Nf, 0x00); 25075718cef0SMichael Rolnik break; 25085718cef0SMichael Rolnik case 0x03: 25095718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Vf, 0x00); 25105718cef0SMichael Rolnik break; 25115718cef0SMichael Rolnik case 0x04: 25125718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Sf, 0x00); 25135718cef0SMichael Rolnik break; 25145718cef0SMichael Rolnik case 0x05: 25155718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Hf, 0x00); 25165718cef0SMichael Rolnik break; 25175718cef0SMichael Rolnik case 0x06: 25185718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_Tf, 0x00); 25195718cef0SMichael Rolnik break; 25205718cef0SMichael Rolnik case 0x07: 25215718cef0SMichael Rolnik tcg_gen_movi_tl(cpu_If, 0x00); 25225718cef0SMichael Rolnik break; 25235718cef0SMichael Rolnik } 25245718cef0SMichael Rolnik 25255718cef0SMichael Rolnik return true; 25265718cef0SMichael Rolnik } 252746188cabSMichael Rolnik 252846188cabSMichael Rolnik /* 252946188cabSMichael Rolnik * MCU Control Instructions 253046188cabSMichael Rolnik */ 253146188cabSMichael Rolnik 253246188cabSMichael Rolnik /* 253346188cabSMichael Rolnik * The BREAK instruction is used by the On-chip Debug system, and is 253446188cabSMichael Rolnik * normally not used in the application software. When the BREAK instruction is 253546188cabSMichael Rolnik * executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip 253646188cabSMichael Rolnik * Debugger access to internal resources. If any Lock bits are set, or either 253746188cabSMichael Rolnik * the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK 253846188cabSMichael Rolnik * instruction as a NOP and will not enter the Stopped mode. This instruction 253946188cabSMichael Rolnik * is not available in all devices. Refer to the device specific instruction 254046188cabSMichael Rolnik * set summary. 254146188cabSMichael Rolnik */ 254246188cabSMichael Rolnik static bool trans_BREAK(DisasContext *ctx, arg_BREAK *a) 254346188cabSMichael Rolnik { 254446188cabSMichael Rolnik if (!avr_have_feature(ctx, AVR_FEATURE_BREAK)) { 254546188cabSMichael Rolnik return true; 254646188cabSMichael Rolnik } 254746188cabSMichael Rolnik 254846188cabSMichael Rolnik #ifdef BREAKPOINT_ON_BREAK 254946188cabSMichael Rolnik tcg_gen_movi_tl(cpu_pc, ctx->npc - 1); 255046188cabSMichael Rolnik gen_helper_debug(cpu_env); 255193d4d5e4SRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 255246188cabSMichael Rolnik #else 255346188cabSMichael Rolnik /* NOP */ 255446188cabSMichael Rolnik #endif 255546188cabSMichael Rolnik 255646188cabSMichael Rolnik return true; 255746188cabSMichael Rolnik } 255846188cabSMichael Rolnik 255946188cabSMichael Rolnik /* 256046188cabSMichael Rolnik * This instruction performs a single cycle No Operation. 256146188cabSMichael Rolnik */ 256246188cabSMichael Rolnik static bool trans_NOP(DisasContext *ctx, arg_NOP *a) 256346188cabSMichael Rolnik { 256446188cabSMichael Rolnik 256546188cabSMichael Rolnik /* NOP */ 256646188cabSMichael Rolnik 256746188cabSMichael Rolnik return true; 256846188cabSMichael Rolnik } 256946188cabSMichael Rolnik 257046188cabSMichael Rolnik /* 257146188cabSMichael Rolnik * This instruction sets the circuit in sleep mode defined by the MCU 257246188cabSMichael Rolnik * Control Register. 257346188cabSMichael Rolnik */ 257446188cabSMichael Rolnik static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a) 257546188cabSMichael Rolnik { 257646188cabSMichael Rolnik gen_helper_sleep(cpu_env); 257793d4d5e4SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 257846188cabSMichael Rolnik return true; 257946188cabSMichael Rolnik } 258046188cabSMichael Rolnik 258146188cabSMichael Rolnik /* 258246188cabSMichael Rolnik * This instruction resets the Watchdog Timer. This instruction must be 258346188cabSMichael Rolnik * executed within a limited time given by the WD prescaler. See the Watchdog 258446188cabSMichael Rolnik * Timer hardware specification. 258546188cabSMichael Rolnik */ 258646188cabSMichael Rolnik static bool trans_WDR(DisasContext *ctx, arg_WDR *a) 258746188cabSMichael Rolnik { 258846188cabSMichael Rolnik gen_helper_wdr(cpu_env); 258946188cabSMichael Rolnik 259046188cabSMichael Rolnik return true; 259146188cabSMichael Rolnik } 25929baade8dSMichael Rolnik 25939baade8dSMichael Rolnik /* 25949baade8dSMichael Rolnik * Core translation mechanism functions: 25959baade8dSMichael Rolnik * 25969baade8dSMichael Rolnik * - translate() 25979baade8dSMichael Rolnik * - canonicalize_skip() 25989baade8dSMichael Rolnik * - gen_intermediate_code() 25999baade8dSMichael Rolnik * - restore_state_to_opc() 26009baade8dSMichael Rolnik * 26019baade8dSMichael Rolnik */ 26029baade8dSMichael Rolnik static void translate(DisasContext *ctx) 26039baade8dSMichael Rolnik { 26049baade8dSMichael Rolnik uint32_t opcode = next_word(ctx); 26059baade8dSMichael Rolnik 26069baade8dSMichael Rolnik if (!decode_insn(ctx, opcode)) { 26079baade8dSMichael Rolnik gen_helper_unsupported(cpu_env); 260893d4d5e4SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 26099baade8dSMichael Rolnik } 26109baade8dSMichael Rolnik } 26119baade8dSMichael Rolnik 26129baade8dSMichael Rolnik /* Standardize the cpu_skip condition to NE. */ 26139baade8dSMichael Rolnik static bool canonicalize_skip(DisasContext *ctx) 26149baade8dSMichael Rolnik { 26159baade8dSMichael Rolnik switch (ctx->skip_cond) { 26169baade8dSMichael Rolnik case TCG_COND_NEVER: 26179baade8dSMichael Rolnik /* Normal case: cpu_skip is known to be false. */ 26189baade8dSMichael Rolnik return false; 26199baade8dSMichael Rolnik 26209baade8dSMichael Rolnik case TCG_COND_ALWAYS: 26219baade8dSMichael Rolnik /* 26229baade8dSMichael Rolnik * Breakpoint case: cpu_skip is known to be true, via TB_FLAGS_SKIP. 26239baade8dSMichael Rolnik * The breakpoint is on the instruction being skipped, at the start 26249baade8dSMichael Rolnik * of the TranslationBlock. No need to update. 26259baade8dSMichael Rolnik */ 26269baade8dSMichael Rolnik return false; 26279baade8dSMichael Rolnik 26289baade8dSMichael Rolnik case TCG_COND_NE: 26299baade8dSMichael Rolnik if (ctx->skip_var1 == NULL) { 26309baade8dSMichael Rolnik tcg_gen_mov_tl(cpu_skip, ctx->skip_var0); 26319baade8dSMichael Rolnik } else { 26329baade8dSMichael Rolnik tcg_gen_xor_tl(cpu_skip, ctx->skip_var0, ctx->skip_var1); 26339baade8dSMichael Rolnik ctx->skip_var1 = NULL; 26349baade8dSMichael Rolnik } 26359baade8dSMichael Rolnik break; 26369baade8dSMichael Rolnik 26379baade8dSMichael Rolnik default: 26389baade8dSMichael Rolnik /* Convert to a NE condition vs 0. */ 26399baade8dSMichael Rolnik if (ctx->skip_var1 == NULL) { 26409baade8dSMichael Rolnik tcg_gen_setcondi_tl(ctx->skip_cond, cpu_skip, ctx->skip_var0, 0); 26419baade8dSMichael Rolnik } else { 26429baade8dSMichael Rolnik tcg_gen_setcond_tl(ctx->skip_cond, cpu_skip, 26439baade8dSMichael Rolnik ctx->skip_var0, ctx->skip_var1); 26449baade8dSMichael Rolnik ctx->skip_var1 = NULL; 26459baade8dSMichael Rolnik } 26469baade8dSMichael Rolnik ctx->skip_cond = TCG_COND_NE; 26479baade8dSMichael Rolnik break; 26489baade8dSMichael Rolnik } 26499baade8dSMichael Rolnik ctx->skip_var0 = cpu_skip; 26509baade8dSMichael Rolnik return true; 26519baade8dSMichael Rolnik } 26529baade8dSMichael Rolnik 26533fbd28d8SRichard Henderson static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 26543fbd28d8SRichard Henderson { 26553fbd28d8SRichard Henderson DisasContext *ctx = container_of(dcbase, DisasContext, base); 26569baade8dSMichael Rolnik CPUAVRState *env = cs->env_ptr; 26573fbd28d8SRichard Henderson uint32_t tb_flags = ctx->base.tb->flags; 26589baade8dSMichael Rolnik 26593fbd28d8SRichard Henderson ctx->cs = cs; 26603fbd28d8SRichard Henderson ctx->env = env; 26613fbd28d8SRichard Henderson ctx->npc = ctx->base.pc_first / 2; 26629baade8dSMichael Rolnik 26633fbd28d8SRichard Henderson ctx->skip_cond = TCG_COND_NEVER; 26643fbd28d8SRichard Henderson if (tb_flags & TB_FLAGS_SKIP) { 2665bcef6d76SRichard Henderson ctx->skip_cond = TCG_COND_ALWAYS; 2666bcef6d76SRichard Henderson ctx->skip_var0 = cpu_skip; 26679baade8dSMichael Rolnik } 26689baade8dSMichael Rolnik 26693fbd28d8SRichard Henderson if (tb_flags & TB_FLAGS_FULL_ACCESS) { 26703fbd28d8SRichard Henderson /* 26713fbd28d8SRichard Henderson * This flag is set by ST/LD instruction we will regenerate it ONLY 26723fbd28d8SRichard Henderson * with mem/cpu memory access instead of mem access 26733fbd28d8SRichard Henderson */ 26743fbd28d8SRichard Henderson ctx->base.max_insns = 1; 26753fbd28d8SRichard Henderson } 26763fbd28d8SRichard Henderson } 26773fbd28d8SRichard Henderson 26783fbd28d8SRichard Henderson static void avr_tr_tb_start(DisasContextBase *db, CPUState *cs) 26793fbd28d8SRichard Henderson { 26803fbd28d8SRichard Henderson } 26813fbd28d8SRichard Henderson 26823fbd28d8SRichard Henderson static void avr_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 26833fbd28d8SRichard Henderson { 26843fbd28d8SRichard Henderson DisasContext *ctx = container_of(dcbase, DisasContext, base); 26853fbd28d8SRichard Henderson 26863fbd28d8SRichard Henderson tcg_gen_insn_start(ctx->npc); 26873fbd28d8SRichard Henderson } 26883fbd28d8SRichard Henderson 26893fbd28d8SRichard Henderson static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 26903fbd28d8SRichard Henderson { 26913fbd28d8SRichard Henderson DisasContext *ctx = container_of(dcbase, DisasContext, base); 26929baade8dSMichael Rolnik TCGLabel *skip_label = NULL; 26939baade8dSMichael Rolnik 26949baade8dSMichael Rolnik /* Conditionally skip the next instruction, if indicated. */ 2695bcef6d76SRichard Henderson if (ctx->skip_cond != TCG_COND_NEVER) { 26969baade8dSMichael Rolnik skip_label = gen_new_label(); 2697bcef6d76SRichard Henderson if (ctx->skip_var0 == cpu_skip) { 26989baade8dSMichael Rolnik /* 26999baade8dSMichael Rolnik * Copy cpu_skip so that we may zero it before the branch. 27009baade8dSMichael Rolnik * This ensures that cpu_skip is non-zero after the label 27019baade8dSMichael Rolnik * if and only if the skipped insn itself sets a skip. 27029baade8dSMichael Rolnik */ 2703bcef6d76SRichard Henderson ctx->skip_var0 = tcg_temp_new(); 2704bcef6d76SRichard Henderson tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); 27059baade8dSMichael Rolnik tcg_gen_movi_tl(cpu_skip, 0); 27069baade8dSMichael Rolnik } 2707bcef6d76SRichard Henderson if (ctx->skip_var1 == NULL) { 27083fbd28d8SRichard Henderson tcg_gen_brcondi_tl(ctx->skip_cond, ctx->skip_var0, 0, skip_label); 27099baade8dSMichael Rolnik } else { 2710bcef6d76SRichard Henderson tcg_gen_brcond_tl(ctx->skip_cond, ctx->skip_var0, 2711bcef6d76SRichard Henderson ctx->skip_var1, skip_label); 2712bcef6d76SRichard Henderson ctx->skip_var1 = NULL; 27139baade8dSMichael Rolnik } 2714bcef6d76SRichard Henderson ctx->skip_cond = TCG_COND_NEVER; 2715bcef6d76SRichard Henderson ctx->skip_var0 = NULL; 27169baade8dSMichael Rolnik } 27179baade8dSMichael Rolnik 2718bcef6d76SRichard Henderson translate(ctx); 27199baade8dSMichael Rolnik 27203fbd28d8SRichard Henderson ctx->base.pc_next = ctx->npc * 2; 27213fbd28d8SRichard Henderson 27229baade8dSMichael Rolnik if (skip_label) { 2723bcef6d76SRichard Henderson canonicalize_skip(ctx); 27249baade8dSMichael Rolnik gen_set_label(skip_label); 272536027c70SRichard Henderson 272636027c70SRichard Henderson switch (ctx->base.is_jmp) { 272736027c70SRichard Henderson case DISAS_NORETURN: 2728bcef6d76SRichard Henderson ctx->base.is_jmp = DISAS_CHAIN; 272936027c70SRichard Henderson break; 273036027c70SRichard Henderson case DISAS_NEXT: 273136027c70SRichard Henderson if (ctx->base.tb->flags & TB_FLAGS_SKIP) { 273236027c70SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 273336027c70SRichard Henderson } 273436027c70SRichard Henderson break; 273536027c70SRichard Henderson default: 273636027c70SRichard Henderson break; 27379baade8dSMichael Rolnik } 27389baade8dSMichael Rolnik } 27399baade8dSMichael Rolnik 27403fbd28d8SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT) { 27413fbd28d8SRichard Henderson target_ulong page_first = ctx->base.pc_first & TARGET_PAGE_MASK; 27423fbd28d8SRichard Henderson 27433fbd28d8SRichard Henderson if ((ctx->base.pc_next - page_first) >= TARGET_PAGE_SIZE - 4) { 27443fbd28d8SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 27453fbd28d8SRichard Henderson } 27463fbd28d8SRichard Henderson } 27479baade8dSMichael Rolnik } 27489baade8dSMichael Rolnik 27493fbd28d8SRichard Henderson static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 27503fbd28d8SRichard Henderson { 27513fbd28d8SRichard Henderson DisasContext *ctx = container_of(dcbase, DisasContext, base); 2752bcef6d76SRichard Henderson bool nonconst_skip = canonicalize_skip(ctx); 275336027c70SRichard Henderson /* 275436027c70SRichard Henderson * Because we disable interrupts while env->skip is set, 275536027c70SRichard Henderson * we must return to the main loop to re-evaluate afterward. 275636027c70SRichard Henderson */ 275736027c70SRichard Henderson bool force_exit = ctx->base.tb->flags & TB_FLAGS_SKIP; 27589baade8dSMichael Rolnik 2759bcef6d76SRichard Henderson switch (ctx->base.is_jmp) { 27609baade8dSMichael Rolnik case DISAS_NORETURN: 27619baade8dSMichael Rolnik assert(!nonconst_skip); 27629baade8dSMichael Rolnik break; 27639baade8dSMichael Rolnik case DISAS_NEXT: 27649baade8dSMichael Rolnik case DISAS_TOO_MANY: 27659baade8dSMichael Rolnik case DISAS_CHAIN: 276636027c70SRichard Henderson if (!nonconst_skip && !force_exit) { 27679baade8dSMichael Rolnik /* Note gen_goto_tb checks singlestep. */ 2768bcef6d76SRichard Henderson gen_goto_tb(ctx, 1, ctx->npc); 27699baade8dSMichael Rolnik break; 27709baade8dSMichael Rolnik } 2771bcef6d76SRichard Henderson tcg_gen_movi_tl(cpu_pc, ctx->npc); 27729baade8dSMichael Rolnik /* fall through */ 27739baade8dSMichael Rolnik case DISAS_LOOKUP: 277436027c70SRichard Henderson if (!force_exit) { 27759baade8dSMichael Rolnik tcg_gen_lookup_and_goto_ptr(); 27769baade8dSMichael Rolnik break; 277736027c70SRichard Henderson } 277836027c70SRichard Henderson /* fall through */ 27799baade8dSMichael Rolnik case DISAS_EXIT: 27809baade8dSMichael Rolnik tcg_gen_exit_tb(NULL, 0); 27819baade8dSMichael Rolnik break; 27829baade8dSMichael Rolnik default: 27839baade8dSMichael Rolnik g_assert_not_reached(); 27849baade8dSMichael Rolnik } 27859d8caa67SMichael Rolnik } 27863fbd28d8SRichard Henderson 27878eb806a7SRichard Henderson static void avr_tr_disas_log(const DisasContextBase *dcbase, 27888eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 27893fbd28d8SRichard Henderson { 27908eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 27918eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 27923fbd28d8SRichard Henderson } 27933fbd28d8SRichard Henderson 27943fbd28d8SRichard Henderson static const TranslatorOps avr_tr_ops = { 27953fbd28d8SRichard Henderson .init_disas_context = avr_tr_init_disas_context, 27963fbd28d8SRichard Henderson .tb_start = avr_tr_tb_start, 27973fbd28d8SRichard Henderson .insn_start = avr_tr_insn_start, 27983fbd28d8SRichard Henderson .translate_insn = avr_tr_translate_insn, 27993fbd28d8SRichard Henderson .tb_stop = avr_tr_tb_stop, 28003fbd28d8SRichard Henderson .disas_log = avr_tr_disas_log, 28013fbd28d8SRichard Henderson }; 28023fbd28d8SRichard Henderson 2803597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 2804306c8721SRichard Henderson target_ulong pc, void *host_pc) 28053fbd28d8SRichard Henderson { 28063fbd28d8SRichard Henderson DisasContext dc = { }; 2807306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base); 28089baade8dSMichael Rolnik } 2809