1 /* 2 * QEMU AVR CPU helpers 3 * 4 * Copyright (c) 2016-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/log.h" 23 #include "qemu/error-report.h" 24 #include "cpu.h" 25 #include "hw/core/tcg-cpu-ops.h" 26 #include "exec/exec-all.h" 27 #include "exec/cpu_ldst.h" 28 #include "exec/address-spaces.h" 29 #include "exec/helper-proto.h" 30 31 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 32 { 33 CPUAVRState *env = cpu_env(cs); 34 35 /* 36 * We cannot separate a skip from the next instruction, 37 * as the skip would not be preserved across the interrupt. 38 * Separating the two insn normally only happens at page boundaries. 39 */ 40 if (env->skip) { 41 return false; 42 } 43 44 if (interrupt_request & CPU_INTERRUPT_RESET) { 45 if (cpu_interrupts_enabled(env)) { 46 cs->exception_index = EXCP_RESET; 47 avr_cpu_do_interrupt(cs); 48 49 cs->interrupt_request &= ~CPU_INTERRUPT_RESET; 50 return true; 51 } 52 } 53 if (interrupt_request & CPU_INTERRUPT_HARD) { 54 if (cpu_interrupts_enabled(env) && env->intsrc != 0) { 55 int index = ctz64(env->intsrc); 56 cs->exception_index = EXCP_INT(index); 57 avr_cpu_do_interrupt(cs); 58 59 env->intsrc &= env->intsrc - 1; /* clear the interrupt */ 60 if (!env->intsrc) { 61 cs->interrupt_request &= ~CPU_INTERRUPT_HARD; 62 } 63 return true; 64 } 65 } 66 return false; 67 } 68 69 void avr_cpu_do_interrupt(CPUState *cs) 70 { 71 CPUAVRState *env = cpu_env(cs); 72 73 uint32_t ret = env->pc_w; 74 int vector = 0; 75 int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1; 76 int base = 0; 77 78 if (cs->exception_index == EXCP_RESET) { 79 vector = 0; 80 } else if (env->intsrc != 0) { 81 vector = ctz64(env->intsrc) + 1; 82 } 83 84 if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { 85 cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); 86 cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); 87 cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16); 88 } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { 89 cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); 90 cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); 91 } else { 92 cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); 93 } 94 95 env->pc_w = base + vector * size; 96 env->sregI = 0; /* clear Global Interrupt Flag */ 97 98 cs->exception_index = -1; 99 } 100 101 hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 102 { 103 return addr; /* I assume 1:1 address correspondence */ 104 } 105 106 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 107 MMUAccessType access_type, int mmu_idx, 108 bool probe, uintptr_t retaddr) 109 { 110 int prot, page_size = TARGET_PAGE_SIZE; 111 uint32_t paddr; 112 113 address &= TARGET_PAGE_MASK; 114 115 if (mmu_idx == MMU_CODE_IDX) { 116 /* Access to code in flash. */ 117 paddr = OFFSET_CODE + address; 118 prot = PAGE_READ | PAGE_EXEC; 119 if (paddr >= OFFSET_DATA) { 120 /* 121 * This should not be possible via any architectural operations. 122 * There is certainly not an exception that we can deliver. 123 * Accept probing that might come from generic code. 124 */ 125 if (probe) { 126 return false; 127 } 128 error_report("execution left flash memory"); 129 abort(); 130 } 131 } else { 132 /* Access to memory. */ 133 paddr = OFFSET_DATA + address; 134 prot = PAGE_READ | PAGE_WRITE; 135 if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { 136 /* 137 * Access to CPU registers, exit and rebuilt this TB to use 138 * full access in case it touches specially handled registers 139 * like SREG or SP. For probing, set page_size = 1, in order 140 * to force tlb_fill to be called for the next access. 141 */ 142 if (probe) { 143 page_size = 1; 144 } else { 145 cpu_env(cs)->fullacc = 1; 146 cpu_loop_exit_restore(cs, retaddr); 147 } 148 } 149 } 150 151 tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size); 152 return true; 153 } 154 155 /* 156 * helpers 157 */ 158 159 void helper_sleep(CPUAVRState *env) 160 { 161 CPUState *cs = env_cpu(env); 162 163 cs->exception_index = EXCP_HLT; 164 cpu_loop_exit(cs); 165 } 166 167 void helper_unsupported(CPUAVRState *env) 168 { 169 CPUState *cs = env_cpu(env); 170 171 /* 172 * I count not find what happens on the real platform, so 173 * it's EXCP_DEBUG for meanwhile 174 */ 175 cs->exception_index = EXCP_DEBUG; 176 if (qemu_loglevel_mask(LOG_UNIMP)) { 177 qemu_log("UNSUPPORTED\n"); 178 cpu_dump_state(cs, stderr, 0); 179 } 180 cpu_loop_exit(cs); 181 } 182 183 void helper_debug(CPUAVRState *env) 184 { 185 CPUState *cs = env_cpu(env); 186 187 cs->exception_index = EXCP_DEBUG; 188 cpu_loop_exit(cs); 189 } 190 191 void helper_break(CPUAVRState *env) 192 { 193 CPUState *cs = env_cpu(env); 194 195 cs->exception_index = EXCP_DEBUG; 196 cpu_loop_exit(cs); 197 } 198 199 void helper_wdr(CPUAVRState *env) 200 { 201 qemu_log_mask(LOG_UNIMP, "WDG reset (not implemented)\n"); 202 } 203 204 /* 205 * This function implements IN instruction 206 * 207 * It does the following 208 * a. if an IO register belongs to CPU, its value is read and returned 209 * b. otherwise io address is translated to mem address and physical memory 210 * is read. 211 * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation 212 * 213 */ 214 target_ulong helper_inb(CPUAVRState *env, uint32_t port) 215 { 216 target_ulong data = 0; 217 218 switch (port) { 219 case 0x38: /* RAMPD */ 220 data = 0xff & (env->rampD >> 16); 221 break; 222 case 0x39: /* RAMPX */ 223 data = 0xff & (env->rampX >> 16); 224 break; 225 case 0x3a: /* RAMPY */ 226 data = 0xff & (env->rampY >> 16); 227 break; 228 case 0x3b: /* RAMPZ */ 229 data = 0xff & (env->rampZ >> 16); 230 break; 231 case 0x3c: /* EIND */ 232 data = 0xff & (env->eind >> 16); 233 break; 234 case 0x3d: /* SPL */ 235 data = env->sp & 0x00ff; 236 break; 237 case 0x3e: /* SPH */ 238 data = env->sp >> 8; 239 break; 240 case 0x3f: /* SREG */ 241 data = cpu_get_sreg(env); 242 break; 243 default: 244 /* not a special register, pass to normal memory access */ 245 data = address_space_ldub(&address_space_memory, 246 OFFSET_IO_REGISTERS + port, 247 MEMTXATTRS_UNSPECIFIED, NULL); 248 } 249 250 return data; 251 } 252 253 /* 254 * This function implements OUT instruction 255 * 256 * It does the following 257 * a. if an IO register belongs to CPU, its value is written into the register 258 * b. otherwise io address is translated to mem address and physical memory 259 * is written. 260 * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation 261 * 262 */ 263 void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data) 264 { 265 data &= 0x000000ff; 266 267 switch (port) { 268 case 0x38: /* RAMPD */ 269 if (avr_feature(env, AVR_FEATURE_RAMPD)) { 270 env->rampD = (data & 0xff) << 16; 271 } 272 break; 273 case 0x39: /* RAMPX */ 274 if (avr_feature(env, AVR_FEATURE_RAMPX)) { 275 env->rampX = (data & 0xff) << 16; 276 } 277 break; 278 case 0x3a: /* RAMPY */ 279 if (avr_feature(env, AVR_FEATURE_RAMPY)) { 280 env->rampY = (data & 0xff) << 16; 281 } 282 break; 283 case 0x3b: /* RAMPZ */ 284 if (avr_feature(env, AVR_FEATURE_RAMPZ)) { 285 env->rampZ = (data & 0xff) << 16; 286 } 287 break; 288 case 0x3c: /* EIDN */ 289 env->eind = (data & 0xff) << 16; 290 break; 291 case 0x3d: /* SPL */ 292 env->sp = (env->sp & 0xff00) | (data); 293 break; 294 case 0x3e: /* SPH */ 295 if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { 296 env->sp = (env->sp & 0x00ff) | (data << 8); 297 } 298 break; 299 case 0x3f: /* SREG */ 300 cpu_set_sreg(env, data); 301 break; 302 default: 303 /* not a special register, pass to normal memory access */ 304 address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port, 305 data, MEMTXATTRS_UNSPECIFIED, NULL); 306 } 307 } 308 309 /* 310 * this function implements LD instruction when there is a possibility to read 311 * from a CPU register 312 */ 313 target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr) 314 { 315 uint8_t data; 316 317 env->fullacc = false; 318 319 if (addr < NUMBER_OF_CPU_REGISTERS) { 320 /* CPU registers */ 321 data = env->r[addr]; 322 } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { 323 /* IO registers */ 324 data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS); 325 } else { 326 /* memory */ 327 data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr, 328 MEMTXATTRS_UNSPECIFIED, NULL); 329 } 330 return data; 331 } 332 333 /* 334 * this function implements ST instruction when there is a possibility to write 335 * into a CPU register 336 */ 337 void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) 338 { 339 env->fullacc = false; 340 341 /* Following logic assumes this: */ 342 assert(OFFSET_CPU_REGISTERS == OFFSET_DATA); 343 assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS + 344 NUMBER_OF_CPU_REGISTERS); 345 346 if (addr < NUMBER_OF_CPU_REGISTERS) { 347 /* CPU registers */ 348 env->r[addr] = data; 349 } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { 350 /* IO registers */ 351 helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data); 352 } else { 353 /* memory */ 354 address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, 355 MEMTXATTRS_UNSPECIFIED, NULL); 356 } 357 } 358