1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2016-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #ifndef QEMU_AVR_CPU_H 22 #define QEMU_AVR_CPU_H 23 24 #include "cpu-qom.h" 25 #include "exec/cpu-defs.h" 26 27 #ifdef CONFIG_USER_ONLY 28 #error "AVR 8-bit does not support user mode" 29 #endif 30 31 #define CPU_RESOLVING_TYPE TYPE_AVR_CPU 32 33 #define TCG_GUEST_DEFAULT_MO 0 34 35 /* 36 * AVR has two memory spaces, data & code. 37 * e.g. both have 0 address 38 * ST/LD instructions access data space 39 * LPM/SPM and instruction fetching access code memory space 40 */ 41 #define MMU_CODE_IDX 0 42 #define MMU_DATA_IDX 1 43 44 #define EXCP_RESET 1 45 #define EXCP_INT(n) (EXCP_RESET + (n) + 1) 46 47 /* Number of CPU registers */ 48 #define NUMBER_OF_CPU_REGISTERS 32 49 /* Number of IO registers accessible by ld/st/in/out */ 50 #define NUMBER_OF_IO_REGISTERS 64 51 52 /* 53 * Offsets of AVR memory regions in host memory space. 54 * 55 * This is needed because the AVR has separate code and data address 56 * spaces that both have start from zero but have to go somewhere in 57 * host memory. 58 * 59 * It's also useful to know where some things are, like the IO registers. 60 */ 61 /* Flash program memory */ 62 #define OFFSET_CODE 0x00000000 63 /* CPU registers, IO registers, and SRAM */ 64 #define OFFSET_DATA 0x00800000 65 /* CPU registers specifically, these are mapped at the start of data */ 66 #define OFFSET_CPU_REGISTERS OFFSET_DATA 67 /* 68 * IO registers, including status register, stack pointer, and memory 69 * mapped peripherals, mapped just after CPU registers 70 */ 71 #define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS) 72 73 typedef enum AVRFeature { 74 AVR_FEATURE_SRAM, 75 76 AVR_FEATURE_1_BYTE_PC, 77 AVR_FEATURE_2_BYTE_PC, 78 AVR_FEATURE_3_BYTE_PC, 79 80 AVR_FEATURE_1_BYTE_SP, 81 AVR_FEATURE_2_BYTE_SP, 82 83 AVR_FEATURE_BREAK, 84 AVR_FEATURE_DES, 85 AVR_FEATURE_RMW, /* Read Modify Write - XCH LAC LAS LAT */ 86 87 AVR_FEATURE_EIJMP_EICALL, 88 AVR_FEATURE_IJMP_ICALL, 89 AVR_FEATURE_JMP_CALL, 90 91 AVR_FEATURE_ADIW_SBIW, 92 93 AVR_FEATURE_SPM, 94 AVR_FEATURE_SPMX, 95 96 AVR_FEATURE_ELPMX, 97 AVR_FEATURE_ELPM, 98 AVR_FEATURE_LPMX, 99 AVR_FEATURE_LPM, 100 101 AVR_FEATURE_MOVW, 102 AVR_FEATURE_MUL, 103 AVR_FEATURE_RAMPD, 104 AVR_FEATURE_RAMPX, 105 AVR_FEATURE_RAMPY, 106 AVR_FEATURE_RAMPZ, 107 } AVRFeature; 108 109 typedef struct CPUArchState { 110 uint32_t pc_w; /* 0x003fffff up to 22 bits */ 111 112 uint32_t sregC; /* 0x00000001 1 bit */ 113 uint32_t sregZ; /* 0x00000001 1 bit */ 114 uint32_t sregN; /* 0x00000001 1 bit */ 115 uint32_t sregV; /* 0x00000001 1 bit */ 116 uint32_t sregS; /* 0x00000001 1 bit */ 117 uint32_t sregH; /* 0x00000001 1 bit */ 118 uint32_t sregT; /* 0x00000001 1 bit */ 119 uint32_t sregI; /* 0x00000001 1 bit */ 120 121 uint32_t rampD; /* 0x00ff0000 8 bits */ 122 uint32_t rampX; /* 0x00ff0000 8 bits */ 123 uint32_t rampY; /* 0x00ff0000 8 bits */ 124 uint32_t rampZ; /* 0x00ff0000 8 bits */ 125 uint32_t eind; /* 0x00ff0000 8 bits */ 126 127 uint32_t r[NUMBER_OF_CPU_REGISTERS]; /* 8 bits each */ 128 uint32_t sp; /* 16 bits */ 129 130 uint32_t skip; /* if set skip instruction */ 131 132 uint64_t intsrc; /* interrupt sources */ 133 bool fullacc; /* CPU/MEM if true MEM only otherwise */ 134 135 uint64_t features; 136 } CPUAVRState; 137 138 /** 139 * AVRCPU: 140 * @env: #CPUAVRState 141 * 142 * A AVR CPU. 143 */ 144 struct ArchCPU { 145 CPUState parent_obj; 146 147 CPUAVRState env; 148 149 /* Initial value of stack pointer */ 150 uint32_t init_sp; 151 }; 152 153 /** 154 * AVRCPUClass: 155 * @parent_realize: The parent class' realize handler. 156 * @parent_phases: The parent class' reset phase handlers. 157 * 158 * A AVR CPU model. 159 */ 160 struct AVRCPUClass { 161 CPUClass parent_class; 162 163 DeviceRealize parent_realize; 164 ResettablePhases parent_phases; 165 }; 166 167 extern const struct VMStateDescription vms_avr_cpu; 168 169 void avr_cpu_do_interrupt(CPUState *cpu); 170 bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req); 171 hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 172 int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 173 int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 174 int avr_print_insn(bfd_vma addr, disassemble_info *info); 175 vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); 176 177 static inline int avr_feature(CPUAVRState *env, AVRFeature feature) 178 { 179 return (env->features & (1U << feature)) != 0; 180 } 181 182 static inline void set_avr_feature(CPUAVRState *env, int feature) 183 { 184 env->features |= (1U << feature); 185 } 186 187 #define cpu_mmu_index avr_cpu_mmu_index 188 189 static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) 190 { 191 return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; 192 } 193 194 void avr_cpu_tcg_init(void); 195 196 int cpu_avr_exec(CPUState *cpu); 197 198 enum { 199 TB_FLAGS_FULL_ACCESS = 1, 200 TB_FLAGS_SKIP = 2, 201 }; 202 203 static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, 204 uint64_t *cs_base, uint32_t *pflags) 205 { 206 uint32_t flags = 0; 207 208 *pc = env->pc_w * 2; 209 *cs_base = 0; 210 211 if (env->fullacc) { 212 flags |= TB_FLAGS_FULL_ACCESS; 213 } 214 if (env->skip) { 215 flags |= TB_FLAGS_SKIP; 216 } 217 218 *pflags = flags; 219 } 220 221 static inline int cpu_interrupts_enabled(CPUAVRState *env) 222 { 223 return env->sregI != 0; 224 } 225 226 static inline uint8_t cpu_get_sreg(CPUAVRState *env) 227 { 228 return (env->sregC) << 0 229 | (env->sregZ) << 1 230 | (env->sregN) << 2 231 | (env->sregV) << 3 232 | (env->sregS) << 4 233 | (env->sregH) << 5 234 | (env->sregT) << 6 235 | (env->sregI) << 7; 236 } 237 238 static inline void cpu_set_sreg(CPUAVRState *env, uint8_t sreg) 239 { 240 env->sregC = (sreg >> 0) & 0x01; 241 env->sregZ = (sreg >> 1) & 0x01; 242 env->sregN = (sreg >> 2) & 0x01; 243 env->sregV = (sreg >> 3) & 0x01; 244 env->sregS = (sreg >> 4) & 0x01; 245 env->sregH = (sreg >> 5) & 0x01; 246 env->sregT = (sreg >> 6) & 0x01; 247 env->sregI = (sreg >> 7) & 0x01; 248 } 249 250 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 251 MMUAccessType access_type, int mmu_idx, 252 bool probe, uintptr_t retaddr); 253 254 #include "exec/cpu-all.h" 255 256 #endif /* QEMU_AVR_CPU_H */ 257