1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2019-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/qemu-print.h" 24 #include "exec/exec-all.h" 25 #include "cpu.h" 26 #include "disas/dis-asm.h" 27 #include "tcg/debug-assert.h" 28 29 static void avr_cpu_set_pc(CPUState *cs, vaddr value) 30 { 31 AVRCPU *cpu = AVR_CPU(cs); 32 33 cpu->env.pc_w = value / 2; /* internally PC points to words */ 34 } 35 36 static vaddr avr_cpu_get_pc(CPUState *cs) 37 { 38 AVRCPU *cpu = AVR_CPU(cs); 39 40 return cpu->env.pc_w * 2; 41 } 42 43 static bool avr_cpu_has_work(CPUState *cs) 44 { 45 AVRCPU *cpu = AVR_CPU(cs); 46 CPUAVRState *env = &cpu->env; 47 48 return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) 49 && cpu_interrupts_enabled(env); 50 } 51 52 static void avr_cpu_synchronize_from_tb(CPUState *cs, 53 const TranslationBlock *tb) 54 { 55 AVRCPU *cpu = AVR_CPU(cs); 56 CPUAVRState *env = &cpu->env; 57 58 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 59 env->pc_w = tb->pc / 2; /* internally PC points to words */ 60 } 61 62 static void avr_restore_state_to_opc(CPUState *cs, 63 const TranslationBlock *tb, 64 const uint64_t *data) 65 { 66 AVRCPU *cpu = AVR_CPU(cs); 67 CPUAVRState *env = &cpu->env; 68 69 env->pc_w = data[0]; 70 } 71 72 static void avr_cpu_reset_hold(Object *obj) 73 { 74 CPUState *cs = CPU(obj); 75 AVRCPU *cpu = AVR_CPU(cs); 76 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu); 77 CPUAVRState *env = &cpu->env; 78 79 if (mcc->parent_phases.hold) { 80 mcc->parent_phases.hold(obj); 81 } 82 83 env->pc_w = 0; 84 env->sregI = 1; 85 env->sregC = 0; 86 env->sregZ = 0; 87 env->sregN = 0; 88 env->sregV = 0; 89 env->sregS = 0; 90 env->sregH = 0; 91 env->sregT = 0; 92 93 env->rampD = 0; 94 env->rampX = 0; 95 env->rampY = 0; 96 env->rampZ = 0; 97 env->eind = 0; 98 env->sp = 0; 99 100 env->skip = 0; 101 102 memset(env->r, 0, sizeof(env->r)); 103 } 104 105 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 106 { 107 info->mach = bfd_arch_avr; 108 info->print_insn = avr_print_insn; 109 } 110 111 static void avr_cpu_realizefn(DeviceState *dev, Error **errp) 112 { 113 CPUState *cs = CPU(dev); 114 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); 115 Error *local_err = NULL; 116 117 cpu_exec_realizefn(cs, &local_err); 118 if (local_err != NULL) { 119 error_propagate(errp, local_err); 120 return; 121 } 122 qemu_init_vcpu(cs); 123 cpu_reset(cs); 124 125 mcc->parent_realize(dev, errp); 126 } 127 128 static void avr_cpu_set_int(void *opaque, int irq, int level) 129 { 130 AVRCPU *cpu = opaque; 131 CPUAVRState *env = &cpu->env; 132 CPUState *cs = CPU(cpu); 133 uint64_t mask = (1ull << irq); 134 135 if (level) { 136 env->intsrc |= mask; 137 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 138 } else { 139 env->intsrc &= ~mask; 140 if (env->intsrc == 0) { 141 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 142 } 143 } 144 } 145 146 static void avr_cpu_initfn(Object *obj) 147 { 148 AVRCPU *cpu = AVR_CPU(obj); 149 150 /* Set the number of interrupts supported by the CPU. */ 151 qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 152 sizeof(cpu->env.intsrc) * 8); 153 } 154 155 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) 156 { 157 ObjectClass *oc; 158 159 oc = object_class_by_name(cpu_model); 160 if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL) { 161 oc = NULL; 162 } 163 return oc; 164 } 165 166 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) 167 { 168 AVRCPU *cpu = AVR_CPU(cs); 169 CPUAVRState *env = &cpu->env; 170 int i; 171 172 qemu_fprintf(f, "\n"); 173 qemu_fprintf(f, "PC: %06x\n", env->pc_w * 2); /* PC points to words */ 174 qemu_fprintf(f, "SP: %04x\n", env->sp); 175 qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16); 176 qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16); 177 qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16); 178 qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16); 179 qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16); 180 qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]); 181 qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]); 182 qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]); 183 qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n", 184 env->sregI ? 'I' : '-', 185 env->sregT ? 'T' : '-', 186 env->sregH ? 'H' : '-', 187 env->sregS ? 'S' : '-', 188 env->sregV ? 'V' : '-', 189 env->sregN ? '-' : 'N', /* Zf has negative logic */ 190 env->sregZ ? 'Z' : '-', 191 env->sregC ? 'I' : '-'); 192 qemu_fprintf(f, "SKIP: %02x\n", env->skip); 193 194 qemu_fprintf(f, "\n"); 195 for (i = 0; i < ARRAY_SIZE(env->r); i++) { 196 qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]); 197 198 if ((i % 8) == 7) { 199 qemu_fprintf(f, "\n"); 200 } 201 } 202 qemu_fprintf(f, "\n"); 203 } 204 205 #include "hw/core/sysemu-cpu-ops.h" 206 207 static const struct SysemuCPUOps avr_sysemu_ops = { 208 .get_phys_page_debug = avr_cpu_get_phys_page_debug, 209 }; 210 211 #include "hw/core/tcg-cpu-ops.h" 212 213 static const struct TCGCPUOps avr_tcg_ops = { 214 .initialize = avr_cpu_tcg_init, 215 .synchronize_from_tb = avr_cpu_synchronize_from_tb, 216 .restore_state_to_opc = avr_restore_state_to_opc, 217 .cpu_exec_interrupt = avr_cpu_exec_interrupt, 218 .tlb_fill = avr_cpu_tlb_fill, 219 .do_interrupt = avr_cpu_do_interrupt, 220 }; 221 222 static void avr_cpu_class_init(ObjectClass *oc, void *data) 223 { 224 DeviceClass *dc = DEVICE_CLASS(oc); 225 CPUClass *cc = CPU_CLASS(oc); 226 AVRCPUClass *mcc = AVR_CPU_CLASS(oc); 227 ResettableClass *rc = RESETTABLE_CLASS(oc); 228 229 device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize); 230 231 resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL, 232 &mcc->parent_phases); 233 234 cc->class_by_name = avr_cpu_class_by_name; 235 236 cc->has_work = avr_cpu_has_work; 237 cc->dump_state = avr_cpu_dump_state; 238 cc->set_pc = avr_cpu_set_pc; 239 cc->get_pc = avr_cpu_get_pc; 240 dc->vmsd = &vms_avr_cpu; 241 cc->sysemu_ops = &avr_sysemu_ops; 242 cc->disas_set_info = avr_cpu_disas_set_info; 243 cc->gdb_read_register = avr_cpu_gdb_read_register; 244 cc->gdb_write_register = avr_cpu_gdb_write_register; 245 cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint; 246 cc->gdb_num_core_regs = 35; 247 cc->gdb_core_xml_file = "avr-cpu.xml"; 248 cc->tcg_ops = &avr_tcg_ops; 249 } 250 251 /* 252 * Setting features of AVR core type avr5 253 * -------------------------------------- 254 * 255 * This type of AVR core is present in the following AVR MCUs: 256 * 257 * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c, 258 * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162, 259 * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, 260 * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, 261 * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb, 262 * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323, 263 * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, 264 * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, 265 * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa, 266 * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1, 267 * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644, 268 * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, 269 * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, 270 * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p, 271 * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2, 272 * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216, 273 * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000 274 */ 275 static void avr_avr5_initfn(Object *obj) 276 { 277 AVRCPU *cpu = AVR_CPU(obj); 278 CPUAVRState *env = &cpu->env; 279 280 set_avr_feature(env, AVR_FEATURE_LPM); 281 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 282 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 283 set_avr_feature(env, AVR_FEATURE_SRAM); 284 set_avr_feature(env, AVR_FEATURE_BREAK); 285 286 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 287 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 288 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 289 set_avr_feature(env, AVR_FEATURE_LPMX); 290 set_avr_feature(env, AVR_FEATURE_MOVW); 291 set_avr_feature(env, AVR_FEATURE_MUL); 292 } 293 294 /* 295 * Setting features of AVR core type avr51 296 * -------------------------------------- 297 * 298 * This type of AVR core is present in the following AVR MCUs: 299 * 300 * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p, 301 * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 302 * at90usb1287 303 */ 304 static void avr_avr51_initfn(Object *obj) 305 { 306 AVRCPU *cpu = AVR_CPU(obj); 307 CPUAVRState *env = &cpu->env; 308 309 set_avr_feature(env, AVR_FEATURE_LPM); 310 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 311 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 312 set_avr_feature(env, AVR_FEATURE_SRAM); 313 set_avr_feature(env, AVR_FEATURE_BREAK); 314 315 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 316 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 317 set_avr_feature(env, AVR_FEATURE_RAMPZ); 318 set_avr_feature(env, AVR_FEATURE_ELPMX); 319 set_avr_feature(env, AVR_FEATURE_ELPM); 320 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 321 set_avr_feature(env, AVR_FEATURE_LPMX); 322 set_avr_feature(env, AVR_FEATURE_MOVW); 323 set_avr_feature(env, AVR_FEATURE_MUL); 324 } 325 326 /* 327 * Setting features of AVR core type avr6 328 * -------------------------------------- 329 * 330 * This type of AVR core is present in the following AVR MCUs: 331 * 332 * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2 333 */ 334 static void avr_avr6_initfn(Object *obj) 335 { 336 AVRCPU *cpu = AVR_CPU(obj); 337 CPUAVRState *env = &cpu->env; 338 339 set_avr_feature(env, AVR_FEATURE_LPM); 340 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 341 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 342 set_avr_feature(env, AVR_FEATURE_SRAM); 343 set_avr_feature(env, AVR_FEATURE_BREAK); 344 345 set_avr_feature(env, AVR_FEATURE_3_BYTE_PC); 346 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 347 set_avr_feature(env, AVR_FEATURE_RAMPZ); 348 set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL); 349 set_avr_feature(env, AVR_FEATURE_ELPMX); 350 set_avr_feature(env, AVR_FEATURE_ELPM); 351 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 352 set_avr_feature(env, AVR_FEATURE_LPMX); 353 set_avr_feature(env, AVR_FEATURE_MOVW); 354 set_avr_feature(env, AVR_FEATURE_MUL); 355 } 356 357 typedef struct AVRCPUInfo { 358 const char *name; 359 void (*initfn)(Object *obj); 360 } AVRCPUInfo; 361 362 363 static void avr_cpu_list_entry(gpointer data, gpointer user_data) 364 { 365 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 366 367 qemu_printf("%s\n", typename); 368 } 369 370 void avr_cpu_list(void) 371 { 372 GSList *list; 373 list = object_class_get_list_sorted(TYPE_AVR_CPU, false); 374 g_slist_foreach(list, avr_cpu_list_entry, NULL); 375 g_slist_free(list); 376 } 377 378 #define DEFINE_AVR_CPU_TYPE(model, initfn) \ 379 { \ 380 .parent = TYPE_AVR_CPU, \ 381 .instance_init = initfn, \ 382 .name = AVR_CPU_TYPE_NAME(model), \ 383 } 384 385 static const TypeInfo avr_cpu_type_info[] = { 386 { 387 .name = TYPE_AVR_CPU, 388 .parent = TYPE_CPU, 389 .instance_size = sizeof(AVRCPU), 390 .instance_align = __alignof(AVRCPU), 391 .instance_init = avr_cpu_initfn, 392 .class_size = sizeof(AVRCPUClass), 393 .class_init = avr_cpu_class_init, 394 .abstract = true, 395 }, 396 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn), 397 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), 398 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn), 399 }; 400 401 DEFINE_TYPES(avr_cpu_type_info) 402