1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2019-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/qemu-print.h" 24 #include "exec/exec-all.h" 25 #include "cpu.h" 26 #include "disas/dis-asm.h" 27 28 static void avr_cpu_set_pc(CPUState *cs, vaddr value) 29 { 30 AVRCPU *cpu = AVR_CPU(cs); 31 32 cpu->env.pc_w = value / 2; /* internally PC points to words */ 33 } 34 35 static bool avr_cpu_has_work(CPUState *cs) 36 { 37 AVRCPU *cpu = AVR_CPU(cs); 38 CPUAVRState *env = &cpu->env; 39 40 return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) 41 && cpu_interrupts_enabled(env); 42 } 43 44 static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 45 { 46 AVRCPU *cpu = AVR_CPU(cs); 47 CPUAVRState *env = &cpu->env; 48 49 env->pc_w = tb->pc / 2; /* internally PC points to words */ 50 } 51 52 static void avr_cpu_reset(DeviceState *ds) 53 { 54 CPUState *cs = CPU(ds); 55 AVRCPU *cpu = AVR_CPU(cs); 56 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu); 57 CPUAVRState *env = &cpu->env; 58 59 mcc->parent_reset(ds); 60 61 env->pc_w = 0; 62 env->sregI = 1; 63 env->sregC = 0; 64 env->sregZ = 0; 65 env->sregN = 0; 66 env->sregV = 0; 67 env->sregS = 0; 68 env->sregH = 0; 69 env->sregT = 0; 70 71 env->rampD = 0; 72 env->rampX = 0; 73 env->rampY = 0; 74 env->rampZ = 0; 75 env->eind = 0; 76 env->sp = 0; 77 78 env->skip = 0; 79 80 memset(env->r, 0, sizeof(env->r)); 81 82 tlb_flush(cs); 83 } 84 85 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 86 { 87 info->mach = bfd_arch_avr; 88 info->print_insn = avr_print_insn; 89 } 90 91 static void avr_cpu_realizefn(DeviceState *dev, Error **errp) 92 { 93 CPUState *cs = CPU(dev); 94 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); 95 Error *local_err = NULL; 96 97 cpu_exec_realizefn(cs, &local_err); 98 if (local_err != NULL) { 99 error_propagate(errp, local_err); 100 return; 101 } 102 qemu_init_vcpu(cs); 103 cpu_reset(cs); 104 105 mcc->parent_realize(dev, errp); 106 } 107 108 static void avr_cpu_set_int(void *opaque, int irq, int level) 109 { 110 AVRCPU *cpu = opaque; 111 CPUAVRState *env = &cpu->env; 112 CPUState *cs = CPU(cpu); 113 uint64_t mask = (1ull << irq); 114 115 if (level) { 116 env->intsrc |= mask; 117 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 118 } else { 119 env->intsrc &= ~mask; 120 if (env->intsrc == 0) { 121 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 122 } 123 } 124 } 125 126 static void avr_cpu_initfn(Object *obj) 127 { 128 AVRCPU *cpu = AVR_CPU(obj); 129 130 cpu_set_cpustate_pointers(cpu); 131 132 /* Set the number of interrupts supported by the CPU. */ 133 qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 134 sizeof(cpu->env.intsrc) * 8); 135 } 136 137 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) 138 { 139 ObjectClass *oc; 140 141 oc = object_class_by_name(cpu_model); 142 if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL || 143 object_class_is_abstract(oc)) { 144 oc = NULL; 145 } 146 return oc; 147 } 148 149 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) 150 { 151 AVRCPU *cpu = AVR_CPU(cs); 152 CPUAVRState *env = &cpu->env; 153 int i; 154 155 qemu_fprintf(f, "\n"); 156 qemu_fprintf(f, "PC: %06x\n", env->pc_w); 157 qemu_fprintf(f, "SP: %04x\n", env->sp); 158 qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16); 159 qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16); 160 qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16); 161 qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16); 162 qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16); 163 qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]); 164 qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]); 165 qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]); 166 qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n", 167 env->sregI ? 'I' : '-', 168 env->sregT ? 'T' : '-', 169 env->sregH ? 'H' : '-', 170 env->sregS ? 'S' : '-', 171 env->sregV ? 'V' : '-', 172 env->sregN ? '-' : 'N', /* Zf has negative logic */ 173 env->sregZ ? 'Z' : '-', 174 env->sregC ? 'I' : '-'); 175 qemu_fprintf(f, "SKIP: %02x\n", env->skip); 176 177 qemu_fprintf(f, "\n"); 178 for (i = 0; i < ARRAY_SIZE(env->r); i++) { 179 qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]); 180 181 if ((i % 8) == 7) { 182 qemu_fprintf(f, "\n"); 183 } 184 } 185 qemu_fprintf(f, "\n"); 186 } 187 188 static void avr_cpu_class_init(ObjectClass *oc, void *data) 189 { 190 DeviceClass *dc = DEVICE_CLASS(oc); 191 CPUClass *cc = CPU_CLASS(oc); 192 AVRCPUClass *mcc = AVR_CPU_CLASS(oc); 193 194 mcc->parent_realize = dc->realize; 195 dc->realize = avr_cpu_realizefn; 196 197 device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset); 198 199 cc->class_by_name = avr_cpu_class_by_name; 200 201 cc->has_work = avr_cpu_has_work; 202 cc->do_interrupt = avr_cpu_do_interrupt; 203 cc->cpu_exec_interrupt = avr_cpu_exec_interrupt; 204 cc->dump_state = avr_cpu_dump_state; 205 cc->set_pc = avr_cpu_set_pc; 206 cc->memory_rw_debug = avr_cpu_memory_rw_debug; 207 cc->get_phys_page_debug = avr_cpu_get_phys_page_debug; 208 cc->tlb_fill = avr_cpu_tlb_fill; 209 cc->vmsd = &vms_avr_cpu; 210 cc->disas_set_info = avr_cpu_disas_set_info; 211 cc->tcg_initialize = avr_cpu_tcg_init; 212 cc->synchronize_from_tb = avr_cpu_synchronize_from_tb; 213 cc->gdb_read_register = avr_cpu_gdb_read_register; 214 cc->gdb_write_register = avr_cpu_gdb_write_register; 215 cc->gdb_num_core_regs = 35; 216 cc->gdb_core_xml_file = "avr-cpu.xml"; 217 } 218 219 /* 220 * Setting features of AVR core type avr5 221 * -------------------------------------- 222 * 223 * This type of AVR core is present in the following AVR MCUs: 224 * 225 * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c, 226 * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162, 227 * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, 228 * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, 229 * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb, 230 * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323, 231 * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, 232 * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, 233 * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa, 234 * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1, 235 * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644, 236 * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, 237 * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, 238 * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p, 239 * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2, 240 * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216, 241 * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000 242 */ 243 static void avr_avr5_initfn(Object *obj) 244 { 245 AVRCPU *cpu = AVR_CPU(obj); 246 CPUAVRState *env = &cpu->env; 247 248 set_avr_feature(env, AVR_FEATURE_LPM); 249 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 250 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 251 set_avr_feature(env, AVR_FEATURE_SRAM); 252 set_avr_feature(env, AVR_FEATURE_BREAK); 253 254 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 255 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 256 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 257 set_avr_feature(env, AVR_FEATURE_LPMX); 258 set_avr_feature(env, AVR_FEATURE_MOVW); 259 set_avr_feature(env, AVR_FEATURE_MUL); 260 } 261 262 /* 263 * Setting features of AVR core type avr51 264 * -------------------------------------- 265 * 266 * This type of AVR core is present in the following AVR MCUs: 267 * 268 * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p, 269 * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 270 * at90usb1287 271 */ 272 static void avr_avr51_initfn(Object *obj) 273 { 274 AVRCPU *cpu = AVR_CPU(obj); 275 CPUAVRState *env = &cpu->env; 276 277 set_avr_feature(env, AVR_FEATURE_LPM); 278 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 279 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 280 set_avr_feature(env, AVR_FEATURE_SRAM); 281 set_avr_feature(env, AVR_FEATURE_BREAK); 282 283 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 284 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 285 set_avr_feature(env, AVR_FEATURE_RAMPZ); 286 set_avr_feature(env, AVR_FEATURE_ELPMX); 287 set_avr_feature(env, AVR_FEATURE_ELPM); 288 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 289 set_avr_feature(env, AVR_FEATURE_LPMX); 290 set_avr_feature(env, AVR_FEATURE_MOVW); 291 set_avr_feature(env, AVR_FEATURE_MUL); 292 } 293 294 /* 295 * Setting features of AVR core type avr6 296 * -------------------------------------- 297 * 298 * This type of AVR core is present in the following AVR MCUs: 299 * 300 * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2 301 */ 302 static void avr_avr6_initfn(Object *obj) 303 { 304 AVRCPU *cpu = AVR_CPU(obj); 305 CPUAVRState *env = &cpu->env; 306 307 set_avr_feature(env, AVR_FEATURE_LPM); 308 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 309 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 310 set_avr_feature(env, AVR_FEATURE_SRAM); 311 set_avr_feature(env, AVR_FEATURE_BREAK); 312 313 set_avr_feature(env, AVR_FEATURE_3_BYTE_PC); 314 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 315 set_avr_feature(env, AVR_FEATURE_RAMPZ); 316 set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL); 317 set_avr_feature(env, AVR_FEATURE_ELPMX); 318 set_avr_feature(env, AVR_FEATURE_ELPM); 319 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 320 set_avr_feature(env, AVR_FEATURE_LPMX); 321 set_avr_feature(env, AVR_FEATURE_MOVW); 322 set_avr_feature(env, AVR_FEATURE_MUL); 323 } 324 325 typedef struct AVRCPUInfo { 326 const char *name; 327 void (*initfn)(Object *obj); 328 } AVRCPUInfo; 329 330 331 static void avr_cpu_list_entry(gpointer data, gpointer user_data) 332 { 333 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 334 335 qemu_printf("%s\n", typename); 336 } 337 338 void avr_cpu_list(void) 339 { 340 GSList *list; 341 list = object_class_get_list_sorted(TYPE_AVR_CPU, false); 342 g_slist_foreach(list, avr_cpu_list_entry, NULL); 343 g_slist_free(list); 344 } 345 346 #define DEFINE_AVR_CPU_TYPE(model, initfn) \ 347 { \ 348 .parent = TYPE_AVR_CPU, \ 349 .instance_init = initfn, \ 350 .name = AVR_CPU_TYPE_NAME(model), \ 351 } 352 353 static const TypeInfo avr_cpu_type_info[] = { 354 { 355 .name = TYPE_AVR_CPU, 356 .parent = TYPE_CPU, 357 .instance_size = sizeof(AVRCPU), 358 .instance_init = avr_cpu_initfn, 359 .class_size = sizeof(AVRCPUClass), 360 .class_init = avr_cpu_class_init, 361 .abstract = true, 362 }, 363 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn), 364 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), 365 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn), 366 }; 367 368 DEFINE_TYPES(avr_cpu_type_info) 369