1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2019-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/qemu-print.h" 24 #include "exec/translation-block.h" 25 #include "system/address-spaces.h" 26 #include "cpu.h" 27 #include "disas/dis-asm.h" 28 #include "tcg/debug-assert.h" 29 #include "hw/qdev-properties.h" 30 31 static void avr_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 AVRCPU *cpu = AVR_CPU(cs); 34 35 cpu->env.pc_w = value / 2; /* internally PC points to words */ 36 } 37 38 static vaddr avr_cpu_get_pc(CPUState *cs) 39 { 40 AVRCPU *cpu = AVR_CPU(cs); 41 42 return cpu->env.pc_w * 2; 43 } 44 45 static bool avr_cpu_has_work(CPUState *cs) 46 { 47 return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) 48 && cpu_interrupts_enabled(cpu_env(cs)); 49 } 50 51 static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) 52 { 53 return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; 54 } 55 56 static void avr_cpu_synchronize_from_tb(CPUState *cs, 57 const TranslationBlock *tb) 58 { 59 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 60 cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */ 61 } 62 63 static void avr_restore_state_to_opc(CPUState *cs, 64 const TranslationBlock *tb, 65 const uint64_t *data) 66 { 67 cpu_env(cs)->pc_w = data[0]; 68 } 69 70 static void avr_cpu_reset_hold(Object *obj, ResetType type) 71 { 72 CPUState *cs = CPU(obj); 73 AVRCPU *cpu = AVR_CPU(cs); 74 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(obj); 75 CPUAVRState *env = &cpu->env; 76 77 if (mcc->parent_phases.hold) { 78 mcc->parent_phases.hold(obj, type); 79 } 80 81 env->pc_w = 0; 82 env->sregI = 1; 83 env->sregC = 0; 84 env->sregZ = 0; 85 env->sregN = 0; 86 env->sregV = 0; 87 env->sregS = 0; 88 env->sregH = 0; 89 env->sregT = 0; 90 91 env->rampD = 0; 92 env->rampX = 0; 93 env->rampY = 0; 94 env->rampZ = 0; 95 env->eind = 0; 96 env->sp = cpu->init_sp; 97 98 env->skip = 0; 99 100 memset(env->r, 0, sizeof(env->r)); 101 } 102 103 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 104 { 105 info->endian = BFD_ENDIAN_LITTLE; 106 info->mach = bfd_arch_avr; 107 info->print_insn = avr_print_insn; 108 } 109 110 static void avr_cpu_realizefn(DeviceState *dev, Error **errp) 111 { 112 CPUState *cs = CPU(dev); 113 CPUAVRState *env = cpu_env(cs); 114 AVRCPU *cpu = env_archcpu(env); 115 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); 116 Error *local_err = NULL; 117 118 cpu_exec_realizefn(cs, &local_err); 119 if (local_err != NULL) { 120 error_propagate(errp, local_err); 121 return; 122 } 123 qemu_init_vcpu(cs); 124 cpu_reset(cs); 125 126 mcc->parent_realize(dev, errp); 127 128 /* 129 * Two blocks in the low data space loop back into cpu registers. 130 */ 131 memory_region_init_io(&cpu->cpu_reg1, OBJECT(cpu), &avr_cpu_reg1, env, 132 "avr-cpu-reg1", 32); 133 memory_region_add_subregion(get_system_memory(), 134 OFFSET_DATA, &cpu->cpu_reg1); 135 136 memory_region_init_io(&cpu->cpu_reg2, OBJECT(cpu), &avr_cpu_reg2, env, 137 "avr-cpu-reg2", 8); 138 memory_region_add_subregion(get_system_memory(), 139 OFFSET_DATA + 0x58, &cpu->cpu_reg2); 140 } 141 142 static void avr_cpu_set_int(void *opaque, int irq, int level) 143 { 144 AVRCPU *cpu = opaque; 145 CPUAVRState *env = &cpu->env; 146 CPUState *cs = CPU(cpu); 147 uint64_t mask = (1ull << irq); 148 149 if (level) { 150 env->intsrc |= mask; 151 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 152 } else { 153 env->intsrc &= ~mask; 154 if (env->intsrc == 0) { 155 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 156 } 157 } 158 } 159 160 static void avr_cpu_initfn(Object *obj) 161 { 162 AVRCPU *cpu = AVR_CPU(obj); 163 164 /* Set the number of interrupts supported by the CPU. */ 165 qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 166 sizeof(cpu->env.intsrc) * 8); 167 } 168 169 static const Property avr_cpu_properties[] = { 170 DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0), 171 }; 172 173 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) 174 { 175 return object_class_by_name(cpu_model); 176 } 177 178 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) 179 { 180 CPUAVRState *env = cpu_env(cs); 181 int i; 182 183 qemu_fprintf(f, "\n"); 184 qemu_fprintf(f, "PC: %06x\n", env->pc_w * 2); /* PC points to words */ 185 qemu_fprintf(f, "SP: %04x\n", env->sp); 186 qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16); 187 qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16); 188 qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16); 189 qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16); 190 qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16); 191 qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]); 192 qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]); 193 qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]); 194 qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n", 195 env->sregI ? 'I' : '-', 196 env->sregT ? 'T' : '-', 197 env->sregH ? 'H' : '-', 198 env->sregS ? 'S' : '-', 199 env->sregV ? 'V' : '-', 200 env->sregN ? '-' : 'N', /* Zf has negative logic */ 201 env->sregZ ? 'Z' : '-', 202 env->sregC ? 'I' : '-'); 203 qemu_fprintf(f, "SKIP: %02x\n", env->skip); 204 205 qemu_fprintf(f, "\n"); 206 for (i = 0; i < ARRAY_SIZE(env->r); i++) { 207 qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]); 208 209 if ((i % 8) == 7) { 210 qemu_fprintf(f, "\n"); 211 } 212 } 213 qemu_fprintf(f, "\n"); 214 } 215 216 #include "hw/core/sysemu-cpu-ops.h" 217 218 static const struct SysemuCPUOps avr_sysemu_ops = { 219 .has_work = avr_cpu_has_work, 220 .get_phys_page_debug = avr_cpu_get_phys_page_debug, 221 }; 222 223 #include "accel/tcg/cpu-ops.h" 224 225 static const TCGCPUOps avr_tcg_ops = { 226 .guest_default_memory_order = 0, 227 .mttcg_supported = false, 228 .initialize = avr_cpu_tcg_init, 229 .translate_code = avr_cpu_translate_code, 230 .synchronize_from_tb = avr_cpu_synchronize_from_tb, 231 .restore_state_to_opc = avr_restore_state_to_opc, 232 .mmu_index = avr_cpu_mmu_index, 233 .cpu_exec_interrupt = avr_cpu_exec_interrupt, 234 .cpu_exec_halt = avr_cpu_has_work, 235 .tlb_fill = avr_cpu_tlb_fill, 236 .do_interrupt = avr_cpu_do_interrupt, 237 }; 238 239 static void avr_cpu_class_init(ObjectClass *oc, const void *data) 240 { 241 DeviceClass *dc = DEVICE_CLASS(oc); 242 CPUClass *cc = CPU_CLASS(oc); 243 AVRCPUClass *mcc = AVR_CPU_CLASS(oc); 244 ResettableClass *rc = RESETTABLE_CLASS(oc); 245 246 device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize); 247 248 device_class_set_props(dc, avr_cpu_properties); 249 250 resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL, 251 &mcc->parent_phases); 252 253 cc->class_by_name = avr_cpu_class_by_name; 254 255 cc->dump_state = avr_cpu_dump_state; 256 cc->set_pc = avr_cpu_set_pc; 257 cc->get_pc = avr_cpu_get_pc; 258 dc->vmsd = &vms_avr_cpu; 259 cc->sysemu_ops = &avr_sysemu_ops; 260 cc->disas_set_info = avr_cpu_disas_set_info; 261 cc->gdb_read_register = avr_cpu_gdb_read_register; 262 cc->gdb_write_register = avr_cpu_gdb_write_register; 263 cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint; 264 cc->gdb_core_xml_file = "avr-cpu.xml"; 265 cc->tcg_ops = &avr_tcg_ops; 266 } 267 268 /* 269 * Setting features of AVR core type avr5 270 * -------------------------------------- 271 * 272 * This type of AVR core is present in the following AVR MCUs: 273 * 274 * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c, 275 * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162, 276 * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, 277 * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, 278 * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb, 279 * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323, 280 * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, 281 * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, 282 * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa, 283 * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1, 284 * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644, 285 * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, 286 * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, 287 * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p, 288 * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2, 289 * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216, 290 * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000 291 */ 292 static void avr_avr5_initfn(Object *obj) 293 { 294 CPUAVRState *env = cpu_env(CPU(obj)); 295 296 set_avr_feature(env, AVR_FEATURE_LPM); 297 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 298 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 299 set_avr_feature(env, AVR_FEATURE_SRAM); 300 set_avr_feature(env, AVR_FEATURE_BREAK); 301 302 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 303 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 304 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 305 set_avr_feature(env, AVR_FEATURE_LPMX); 306 set_avr_feature(env, AVR_FEATURE_MOVW); 307 set_avr_feature(env, AVR_FEATURE_MUL); 308 } 309 310 /* 311 * Setting features of AVR core type avr51 312 * -------------------------------------- 313 * 314 * This type of AVR core is present in the following AVR MCUs: 315 * 316 * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p, 317 * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 318 * at90usb1287 319 */ 320 static void avr_avr51_initfn(Object *obj) 321 { 322 CPUAVRState *env = cpu_env(CPU(obj)); 323 324 set_avr_feature(env, AVR_FEATURE_LPM); 325 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 326 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 327 set_avr_feature(env, AVR_FEATURE_SRAM); 328 set_avr_feature(env, AVR_FEATURE_BREAK); 329 330 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 331 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 332 set_avr_feature(env, AVR_FEATURE_RAMPZ); 333 set_avr_feature(env, AVR_FEATURE_ELPMX); 334 set_avr_feature(env, AVR_FEATURE_ELPM); 335 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 336 set_avr_feature(env, AVR_FEATURE_LPMX); 337 set_avr_feature(env, AVR_FEATURE_MOVW); 338 set_avr_feature(env, AVR_FEATURE_MUL); 339 } 340 341 /* 342 * Setting features of AVR core type avr6 343 * -------------------------------------- 344 * 345 * This type of AVR core is present in the following AVR MCUs: 346 * 347 * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2 348 */ 349 static void avr_avr6_initfn(Object *obj) 350 { 351 CPUAVRState *env = cpu_env(CPU(obj)); 352 353 set_avr_feature(env, AVR_FEATURE_LPM); 354 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 355 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 356 set_avr_feature(env, AVR_FEATURE_SRAM); 357 set_avr_feature(env, AVR_FEATURE_BREAK); 358 359 set_avr_feature(env, AVR_FEATURE_3_BYTE_PC); 360 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 361 set_avr_feature(env, AVR_FEATURE_RAMPZ); 362 set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL); 363 set_avr_feature(env, AVR_FEATURE_ELPMX); 364 set_avr_feature(env, AVR_FEATURE_ELPM); 365 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 366 set_avr_feature(env, AVR_FEATURE_LPMX); 367 set_avr_feature(env, AVR_FEATURE_MOVW); 368 set_avr_feature(env, AVR_FEATURE_MUL); 369 } 370 371 typedef struct AVRCPUInfo { 372 const char *name; 373 void (*initfn)(Object *obj); 374 } AVRCPUInfo; 375 376 377 #define DEFINE_AVR_CPU_TYPE(model, initfn) \ 378 { \ 379 .parent = TYPE_AVR_CPU, \ 380 .instance_init = initfn, \ 381 .name = AVR_CPU_TYPE_NAME(model), \ 382 } 383 384 static const TypeInfo avr_cpu_type_info[] = { 385 { 386 .name = TYPE_AVR_CPU, 387 .parent = TYPE_CPU, 388 .instance_size = sizeof(AVRCPU), 389 .instance_align = __alignof(AVRCPU), 390 .instance_init = avr_cpu_initfn, 391 .class_size = sizeof(AVRCPUClass), 392 .class_init = avr_cpu_class_init, 393 .abstract = true, 394 }, 395 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn), 396 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), 397 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn), 398 }; 399 400 DEFINE_TYPES(avr_cpu_type_info) 401