1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2019-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/qemu-print.h" 24 #include "exec/exec-all.h" 25 #include "cpu.h" 26 #include "disas/dis-asm.h" 27 28 static void avr_cpu_set_pc(CPUState *cs, vaddr value) 29 { 30 AVRCPU *cpu = AVR_CPU(cs); 31 32 cpu->env.pc_w = value / 2; /* internally PC points to words */ 33 } 34 35 static vaddr avr_cpu_get_pc(CPUState *cs) 36 { 37 AVRCPU *cpu = AVR_CPU(cs); 38 39 return cpu->env.pc_w * 2; 40 } 41 42 static bool avr_cpu_has_work(CPUState *cs) 43 { 44 AVRCPU *cpu = AVR_CPU(cs); 45 CPUAVRState *env = &cpu->env; 46 47 return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) 48 && cpu_interrupts_enabled(env); 49 } 50 51 static void avr_cpu_synchronize_from_tb(CPUState *cs, 52 const TranslationBlock *tb) 53 { 54 AVRCPU *cpu = AVR_CPU(cs); 55 CPUAVRState *env = &cpu->env; 56 57 env->pc_w = tb_pc(tb) / 2; /* internally PC points to words */ 58 } 59 60 static void avr_cpu_reset(DeviceState *ds) 61 { 62 CPUState *cs = CPU(ds); 63 AVRCPU *cpu = AVR_CPU(cs); 64 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu); 65 CPUAVRState *env = &cpu->env; 66 67 mcc->parent_reset(ds); 68 69 env->pc_w = 0; 70 env->sregI = 1; 71 env->sregC = 0; 72 env->sregZ = 0; 73 env->sregN = 0; 74 env->sregV = 0; 75 env->sregS = 0; 76 env->sregH = 0; 77 env->sregT = 0; 78 79 env->rampD = 0; 80 env->rampX = 0; 81 env->rampY = 0; 82 env->rampZ = 0; 83 env->eind = 0; 84 env->sp = 0; 85 86 env->skip = 0; 87 88 memset(env->r, 0, sizeof(env->r)); 89 } 90 91 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 92 { 93 info->mach = bfd_arch_avr; 94 info->print_insn = avr_print_insn; 95 } 96 97 static void avr_cpu_realizefn(DeviceState *dev, Error **errp) 98 { 99 CPUState *cs = CPU(dev); 100 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); 101 Error *local_err = NULL; 102 103 cpu_exec_realizefn(cs, &local_err); 104 if (local_err != NULL) { 105 error_propagate(errp, local_err); 106 return; 107 } 108 qemu_init_vcpu(cs); 109 cpu_reset(cs); 110 111 mcc->parent_realize(dev, errp); 112 } 113 114 static void avr_cpu_set_int(void *opaque, int irq, int level) 115 { 116 AVRCPU *cpu = opaque; 117 CPUAVRState *env = &cpu->env; 118 CPUState *cs = CPU(cpu); 119 uint64_t mask = (1ull << irq); 120 121 if (level) { 122 env->intsrc |= mask; 123 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 124 } else { 125 env->intsrc &= ~mask; 126 if (env->intsrc == 0) { 127 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 128 } 129 } 130 } 131 132 static void avr_cpu_initfn(Object *obj) 133 { 134 AVRCPU *cpu = AVR_CPU(obj); 135 136 cpu_set_cpustate_pointers(cpu); 137 138 /* Set the number of interrupts supported by the CPU. */ 139 qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 140 sizeof(cpu->env.intsrc) * 8); 141 } 142 143 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) 144 { 145 ObjectClass *oc; 146 147 oc = object_class_by_name(cpu_model); 148 if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL || 149 object_class_is_abstract(oc)) { 150 oc = NULL; 151 } 152 return oc; 153 } 154 155 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) 156 { 157 AVRCPU *cpu = AVR_CPU(cs); 158 CPUAVRState *env = &cpu->env; 159 int i; 160 161 qemu_fprintf(f, "\n"); 162 qemu_fprintf(f, "PC: %06x\n", env->pc_w * 2); /* PC points to words */ 163 qemu_fprintf(f, "SP: %04x\n", env->sp); 164 qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16); 165 qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16); 166 qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16); 167 qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16); 168 qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16); 169 qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]); 170 qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]); 171 qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]); 172 qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n", 173 env->sregI ? 'I' : '-', 174 env->sregT ? 'T' : '-', 175 env->sregH ? 'H' : '-', 176 env->sregS ? 'S' : '-', 177 env->sregV ? 'V' : '-', 178 env->sregN ? '-' : 'N', /* Zf has negative logic */ 179 env->sregZ ? 'Z' : '-', 180 env->sregC ? 'I' : '-'); 181 qemu_fprintf(f, "SKIP: %02x\n", env->skip); 182 183 qemu_fprintf(f, "\n"); 184 for (i = 0; i < ARRAY_SIZE(env->r); i++) { 185 qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]); 186 187 if ((i % 8) == 7) { 188 qemu_fprintf(f, "\n"); 189 } 190 } 191 qemu_fprintf(f, "\n"); 192 } 193 194 #include "hw/core/sysemu-cpu-ops.h" 195 196 static const struct SysemuCPUOps avr_sysemu_ops = { 197 .get_phys_page_debug = avr_cpu_get_phys_page_debug, 198 }; 199 200 #include "hw/core/tcg-cpu-ops.h" 201 202 static const struct TCGCPUOps avr_tcg_ops = { 203 .initialize = avr_cpu_tcg_init, 204 .synchronize_from_tb = avr_cpu_synchronize_from_tb, 205 .cpu_exec_interrupt = avr_cpu_exec_interrupt, 206 .tlb_fill = avr_cpu_tlb_fill, 207 .do_interrupt = avr_cpu_do_interrupt, 208 }; 209 210 static void avr_cpu_class_init(ObjectClass *oc, void *data) 211 { 212 DeviceClass *dc = DEVICE_CLASS(oc); 213 CPUClass *cc = CPU_CLASS(oc); 214 AVRCPUClass *mcc = AVR_CPU_CLASS(oc); 215 216 device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize); 217 device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset); 218 219 cc->class_by_name = avr_cpu_class_by_name; 220 221 cc->has_work = avr_cpu_has_work; 222 cc->dump_state = avr_cpu_dump_state; 223 cc->set_pc = avr_cpu_set_pc; 224 cc->get_pc = avr_cpu_get_pc; 225 dc->vmsd = &vms_avr_cpu; 226 cc->sysemu_ops = &avr_sysemu_ops; 227 cc->disas_set_info = avr_cpu_disas_set_info; 228 cc->gdb_read_register = avr_cpu_gdb_read_register; 229 cc->gdb_write_register = avr_cpu_gdb_write_register; 230 cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint; 231 cc->gdb_num_core_regs = 35; 232 cc->gdb_core_xml_file = "avr-cpu.xml"; 233 cc->tcg_ops = &avr_tcg_ops; 234 } 235 236 /* 237 * Setting features of AVR core type avr5 238 * -------------------------------------- 239 * 240 * This type of AVR core is present in the following AVR MCUs: 241 * 242 * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c, 243 * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162, 244 * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, 245 * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, 246 * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb, 247 * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323, 248 * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, 249 * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, 250 * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa, 251 * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1, 252 * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644, 253 * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, 254 * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, 255 * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p, 256 * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2, 257 * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216, 258 * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000 259 */ 260 static void avr_avr5_initfn(Object *obj) 261 { 262 AVRCPU *cpu = AVR_CPU(obj); 263 CPUAVRState *env = &cpu->env; 264 265 set_avr_feature(env, AVR_FEATURE_LPM); 266 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 267 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 268 set_avr_feature(env, AVR_FEATURE_SRAM); 269 set_avr_feature(env, AVR_FEATURE_BREAK); 270 271 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 272 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 273 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 274 set_avr_feature(env, AVR_FEATURE_LPMX); 275 set_avr_feature(env, AVR_FEATURE_MOVW); 276 set_avr_feature(env, AVR_FEATURE_MUL); 277 } 278 279 /* 280 * Setting features of AVR core type avr51 281 * -------------------------------------- 282 * 283 * This type of AVR core is present in the following AVR MCUs: 284 * 285 * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p, 286 * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 287 * at90usb1287 288 */ 289 static void avr_avr51_initfn(Object *obj) 290 { 291 AVRCPU *cpu = AVR_CPU(obj); 292 CPUAVRState *env = &cpu->env; 293 294 set_avr_feature(env, AVR_FEATURE_LPM); 295 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 296 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 297 set_avr_feature(env, AVR_FEATURE_SRAM); 298 set_avr_feature(env, AVR_FEATURE_BREAK); 299 300 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 301 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 302 set_avr_feature(env, AVR_FEATURE_RAMPZ); 303 set_avr_feature(env, AVR_FEATURE_ELPMX); 304 set_avr_feature(env, AVR_FEATURE_ELPM); 305 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 306 set_avr_feature(env, AVR_FEATURE_LPMX); 307 set_avr_feature(env, AVR_FEATURE_MOVW); 308 set_avr_feature(env, AVR_FEATURE_MUL); 309 } 310 311 /* 312 * Setting features of AVR core type avr6 313 * -------------------------------------- 314 * 315 * This type of AVR core is present in the following AVR MCUs: 316 * 317 * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2 318 */ 319 static void avr_avr6_initfn(Object *obj) 320 { 321 AVRCPU *cpu = AVR_CPU(obj); 322 CPUAVRState *env = &cpu->env; 323 324 set_avr_feature(env, AVR_FEATURE_LPM); 325 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 326 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 327 set_avr_feature(env, AVR_FEATURE_SRAM); 328 set_avr_feature(env, AVR_FEATURE_BREAK); 329 330 set_avr_feature(env, AVR_FEATURE_3_BYTE_PC); 331 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 332 set_avr_feature(env, AVR_FEATURE_RAMPZ); 333 set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL); 334 set_avr_feature(env, AVR_FEATURE_ELPMX); 335 set_avr_feature(env, AVR_FEATURE_ELPM); 336 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 337 set_avr_feature(env, AVR_FEATURE_LPMX); 338 set_avr_feature(env, AVR_FEATURE_MOVW); 339 set_avr_feature(env, AVR_FEATURE_MUL); 340 } 341 342 typedef struct AVRCPUInfo { 343 const char *name; 344 void (*initfn)(Object *obj); 345 } AVRCPUInfo; 346 347 348 static void avr_cpu_list_entry(gpointer data, gpointer user_data) 349 { 350 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 351 352 qemu_printf("%s\n", typename); 353 } 354 355 void avr_cpu_list(void) 356 { 357 GSList *list; 358 list = object_class_get_list_sorted(TYPE_AVR_CPU, false); 359 g_slist_foreach(list, avr_cpu_list_entry, NULL); 360 g_slist_free(list); 361 } 362 363 #define DEFINE_AVR_CPU_TYPE(model, initfn) \ 364 { \ 365 .parent = TYPE_AVR_CPU, \ 366 .instance_init = initfn, \ 367 .name = AVR_CPU_TYPE_NAME(model), \ 368 } 369 370 static const TypeInfo avr_cpu_type_info[] = { 371 { 372 .name = TYPE_AVR_CPU, 373 .parent = TYPE_CPU, 374 .instance_size = sizeof(AVRCPU), 375 .instance_init = avr_cpu_initfn, 376 .class_size = sizeof(AVRCPUClass), 377 .class_init = avr_cpu_class_init, 378 .abstract = true, 379 }, 380 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn), 381 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), 382 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn), 383 }; 384 385 DEFINE_TYPES(avr_cpu_type_info) 386