1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2019-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/qemu-print.h" 24 #include "exec/exec-all.h" 25 #include "cpu.h" 26 #include "disas/dis-asm.h" 27 28 static void avr_cpu_set_pc(CPUState *cs, vaddr value) 29 { 30 AVRCPU *cpu = AVR_CPU(cs); 31 32 cpu->env.pc_w = value / 2; /* internally PC points to words */ 33 } 34 35 static bool avr_cpu_has_work(CPUState *cs) 36 { 37 AVRCPU *cpu = AVR_CPU(cs); 38 CPUAVRState *env = &cpu->env; 39 40 return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) 41 && cpu_interrupts_enabled(env); 42 } 43 44 static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 45 { 46 AVRCPU *cpu = AVR_CPU(cs); 47 CPUAVRState *env = &cpu->env; 48 49 env->pc_w = tb->pc / 2; /* internally PC points to words */ 50 } 51 52 static void avr_cpu_reset(DeviceState *ds) 53 { 54 CPUState *cs = CPU(ds); 55 AVRCPU *cpu = AVR_CPU(cs); 56 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu); 57 CPUAVRState *env = &cpu->env; 58 59 mcc->parent_reset(ds); 60 61 env->pc_w = 0; 62 env->sregI = 1; 63 env->sregC = 0; 64 env->sregZ = 0; 65 env->sregN = 0; 66 env->sregV = 0; 67 env->sregS = 0; 68 env->sregH = 0; 69 env->sregT = 0; 70 71 env->rampD = 0; 72 env->rampX = 0; 73 env->rampY = 0; 74 env->rampZ = 0; 75 env->eind = 0; 76 env->sp = 0; 77 78 env->skip = 0; 79 80 memset(env->r, 0, sizeof(env->r)); 81 } 82 83 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 84 { 85 info->mach = bfd_arch_avr; 86 info->print_insn = avr_print_insn; 87 } 88 89 static void avr_cpu_realizefn(DeviceState *dev, Error **errp) 90 { 91 CPUState *cs = CPU(dev); 92 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); 93 Error *local_err = NULL; 94 95 cpu_exec_realizefn(cs, &local_err); 96 if (local_err != NULL) { 97 error_propagate(errp, local_err); 98 return; 99 } 100 qemu_init_vcpu(cs); 101 cpu_reset(cs); 102 103 mcc->parent_realize(dev, errp); 104 } 105 106 static void avr_cpu_set_int(void *opaque, int irq, int level) 107 { 108 AVRCPU *cpu = opaque; 109 CPUAVRState *env = &cpu->env; 110 CPUState *cs = CPU(cpu); 111 uint64_t mask = (1ull << irq); 112 113 if (level) { 114 env->intsrc |= mask; 115 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 116 } else { 117 env->intsrc &= ~mask; 118 if (env->intsrc == 0) { 119 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 120 } 121 } 122 } 123 124 static void avr_cpu_initfn(Object *obj) 125 { 126 AVRCPU *cpu = AVR_CPU(obj); 127 128 cpu_set_cpustate_pointers(cpu); 129 130 /* Set the number of interrupts supported by the CPU. */ 131 qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 132 sizeof(cpu->env.intsrc) * 8); 133 } 134 135 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) 136 { 137 ObjectClass *oc; 138 139 oc = object_class_by_name(cpu_model); 140 if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL || 141 object_class_is_abstract(oc)) { 142 oc = NULL; 143 } 144 return oc; 145 } 146 147 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) 148 { 149 AVRCPU *cpu = AVR_CPU(cs); 150 CPUAVRState *env = &cpu->env; 151 int i; 152 153 qemu_fprintf(f, "\n"); 154 qemu_fprintf(f, "PC: %06x\n", env->pc_w * 2); /* PC points to words */ 155 qemu_fprintf(f, "SP: %04x\n", env->sp); 156 qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16); 157 qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16); 158 qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16); 159 qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16); 160 qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16); 161 qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]); 162 qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]); 163 qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]); 164 qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n", 165 env->sregI ? 'I' : '-', 166 env->sregT ? 'T' : '-', 167 env->sregH ? 'H' : '-', 168 env->sregS ? 'S' : '-', 169 env->sregV ? 'V' : '-', 170 env->sregN ? '-' : 'N', /* Zf has negative logic */ 171 env->sregZ ? 'Z' : '-', 172 env->sregC ? 'I' : '-'); 173 qemu_fprintf(f, "SKIP: %02x\n", env->skip); 174 175 qemu_fprintf(f, "\n"); 176 for (i = 0; i < ARRAY_SIZE(env->r); i++) { 177 qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]); 178 179 if ((i % 8) == 7) { 180 qemu_fprintf(f, "\n"); 181 } 182 } 183 qemu_fprintf(f, "\n"); 184 } 185 186 static void avr_cpu_class_init(ObjectClass *oc, void *data) 187 { 188 DeviceClass *dc = DEVICE_CLASS(oc); 189 CPUClass *cc = CPU_CLASS(oc); 190 AVRCPUClass *mcc = AVR_CPU_CLASS(oc); 191 192 mcc->parent_realize = dc->realize; 193 dc->realize = avr_cpu_realizefn; 194 195 device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset); 196 197 cc->class_by_name = avr_cpu_class_by_name; 198 199 cc->has_work = avr_cpu_has_work; 200 cc->do_interrupt = avr_cpu_do_interrupt; 201 cc->cpu_exec_interrupt = avr_cpu_exec_interrupt; 202 cc->dump_state = avr_cpu_dump_state; 203 cc->set_pc = avr_cpu_set_pc; 204 cc->memory_rw_debug = avr_cpu_memory_rw_debug; 205 cc->get_phys_page_debug = avr_cpu_get_phys_page_debug; 206 cc->tlb_fill = avr_cpu_tlb_fill; 207 cc->vmsd = &vms_avr_cpu; 208 cc->disas_set_info = avr_cpu_disas_set_info; 209 cc->tcg_initialize = avr_cpu_tcg_init; 210 cc->synchronize_from_tb = avr_cpu_synchronize_from_tb; 211 cc->gdb_read_register = avr_cpu_gdb_read_register; 212 cc->gdb_write_register = avr_cpu_gdb_write_register; 213 cc->gdb_num_core_regs = 35; 214 cc->gdb_core_xml_file = "avr-cpu.xml"; 215 } 216 217 /* 218 * Setting features of AVR core type avr5 219 * -------------------------------------- 220 * 221 * This type of AVR core is present in the following AVR MCUs: 222 * 223 * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c, 224 * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162, 225 * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, 226 * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, 227 * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb, 228 * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323, 229 * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, 230 * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, 231 * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa, 232 * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1, 233 * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644, 234 * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, 235 * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, 236 * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p, 237 * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2, 238 * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216, 239 * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000 240 */ 241 static void avr_avr5_initfn(Object *obj) 242 { 243 AVRCPU *cpu = AVR_CPU(obj); 244 CPUAVRState *env = &cpu->env; 245 246 set_avr_feature(env, AVR_FEATURE_LPM); 247 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 248 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 249 set_avr_feature(env, AVR_FEATURE_SRAM); 250 set_avr_feature(env, AVR_FEATURE_BREAK); 251 252 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 253 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 254 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 255 set_avr_feature(env, AVR_FEATURE_LPMX); 256 set_avr_feature(env, AVR_FEATURE_MOVW); 257 set_avr_feature(env, AVR_FEATURE_MUL); 258 } 259 260 /* 261 * Setting features of AVR core type avr51 262 * -------------------------------------- 263 * 264 * This type of AVR core is present in the following AVR MCUs: 265 * 266 * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p, 267 * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 268 * at90usb1287 269 */ 270 static void avr_avr51_initfn(Object *obj) 271 { 272 AVRCPU *cpu = AVR_CPU(obj); 273 CPUAVRState *env = &cpu->env; 274 275 set_avr_feature(env, AVR_FEATURE_LPM); 276 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 277 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 278 set_avr_feature(env, AVR_FEATURE_SRAM); 279 set_avr_feature(env, AVR_FEATURE_BREAK); 280 281 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 282 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 283 set_avr_feature(env, AVR_FEATURE_RAMPZ); 284 set_avr_feature(env, AVR_FEATURE_ELPMX); 285 set_avr_feature(env, AVR_FEATURE_ELPM); 286 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 287 set_avr_feature(env, AVR_FEATURE_LPMX); 288 set_avr_feature(env, AVR_FEATURE_MOVW); 289 set_avr_feature(env, AVR_FEATURE_MUL); 290 } 291 292 /* 293 * Setting features of AVR core type avr6 294 * -------------------------------------- 295 * 296 * This type of AVR core is present in the following AVR MCUs: 297 * 298 * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2 299 */ 300 static void avr_avr6_initfn(Object *obj) 301 { 302 AVRCPU *cpu = AVR_CPU(obj); 303 CPUAVRState *env = &cpu->env; 304 305 set_avr_feature(env, AVR_FEATURE_LPM); 306 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 307 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 308 set_avr_feature(env, AVR_FEATURE_SRAM); 309 set_avr_feature(env, AVR_FEATURE_BREAK); 310 311 set_avr_feature(env, AVR_FEATURE_3_BYTE_PC); 312 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 313 set_avr_feature(env, AVR_FEATURE_RAMPZ); 314 set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL); 315 set_avr_feature(env, AVR_FEATURE_ELPMX); 316 set_avr_feature(env, AVR_FEATURE_ELPM); 317 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 318 set_avr_feature(env, AVR_FEATURE_LPMX); 319 set_avr_feature(env, AVR_FEATURE_MOVW); 320 set_avr_feature(env, AVR_FEATURE_MUL); 321 } 322 323 typedef struct AVRCPUInfo { 324 const char *name; 325 void (*initfn)(Object *obj); 326 } AVRCPUInfo; 327 328 329 static void avr_cpu_list_entry(gpointer data, gpointer user_data) 330 { 331 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 332 333 qemu_printf("%s\n", typename); 334 } 335 336 void avr_cpu_list(void) 337 { 338 GSList *list; 339 list = object_class_get_list_sorted(TYPE_AVR_CPU, false); 340 g_slist_foreach(list, avr_cpu_list_entry, NULL); 341 g_slist_free(list); 342 } 343 344 #define DEFINE_AVR_CPU_TYPE(model, initfn) \ 345 { \ 346 .parent = TYPE_AVR_CPU, \ 347 .instance_init = initfn, \ 348 .name = AVR_CPU_TYPE_NAME(model), \ 349 } 350 351 static const TypeInfo avr_cpu_type_info[] = { 352 { 353 .name = TYPE_AVR_CPU, 354 .parent = TYPE_CPU, 355 .instance_size = sizeof(AVRCPU), 356 .instance_init = avr_cpu_initfn, 357 .class_size = sizeof(AVRCPUClass), 358 .class_init = avr_cpu_class_init, 359 .abstract = true, 360 }, 361 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn), 362 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), 363 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn), 364 }; 365 366 DEFINE_TYPES(avr_cpu_type_info) 367