xref: /openbmc/qemu/target/avr/cpu.c (revision 30a1690f)
1 /*
2  * QEMU AVR CPU
3  *
4  * Copyright (c) 2019-2020 Michael Rolnik
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see
18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/qemu-print.h"
24 #include "exec/exec-all.h"
25 #include "cpu.h"
26 #include "disas/dis-asm.h"
27 #include "tcg/debug-assert.h"
28 #include "hw/qdev-properties.h"
29 
30 static void avr_cpu_set_pc(CPUState *cs, vaddr value)
31 {
32     AVRCPU *cpu = AVR_CPU(cs);
33 
34     cpu->env.pc_w = value / 2; /* internally PC points to words */
35 }
36 
37 static vaddr avr_cpu_get_pc(CPUState *cs)
38 {
39     AVRCPU *cpu = AVR_CPU(cs);
40 
41     return cpu->env.pc_w * 2;
42 }
43 
44 static bool avr_cpu_has_work(CPUState *cs)
45 {
46     return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
47             && cpu_interrupts_enabled(cpu_env(cs));
48 }
49 
50 static int avr_cpu_mmu_index(CPUState *cs, bool ifetch)
51 {
52     return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
53 }
54 
55 static void avr_cpu_synchronize_from_tb(CPUState *cs,
56                                         const TranslationBlock *tb)
57 {
58     tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
59     cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */
60 }
61 
62 static void avr_restore_state_to_opc(CPUState *cs,
63                                      const TranslationBlock *tb,
64                                      const uint64_t *data)
65 {
66     cpu_env(cs)->pc_w = data[0];
67 }
68 
69 static void avr_cpu_reset_hold(Object *obj, ResetType type)
70 {
71     CPUState *cs = CPU(obj);
72     AVRCPU *cpu = AVR_CPU(cs);
73     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(obj);
74     CPUAVRState *env = &cpu->env;
75 
76     if (mcc->parent_phases.hold) {
77         mcc->parent_phases.hold(obj, type);
78     }
79 
80     env->pc_w = 0;
81     env->sregI = 1;
82     env->sregC = 0;
83     env->sregZ = 0;
84     env->sregN = 0;
85     env->sregV = 0;
86     env->sregS = 0;
87     env->sregH = 0;
88     env->sregT = 0;
89 
90     env->rampD = 0;
91     env->rampX = 0;
92     env->rampY = 0;
93     env->rampZ = 0;
94     env->eind = 0;
95     env->sp = cpu->init_sp;
96 
97     env->skip = 0;
98 
99     memset(env->r, 0, sizeof(env->r));
100 }
101 
102 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
103 {
104     info->mach = bfd_arch_avr;
105     info->print_insn = avr_print_insn;
106 }
107 
108 static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
109 {
110     CPUState *cs = CPU(dev);
111     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
112     Error *local_err = NULL;
113 
114     cpu_exec_realizefn(cs, &local_err);
115     if (local_err != NULL) {
116         error_propagate(errp, local_err);
117         return;
118     }
119     qemu_init_vcpu(cs);
120     cpu_reset(cs);
121 
122     mcc->parent_realize(dev, errp);
123 }
124 
125 static void avr_cpu_set_int(void *opaque, int irq, int level)
126 {
127     AVRCPU *cpu = opaque;
128     CPUAVRState *env = &cpu->env;
129     CPUState *cs = CPU(cpu);
130     uint64_t mask = (1ull << irq);
131 
132     if (level) {
133         env->intsrc |= mask;
134         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
135     } else {
136         env->intsrc &= ~mask;
137         if (env->intsrc == 0) {
138             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
139         }
140     }
141 }
142 
143 static void avr_cpu_initfn(Object *obj)
144 {
145     AVRCPU *cpu = AVR_CPU(obj);
146 
147     /* Set the number of interrupts supported by the CPU. */
148     qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
149                       sizeof(cpu->env.intsrc) * 8);
150 }
151 
152 static Property avr_cpu_properties[] = {
153     DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0),
154     DEFINE_PROP_END_OF_LIST()
155 };
156 
157 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
158 {
159     return object_class_by_name(cpu_model);
160 }
161 
162 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
163 {
164     CPUAVRState *env = cpu_env(cs);
165     int i;
166 
167     qemu_fprintf(f, "\n");
168     qemu_fprintf(f, "PC:    %06x\n", env->pc_w * 2); /* PC points to words */
169     qemu_fprintf(f, "SP:      %04x\n", env->sp);
170     qemu_fprintf(f, "rampD:     %02x\n", env->rampD >> 16);
171     qemu_fprintf(f, "rampX:     %02x\n", env->rampX >> 16);
172     qemu_fprintf(f, "rampY:     %02x\n", env->rampY >> 16);
173     qemu_fprintf(f, "rampZ:     %02x\n", env->rampZ >> 16);
174     qemu_fprintf(f, "EIND:      %02x\n", env->eind >> 16);
175     qemu_fprintf(f, "X:       %02x%02x\n", env->r[27], env->r[26]);
176     qemu_fprintf(f, "Y:       %02x%02x\n", env->r[29], env->r[28]);
177     qemu_fprintf(f, "Z:       %02x%02x\n", env->r[31], env->r[30]);
178     qemu_fprintf(f, "SREG:    [ %c %c %c %c %c %c %c %c ]\n",
179                  env->sregI ? 'I' : '-',
180                  env->sregT ? 'T' : '-',
181                  env->sregH ? 'H' : '-',
182                  env->sregS ? 'S' : '-',
183                  env->sregV ? 'V' : '-',
184                  env->sregN ? '-' : 'N', /* Zf has negative logic */
185                  env->sregZ ? 'Z' : '-',
186                  env->sregC ? 'I' : '-');
187     qemu_fprintf(f, "SKIP:    %02x\n", env->skip);
188 
189     qemu_fprintf(f, "\n");
190     for (i = 0; i < ARRAY_SIZE(env->r); i++) {
191         qemu_fprintf(f, "R[%02d]:  %02x   ", i, env->r[i]);
192 
193         if ((i % 8) == 7) {
194             qemu_fprintf(f, "\n");
195         }
196     }
197     qemu_fprintf(f, "\n");
198 }
199 
200 #include "hw/core/sysemu-cpu-ops.h"
201 
202 static const struct SysemuCPUOps avr_sysemu_ops = {
203     .get_phys_page_debug = avr_cpu_get_phys_page_debug,
204 };
205 
206 #include "hw/core/tcg-cpu-ops.h"
207 
208 static const TCGCPUOps avr_tcg_ops = {
209     .initialize = avr_cpu_tcg_init,
210     .synchronize_from_tb = avr_cpu_synchronize_from_tb,
211     .restore_state_to_opc = avr_restore_state_to_opc,
212     .cpu_exec_interrupt = avr_cpu_exec_interrupt,
213     .cpu_exec_halt = avr_cpu_has_work,
214     .tlb_fill = avr_cpu_tlb_fill,
215     .do_interrupt = avr_cpu_do_interrupt,
216 };
217 
218 static void avr_cpu_class_init(ObjectClass *oc, void *data)
219 {
220     DeviceClass *dc = DEVICE_CLASS(oc);
221     CPUClass *cc = CPU_CLASS(oc);
222     AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
223     ResettableClass *rc = RESETTABLE_CLASS(oc);
224 
225     device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize);
226 
227     device_class_set_props(dc, avr_cpu_properties);
228 
229     resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL,
230                                        &mcc->parent_phases);
231 
232     cc->class_by_name = avr_cpu_class_by_name;
233 
234     cc->has_work = avr_cpu_has_work;
235     cc->mmu_index = avr_cpu_mmu_index;
236     cc->dump_state = avr_cpu_dump_state;
237     cc->set_pc = avr_cpu_set_pc;
238     cc->get_pc = avr_cpu_get_pc;
239     dc->vmsd = &vms_avr_cpu;
240     cc->sysemu_ops = &avr_sysemu_ops;
241     cc->disas_set_info = avr_cpu_disas_set_info;
242     cc->gdb_read_register = avr_cpu_gdb_read_register;
243     cc->gdb_write_register = avr_cpu_gdb_write_register;
244     cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint;
245     cc->gdb_core_xml_file = "avr-cpu.xml";
246     cc->tcg_ops = &avr_tcg_ops;
247 }
248 
249 /*
250  * Setting features of AVR core type avr5
251  * --------------------------------------
252  *
253  * This type of AVR core is present in the following AVR MCUs:
254  *
255  * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c,
256  * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162,
257  * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a,
258  * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa,
259  * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb,
260  * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323,
261  * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p,
262  * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328,
263  * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa,
264  * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1,
265  * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644,
266  * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p,
267  * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p,
268  * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p,
269  * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2,
270  * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216,
271  * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000
272  */
273 static void avr_avr5_initfn(Object *obj)
274 {
275     CPUAVRState *env = cpu_env(CPU(obj));
276 
277     set_avr_feature(env, AVR_FEATURE_LPM);
278     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
279     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
280     set_avr_feature(env, AVR_FEATURE_SRAM);
281     set_avr_feature(env, AVR_FEATURE_BREAK);
282 
283     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
284     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
285     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
286     set_avr_feature(env, AVR_FEATURE_LPMX);
287     set_avr_feature(env, AVR_FEATURE_MOVW);
288     set_avr_feature(env, AVR_FEATURE_MUL);
289 }
290 
291 /*
292  * Setting features of AVR core type avr51
293  * --------------------------------------
294  *
295  * This type of AVR core is present in the following AVR MCUs:
296  *
297  * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p,
298  * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286,
299  * at90usb1287
300  */
301 static void avr_avr51_initfn(Object *obj)
302 {
303     CPUAVRState *env = cpu_env(CPU(obj));
304 
305     set_avr_feature(env, AVR_FEATURE_LPM);
306     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
307     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
308     set_avr_feature(env, AVR_FEATURE_SRAM);
309     set_avr_feature(env, AVR_FEATURE_BREAK);
310 
311     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
312     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
313     set_avr_feature(env, AVR_FEATURE_RAMPZ);
314     set_avr_feature(env, AVR_FEATURE_ELPMX);
315     set_avr_feature(env, AVR_FEATURE_ELPM);
316     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
317     set_avr_feature(env, AVR_FEATURE_LPMX);
318     set_avr_feature(env, AVR_FEATURE_MOVW);
319     set_avr_feature(env, AVR_FEATURE_MUL);
320 }
321 
322 /*
323  * Setting features of AVR core type avr6
324  * --------------------------------------
325  *
326  * This type of AVR core is present in the following AVR MCUs:
327  *
328  * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2
329  */
330 static void avr_avr6_initfn(Object *obj)
331 {
332     CPUAVRState *env = cpu_env(CPU(obj));
333 
334     set_avr_feature(env, AVR_FEATURE_LPM);
335     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
336     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
337     set_avr_feature(env, AVR_FEATURE_SRAM);
338     set_avr_feature(env, AVR_FEATURE_BREAK);
339 
340     set_avr_feature(env, AVR_FEATURE_3_BYTE_PC);
341     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
342     set_avr_feature(env, AVR_FEATURE_RAMPZ);
343     set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL);
344     set_avr_feature(env, AVR_FEATURE_ELPMX);
345     set_avr_feature(env, AVR_FEATURE_ELPM);
346     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
347     set_avr_feature(env, AVR_FEATURE_LPMX);
348     set_avr_feature(env, AVR_FEATURE_MOVW);
349     set_avr_feature(env, AVR_FEATURE_MUL);
350 }
351 
352 typedef struct AVRCPUInfo {
353     const char *name;
354     void (*initfn)(Object *obj);
355 } AVRCPUInfo;
356 
357 
358 #define DEFINE_AVR_CPU_TYPE(model, initfn) \
359     { \
360         .parent = TYPE_AVR_CPU, \
361         .instance_init = initfn, \
362         .name = AVR_CPU_TYPE_NAME(model), \
363     }
364 
365 static const TypeInfo avr_cpu_type_info[] = {
366     {
367         .name = TYPE_AVR_CPU,
368         .parent = TYPE_CPU,
369         .instance_size = sizeof(AVRCPU),
370         .instance_align = __alignof(AVRCPU),
371         .instance_init = avr_cpu_initfn,
372         .class_size = sizeof(AVRCPUClass),
373         .class_init = avr_cpu_class_init,
374         .abstract = true,
375     },
376     DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn),
377     DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn),
378     DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn),
379 };
380 
381 DEFINE_TYPES(avr_cpu_type_info)
382