1 /* 2 * ARM VFP floating-point operations 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "internals.h" 24 #ifdef CONFIG_TCG 25 #include "qemu/log.h" 26 #include "fpu/softfloat.h" 27 #endif 28 29 /* VFP support. We follow the convention used for VFP instructions: 30 Single precision routines have a "s" suffix, double precision a 31 "d" suffix. */ 32 33 #ifdef CONFIG_TCG 34 35 /* Convert host exception flags to vfp form. */ 36 static inline int vfp_exceptbits_from_host(int host_bits) 37 { 38 int target_bits = 0; 39 40 if (host_bits & float_flag_invalid) { 41 target_bits |= 1; 42 } 43 if (host_bits & float_flag_divbyzero) { 44 target_bits |= 2; 45 } 46 if (host_bits & float_flag_overflow) { 47 target_bits |= 4; 48 } 49 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { 50 target_bits |= 8; 51 } 52 if (host_bits & float_flag_inexact) { 53 target_bits |= 0x10; 54 } 55 if (host_bits & float_flag_input_denormal) { 56 target_bits |= 0x80; 57 } 58 return target_bits; 59 } 60 61 /* Convert vfp exception flags to target form. */ 62 static inline int vfp_exceptbits_to_host(int target_bits) 63 { 64 int host_bits = 0; 65 66 if (target_bits & 1) { 67 host_bits |= float_flag_invalid; 68 } 69 if (target_bits & 2) { 70 host_bits |= float_flag_divbyzero; 71 } 72 if (target_bits & 4) { 73 host_bits |= float_flag_overflow; 74 } 75 if (target_bits & 8) { 76 host_bits |= float_flag_underflow; 77 } 78 if (target_bits & 0x10) { 79 host_bits |= float_flag_inexact; 80 } 81 if (target_bits & 0x80) { 82 host_bits |= float_flag_input_denormal; 83 } 84 return host_bits; 85 } 86 87 static uint32_t vfp_get_fpscr_from_host(CPUARMState *env) 88 { 89 uint32_t i; 90 91 i = get_float_exception_flags(&env->vfp.fp_status); 92 i |= get_float_exception_flags(&env->vfp.standard_fp_status); 93 /* FZ16 does not generate an input denormal exception. */ 94 i |= (get_float_exception_flags(&env->vfp.fp_status_f16) 95 & ~float_flag_input_denormal); 96 i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16) 97 & ~float_flag_input_denormal); 98 return vfp_exceptbits_from_host(i); 99 } 100 101 static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) 102 { 103 int i; 104 uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR]; 105 106 changed ^= val; 107 if (changed & (3 << 22)) { 108 i = (val >> 22) & 3; 109 switch (i) { 110 case FPROUNDING_TIEEVEN: 111 i = float_round_nearest_even; 112 break; 113 case FPROUNDING_POSINF: 114 i = float_round_up; 115 break; 116 case FPROUNDING_NEGINF: 117 i = float_round_down; 118 break; 119 case FPROUNDING_ZERO: 120 i = float_round_to_zero; 121 break; 122 } 123 set_float_rounding_mode(i, &env->vfp.fp_status); 124 set_float_rounding_mode(i, &env->vfp.fp_status_f16); 125 } 126 if (changed & FPCR_FZ16) { 127 bool ftz_enabled = val & FPCR_FZ16; 128 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); 129 set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); 130 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); 131 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); 132 } 133 if (changed & FPCR_FZ) { 134 bool ftz_enabled = val & FPCR_FZ; 135 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); 136 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); 137 } 138 if (changed & FPCR_DN) { 139 bool dnan_enabled = val & FPCR_DN; 140 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); 141 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); 142 } 143 144 /* 145 * The exception flags are ORed together when we read fpscr so we 146 * only need to preserve the current state in one of our 147 * float_status values. 148 */ 149 i = vfp_exceptbits_to_host(val); 150 set_float_exception_flags(i, &env->vfp.fp_status); 151 set_float_exception_flags(0, &env->vfp.fp_status_f16); 152 set_float_exception_flags(0, &env->vfp.standard_fp_status); 153 set_float_exception_flags(0, &env->vfp.standard_fp_status_f16); 154 } 155 156 #else 157 158 static uint32_t vfp_get_fpscr_from_host(CPUARMState *env) 159 { 160 return 0; 161 } 162 163 static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) 164 { 165 } 166 167 #endif 168 169 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) 170 { 171 uint32_t i, fpscr; 172 173 fpscr = env->vfp.xregs[ARM_VFP_FPSCR] 174 | (env->vfp.vec_len << 16) 175 | (env->vfp.vec_stride << 20); 176 177 fpscr |= vfp_get_fpscr_from_host(env); 178 179 i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3]; 180 fpscr |= i ? FPCR_QC : 0; 181 182 return fpscr; 183 } 184 185 uint32_t vfp_get_fpscr(CPUARMState *env) 186 { 187 return HELPER(vfp_get_fpscr)(env); 188 } 189 190 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 191 { 192 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ 193 if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { 194 val &= ~FPCR_FZ16; 195 } 196 197 if (arm_feature(env, ARM_FEATURE_M)) { 198 /* 199 * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits 200 * and also for the trapped-exception-handling bits IxE. 201 */ 202 val &= 0xf7c0009f; 203 } 204 205 vfp_set_fpscr_to_host(env, val); 206 207 /* 208 * We don't implement trapped exception handling, so the 209 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) 210 * 211 * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC 212 * (which are stored in fp_status), and the other RES0 bits 213 * in between, then we clear all of the low 16 bits. 214 */ 215 env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000; 216 env->vfp.vec_len = (val >> 16) & 7; 217 env->vfp.vec_stride = (val >> 20) & 3; 218 219 /* 220 * The bit we set within fpscr_q is arbitrary; the register as a 221 * whole being zero/non-zero is what counts. 222 */ 223 env->vfp.qc[0] = val & FPCR_QC; 224 env->vfp.qc[1] = 0; 225 env->vfp.qc[2] = 0; 226 env->vfp.qc[3] = 0; 227 } 228 229 void vfp_set_fpscr(CPUARMState *env, uint32_t val) 230 { 231 HELPER(vfp_set_fpscr)(env, val); 232 } 233 234 #ifdef CONFIG_TCG 235 236 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) 237 238 #define VFP_BINOP(name) \ 239 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \ 240 { \ 241 float_status *fpst = fpstp; \ 242 return float16_ ## name(a, b, fpst); \ 243 } \ 244 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ 245 { \ 246 float_status *fpst = fpstp; \ 247 return float32_ ## name(a, b, fpst); \ 248 } \ 249 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ 250 { \ 251 float_status *fpst = fpstp; \ 252 return float64_ ## name(a, b, fpst); \ 253 } 254 VFP_BINOP(add) 255 VFP_BINOP(sub) 256 VFP_BINOP(mul) 257 VFP_BINOP(div) 258 VFP_BINOP(min) 259 VFP_BINOP(max) 260 VFP_BINOP(minnum) 261 VFP_BINOP(maxnum) 262 #undef VFP_BINOP 263 264 dh_ctype_f16 VFP_HELPER(neg, h)(dh_ctype_f16 a) 265 { 266 return float16_chs(a); 267 } 268 269 float32 VFP_HELPER(neg, s)(float32 a) 270 { 271 return float32_chs(a); 272 } 273 274 float64 VFP_HELPER(neg, d)(float64 a) 275 { 276 return float64_chs(a); 277 } 278 279 dh_ctype_f16 VFP_HELPER(abs, h)(dh_ctype_f16 a) 280 { 281 return float16_abs(a); 282 } 283 284 float32 VFP_HELPER(abs, s)(float32 a) 285 { 286 return float32_abs(a); 287 } 288 289 float64 VFP_HELPER(abs, d)(float64 a) 290 { 291 return float64_abs(a); 292 } 293 294 dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env) 295 { 296 return float16_sqrt(a, &env->vfp.fp_status_f16); 297 } 298 299 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) 300 { 301 return float32_sqrt(a, &env->vfp.fp_status); 302 } 303 304 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) 305 { 306 return float64_sqrt(a, &env->vfp.fp_status); 307 } 308 309 static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp) 310 { 311 uint32_t flags; 312 switch (cmp) { 313 case float_relation_equal: 314 flags = 0x6; 315 break; 316 case float_relation_less: 317 flags = 0x8; 318 break; 319 case float_relation_greater: 320 flags = 0x2; 321 break; 322 case float_relation_unordered: 323 flags = 0x3; 324 break; 325 default: 326 g_assert_not_reached(); 327 } 328 env->vfp.xregs[ARM_VFP_FPSCR] = 329 deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags); 330 } 331 332 /* XXX: check quiet/signaling case */ 333 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \ 334 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ 335 { \ 336 softfloat_to_vfp_compare(env, \ 337 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \ 338 } \ 339 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ 340 { \ 341 softfloat_to_vfp_compare(env, \ 342 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \ 343 } 344 DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16) 345 DO_VFP_cmp(s, float32, float32, fp_status) 346 DO_VFP_cmp(d, float64, float64, fp_status) 347 #undef DO_VFP_cmp 348 349 /* Integer to float and float to integer conversions */ 350 351 #define CONV_ITOF(name, ftype, fsz, sign) \ 352 ftype HELPER(name)(uint32_t x, void *fpstp) \ 353 { \ 354 float_status *fpst = fpstp; \ 355 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ 356 } 357 358 #define CONV_FTOI(name, ftype, fsz, sign, round) \ 359 sign##int32_t HELPER(name)(ftype x, void *fpstp) \ 360 { \ 361 float_status *fpst = fpstp; \ 362 if (float##fsz##_is_any_nan(x)) { \ 363 float_raise(float_flag_invalid, fpst); \ 364 return 0; \ 365 } \ 366 return float##fsz##_to_##sign##int32##round(x, fpst); \ 367 } 368 369 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \ 370 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \ 371 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \ 372 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero) 373 374 FLOAT_CONVS(si, h, uint32_t, 16, ) 375 FLOAT_CONVS(si, s, float32, 32, ) 376 FLOAT_CONVS(si, d, float64, 64, ) 377 FLOAT_CONVS(ui, h, uint32_t, 16, u) 378 FLOAT_CONVS(ui, s, float32, 32, u) 379 FLOAT_CONVS(ui, d, float64, 64, u) 380 381 #undef CONV_ITOF 382 #undef CONV_FTOI 383 #undef FLOAT_CONVS 384 385 /* floating point conversion */ 386 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) 387 { 388 return float32_to_float64(x, &env->vfp.fp_status); 389 } 390 391 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) 392 { 393 return float64_to_float32(x, &env->vfp.fp_status); 394 } 395 396 /* VFP3 fixed point conversion. */ 397 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 398 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ 399 void *fpstp) \ 400 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); } 401 402 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \ 403 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \ 404 void *fpst) \ 405 { \ 406 if (unlikely(float##fsz##_is_any_nan(x))) { \ 407 float_raise(float_flag_invalid, fpst); \ 408 return 0; \ 409 } \ 410 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \ 411 } 412 413 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \ 414 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 415 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 416 float_round_to_zero, _round_to_zero) \ 417 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 418 get_float_rounding_mode(fpst), ) 419 420 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \ 421 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 422 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 423 get_float_rounding_mode(fpst), ) 424 425 VFP_CONV_FIX(sh, d, 64, float64, 64, int16) 426 VFP_CONV_FIX(sl, d, 64, float64, 64, int32) 427 VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64) 428 VFP_CONV_FIX(uh, d, 64, float64, 64, uint16) 429 VFP_CONV_FIX(ul, d, 64, float64, 64, uint32) 430 VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64) 431 VFP_CONV_FIX(sh, s, 32, float32, 32, int16) 432 VFP_CONV_FIX(sl, s, 32, float32, 32, int32) 433 VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64) 434 VFP_CONV_FIX(uh, s, 32, float32, 32, uint16) 435 VFP_CONV_FIX(ul, s, 32, float32, 32, uint32) 436 VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64) 437 VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16) 438 VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32) 439 VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64) 440 VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16) 441 VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32) 442 VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64) 443 444 #undef VFP_CONV_FIX 445 #undef VFP_CONV_FIX_FLOAT 446 #undef VFP_CONV_FLOAT_FIX_ROUND 447 #undef VFP_CONV_FIX_A64 448 449 /* Set the current fp rounding mode and return the old one. 450 * The argument is a softfloat float_round_ value. 451 */ 452 uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) 453 { 454 float_status *fp_status = fpstp; 455 456 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 457 set_float_rounding_mode(rmode, fp_status); 458 459 return prev_rmode; 460 } 461 462 /* Half precision conversions. */ 463 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode) 464 { 465 /* Squash FZ16 to 0 for the duration of conversion. In this case, 466 * it would affect flushing input denormals. 467 */ 468 float_status *fpst = fpstp; 469 bool save = get_flush_inputs_to_zero(fpst); 470 set_flush_inputs_to_zero(false, fpst); 471 float32 r = float16_to_float32(a, !ahp_mode, fpst); 472 set_flush_inputs_to_zero(save, fpst); 473 return r; 474 } 475 476 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) 477 { 478 /* Squash FZ16 to 0 for the duration of conversion. In this case, 479 * it would affect flushing output denormals. 480 */ 481 float_status *fpst = fpstp; 482 bool save = get_flush_to_zero(fpst); 483 set_flush_to_zero(false, fpst); 484 float16 r = float32_to_float16(a, !ahp_mode, fpst); 485 set_flush_to_zero(save, fpst); 486 return r; 487 } 488 489 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode) 490 { 491 /* Squash FZ16 to 0 for the duration of conversion. In this case, 492 * it would affect flushing input denormals. 493 */ 494 float_status *fpst = fpstp; 495 bool save = get_flush_inputs_to_zero(fpst); 496 set_flush_inputs_to_zero(false, fpst); 497 float64 r = float16_to_float64(a, !ahp_mode, fpst); 498 set_flush_inputs_to_zero(save, fpst); 499 return r; 500 } 501 502 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) 503 { 504 /* Squash FZ16 to 0 for the duration of conversion. In this case, 505 * it would affect flushing output denormals. 506 */ 507 float_status *fpst = fpstp; 508 bool save = get_flush_to_zero(fpst); 509 set_flush_to_zero(false, fpst); 510 float16 r = float64_to_float16(a, !ahp_mode, fpst); 511 set_flush_to_zero(save, fpst); 512 return r; 513 } 514 515 /* NEON helpers. */ 516 517 /* Constants 256 and 512 are used in some helpers; we avoid relying on 518 * int->float conversions at run-time. */ 519 #define float64_256 make_float64(0x4070000000000000LL) 520 #define float64_512 make_float64(0x4080000000000000LL) 521 #define float16_maxnorm make_float16(0x7bff) 522 #define float32_maxnorm make_float32(0x7f7fffff) 523 #define float64_maxnorm make_float64(0x7fefffffffffffffLL) 524 525 /* Reciprocal functions 526 * 527 * The algorithm that must be used to calculate the estimate 528 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate 529 */ 530 531 /* See RecipEstimate() 532 * 533 * input is a 9 bit fixed point number 534 * input range 256 .. 511 for a number from 0.5 <= x < 1.0. 535 * result range 256 .. 511 for a number from 1.0 to 511/256. 536 */ 537 538 static int recip_estimate(int input) 539 { 540 int a, b, r; 541 assert(256 <= input && input < 512); 542 a = (input * 2) + 1; 543 b = (1 << 19) / a; 544 r = (b + 1) >> 1; 545 assert(256 <= r && r < 512); 546 return r; 547 } 548 549 /* 550 * Common wrapper to call recip_estimate 551 * 552 * The parameters are exponent and 64 bit fraction (without implicit 553 * bit) where the binary point is nominally at bit 52. Returns a 554 * float64 which can then be rounded to the appropriate size by the 555 * callee. 556 */ 557 558 static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac) 559 { 560 uint32_t scaled, estimate; 561 uint64_t result_frac; 562 int result_exp; 563 564 /* Handle sub-normals */ 565 if (*exp == 0) { 566 if (extract64(frac, 51, 1) == 0) { 567 *exp = -1; 568 frac <<= 2; 569 } else { 570 frac <<= 1; 571 } 572 } 573 574 /* scaled = UInt('1':fraction<51:44>) */ 575 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); 576 estimate = recip_estimate(scaled); 577 578 result_exp = exp_off - *exp; 579 result_frac = deposit64(0, 44, 8, estimate); 580 if (result_exp == 0) { 581 result_frac = deposit64(result_frac >> 1, 51, 1, 1); 582 } else if (result_exp == -1) { 583 result_frac = deposit64(result_frac >> 2, 50, 2, 1); 584 result_exp = 0; 585 } 586 587 *exp = result_exp; 588 589 return result_frac; 590 } 591 592 static bool round_to_inf(float_status *fpst, bool sign_bit) 593 { 594 switch (fpst->float_rounding_mode) { 595 case float_round_nearest_even: /* Round to Nearest */ 596 return true; 597 case float_round_up: /* Round to +Inf */ 598 return !sign_bit; 599 case float_round_down: /* Round to -Inf */ 600 return sign_bit; 601 case float_round_to_zero: /* Round to Zero */ 602 return false; 603 default: 604 g_assert_not_reached(); 605 } 606 } 607 608 uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) 609 { 610 float_status *fpst = fpstp; 611 float16 f16 = float16_squash_input_denormal(input, fpst); 612 uint32_t f16_val = float16_val(f16); 613 uint32_t f16_sign = float16_is_neg(f16); 614 int f16_exp = extract32(f16_val, 10, 5); 615 uint32_t f16_frac = extract32(f16_val, 0, 10); 616 uint64_t f64_frac; 617 618 if (float16_is_any_nan(f16)) { 619 float16 nan = f16; 620 if (float16_is_signaling_nan(f16, fpst)) { 621 float_raise(float_flag_invalid, fpst); 622 nan = float16_silence_nan(f16, fpst); 623 } 624 if (fpst->default_nan_mode) { 625 nan = float16_default_nan(fpst); 626 } 627 return nan; 628 } else if (float16_is_infinity(f16)) { 629 return float16_set_sign(float16_zero, float16_is_neg(f16)); 630 } else if (float16_is_zero(f16)) { 631 float_raise(float_flag_divbyzero, fpst); 632 return float16_set_sign(float16_infinity, float16_is_neg(f16)); 633 } else if (float16_abs(f16) < (1 << 8)) { 634 /* Abs(value) < 2.0^-16 */ 635 float_raise(float_flag_overflow | float_flag_inexact, fpst); 636 if (round_to_inf(fpst, f16_sign)) { 637 return float16_set_sign(float16_infinity, f16_sign); 638 } else { 639 return float16_set_sign(float16_maxnorm, f16_sign); 640 } 641 } else if (f16_exp >= 29 && fpst->flush_to_zero) { 642 float_raise(float_flag_underflow, fpst); 643 return float16_set_sign(float16_zero, float16_is_neg(f16)); 644 } 645 646 f64_frac = call_recip_estimate(&f16_exp, 29, 647 ((uint64_t) f16_frac) << (52 - 10)); 648 649 /* result = sign : result_exp<4:0> : fraction<51:42> */ 650 f16_val = deposit32(0, 15, 1, f16_sign); 651 f16_val = deposit32(f16_val, 10, 5, f16_exp); 652 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10)); 653 return make_float16(f16_val); 654 } 655 656 float32 HELPER(recpe_f32)(float32 input, void *fpstp) 657 { 658 float_status *fpst = fpstp; 659 float32 f32 = float32_squash_input_denormal(input, fpst); 660 uint32_t f32_val = float32_val(f32); 661 bool f32_sign = float32_is_neg(f32); 662 int f32_exp = extract32(f32_val, 23, 8); 663 uint32_t f32_frac = extract32(f32_val, 0, 23); 664 uint64_t f64_frac; 665 666 if (float32_is_any_nan(f32)) { 667 float32 nan = f32; 668 if (float32_is_signaling_nan(f32, fpst)) { 669 float_raise(float_flag_invalid, fpst); 670 nan = float32_silence_nan(f32, fpst); 671 } 672 if (fpst->default_nan_mode) { 673 nan = float32_default_nan(fpst); 674 } 675 return nan; 676 } else if (float32_is_infinity(f32)) { 677 return float32_set_sign(float32_zero, float32_is_neg(f32)); 678 } else if (float32_is_zero(f32)) { 679 float_raise(float_flag_divbyzero, fpst); 680 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 681 } else if (float32_abs(f32) < (1ULL << 21)) { 682 /* Abs(value) < 2.0^-128 */ 683 float_raise(float_flag_overflow | float_flag_inexact, fpst); 684 if (round_to_inf(fpst, f32_sign)) { 685 return float32_set_sign(float32_infinity, f32_sign); 686 } else { 687 return float32_set_sign(float32_maxnorm, f32_sign); 688 } 689 } else if (f32_exp >= 253 && fpst->flush_to_zero) { 690 float_raise(float_flag_underflow, fpst); 691 return float32_set_sign(float32_zero, float32_is_neg(f32)); 692 } 693 694 f64_frac = call_recip_estimate(&f32_exp, 253, 695 ((uint64_t) f32_frac) << (52 - 23)); 696 697 /* result = sign : result_exp<7:0> : fraction<51:29> */ 698 f32_val = deposit32(0, 31, 1, f32_sign); 699 f32_val = deposit32(f32_val, 23, 8, f32_exp); 700 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)); 701 return make_float32(f32_val); 702 } 703 704 float64 HELPER(recpe_f64)(float64 input, void *fpstp) 705 { 706 float_status *fpst = fpstp; 707 float64 f64 = float64_squash_input_denormal(input, fpst); 708 uint64_t f64_val = float64_val(f64); 709 bool f64_sign = float64_is_neg(f64); 710 int f64_exp = extract64(f64_val, 52, 11); 711 uint64_t f64_frac = extract64(f64_val, 0, 52); 712 713 /* Deal with any special cases */ 714 if (float64_is_any_nan(f64)) { 715 float64 nan = f64; 716 if (float64_is_signaling_nan(f64, fpst)) { 717 float_raise(float_flag_invalid, fpst); 718 nan = float64_silence_nan(f64, fpst); 719 } 720 if (fpst->default_nan_mode) { 721 nan = float64_default_nan(fpst); 722 } 723 return nan; 724 } else if (float64_is_infinity(f64)) { 725 return float64_set_sign(float64_zero, float64_is_neg(f64)); 726 } else if (float64_is_zero(f64)) { 727 float_raise(float_flag_divbyzero, fpst); 728 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 729 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { 730 /* Abs(value) < 2.0^-1024 */ 731 float_raise(float_flag_overflow | float_flag_inexact, fpst); 732 if (round_to_inf(fpst, f64_sign)) { 733 return float64_set_sign(float64_infinity, f64_sign); 734 } else { 735 return float64_set_sign(float64_maxnorm, f64_sign); 736 } 737 } else if (f64_exp >= 2045 && fpst->flush_to_zero) { 738 float_raise(float_flag_underflow, fpst); 739 return float64_set_sign(float64_zero, float64_is_neg(f64)); 740 } 741 742 f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac); 743 744 /* result = sign : result_exp<10:0> : fraction<51:0>; */ 745 f64_val = deposit64(0, 63, 1, f64_sign); 746 f64_val = deposit64(f64_val, 52, 11, f64_exp); 747 f64_val = deposit64(f64_val, 0, 52, f64_frac); 748 return make_float64(f64_val); 749 } 750 751 /* The algorithm that must be used to calculate the estimate 752 * is specified by the ARM ARM. 753 */ 754 755 static int do_recip_sqrt_estimate(int a) 756 { 757 int b, estimate; 758 759 assert(128 <= a && a < 512); 760 if (a < 256) { 761 a = a * 2 + 1; 762 } else { 763 a = (a >> 1) << 1; 764 a = (a + 1) * 2; 765 } 766 b = 512; 767 while (a * (b + 1) * (b + 1) < (1 << 28)) { 768 b += 1; 769 } 770 estimate = (b + 1) / 2; 771 assert(256 <= estimate && estimate < 512); 772 773 return estimate; 774 } 775 776 777 static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac) 778 { 779 int estimate; 780 uint32_t scaled; 781 782 if (*exp == 0) { 783 while (extract64(frac, 51, 1) == 0) { 784 frac = frac << 1; 785 *exp -= 1; 786 } 787 frac = extract64(frac, 0, 51) << 1; 788 } 789 790 if (*exp & 1) { 791 /* scaled = UInt('01':fraction<51:45>) */ 792 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); 793 } else { 794 /* scaled = UInt('1':fraction<51:44>) */ 795 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); 796 } 797 estimate = do_recip_sqrt_estimate(scaled); 798 799 *exp = (exp_off - *exp) / 2; 800 return extract64(estimate, 0, 8) << 44; 801 } 802 803 uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) 804 { 805 float_status *s = fpstp; 806 float16 f16 = float16_squash_input_denormal(input, s); 807 uint16_t val = float16_val(f16); 808 bool f16_sign = float16_is_neg(f16); 809 int f16_exp = extract32(val, 10, 5); 810 uint16_t f16_frac = extract32(val, 0, 10); 811 uint64_t f64_frac; 812 813 if (float16_is_any_nan(f16)) { 814 float16 nan = f16; 815 if (float16_is_signaling_nan(f16, s)) { 816 float_raise(float_flag_invalid, s); 817 nan = float16_silence_nan(f16, s); 818 } 819 if (s->default_nan_mode) { 820 nan = float16_default_nan(s); 821 } 822 return nan; 823 } else if (float16_is_zero(f16)) { 824 float_raise(float_flag_divbyzero, s); 825 return float16_set_sign(float16_infinity, f16_sign); 826 } else if (f16_sign) { 827 float_raise(float_flag_invalid, s); 828 return float16_default_nan(s); 829 } else if (float16_is_infinity(f16)) { 830 return float16_zero; 831 } 832 833 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 834 * preserving the parity of the exponent. */ 835 836 f64_frac = ((uint64_t) f16_frac) << (52 - 10); 837 838 f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac); 839 840 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */ 841 val = deposit32(0, 15, 1, f16_sign); 842 val = deposit32(val, 10, 5, f16_exp); 843 val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8)); 844 return make_float16(val); 845 } 846 847 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) 848 { 849 float_status *s = fpstp; 850 float32 f32 = float32_squash_input_denormal(input, s); 851 uint32_t val = float32_val(f32); 852 uint32_t f32_sign = float32_is_neg(f32); 853 int f32_exp = extract32(val, 23, 8); 854 uint32_t f32_frac = extract32(val, 0, 23); 855 uint64_t f64_frac; 856 857 if (float32_is_any_nan(f32)) { 858 float32 nan = f32; 859 if (float32_is_signaling_nan(f32, s)) { 860 float_raise(float_flag_invalid, s); 861 nan = float32_silence_nan(f32, s); 862 } 863 if (s->default_nan_mode) { 864 nan = float32_default_nan(s); 865 } 866 return nan; 867 } else if (float32_is_zero(f32)) { 868 float_raise(float_flag_divbyzero, s); 869 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 870 } else if (float32_is_neg(f32)) { 871 float_raise(float_flag_invalid, s); 872 return float32_default_nan(s); 873 } else if (float32_is_infinity(f32)) { 874 return float32_zero; 875 } 876 877 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 878 * preserving the parity of the exponent. */ 879 880 f64_frac = ((uint64_t) f32_frac) << 29; 881 882 f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac); 883 884 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */ 885 val = deposit32(0, 31, 1, f32_sign); 886 val = deposit32(val, 23, 8, f32_exp); 887 val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8)); 888 return make_float32(val); 889 } 890 891 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) 892 { 893 float_status *s = fpstp; 894 float64 f64 = float64_squash_input_denormal(input, s); 895 uint64_t val = float64_val(f64); 896 bool f64_sign = float64_is_neg(f64); 897 int f64_exp = extract64(val, 52, 11); 898 uint64_t f64_frac = extract64(val, 0, 52); 899 900 if (float64_is_any_nan(f64)) { 901 float64 nan = f64; 902 if (float64_is_signaling_nan(f64, s)) { 903 float_raise(float_flag_invalid, s); 904 nan = float64_silence_nan(f64, s); 905 } 906 if (s->default_nan_mode) { 907 nan = float64_default_nan(s); 908 } 909 return nan; 910 } else if (float64_is_zero(f64)) { 911 float_raise(float_flag_divbyzero, s); 912 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 913 } else if (float64_is_neg(f64)) { 914 float_raise(float_flag_invalid, s); 915 return float64_default_nan(s); 916 } else if (float64_is_infinity(f64)) { 917 return float64_zero; 918 } 919 920 f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac); 921 922 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */ 923 val = deposit64(0, 61, 1, f64_sign); 924 val = deposit64(val, 52, 11, f64_exp); 925 val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8)); 926 return make_float64(val); 927 } 928 929 uint32_t HELPER(recpe_u32)(uint32_t a) 930 { 931 int input, estimate; 932 933 if ((a & 0x80000000) == 0) { 934 return 0xffffffff; 935 } 936 937 input = extract32(a, 23, 9); 938 estimate = recip_estimate(input); 939 940 return deposit32(0, (32 - 9), 9, estimate); 941 } 942 943 uint32_t HELPER(rsqrte_u32)(uint32_t a) 944 { 945 int estimate; 946 947 if ((a & 0xc0000000) == 0) { 948 return 0xffffffff; 949 } 950 951 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9)); 952 953 return deposit32(0, 23, 9, estimate); 954 } 955 956 /* VFPv4 fused multiply-accumulate */ 957 dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b, 958 dh_ctype_f16 c, void *fpstp) 959 { 960 float_status *fpst = fpstp; 961 return float16_muladd(a, b, c, 0, fpst); 962 } 963 964 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) 965 { 966 float_status *fpst = fpstp; 967 return float32_muladd(a, b, c, 0, fpst); 968 } 969 970 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) 971 { 972 float_status *fpst = fpstp; 973 return float64_muladd(a, b, c, 0, fpst); 974 } 975 976 /* ARMv8 round to integral */ 977 dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status) 978 { 979 return float16_round_to_int(x, fp_status); 980 } 981 982 float32 HELPER(rints_exact)(float32 x, void *fp_status) 983 { 984 return float32_round_to_int(x, fp_status); 985 } 986 987 float64 HELPER(rintd_exact)(float64 x, void *fp_status) 988 { 989 return float64_round_to_int(x, fp_status); 990 } 991 992 dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status) 993 { 994 int old_flags = get_float_exception_flags(fp_status), new_flags; 995 float16 ret; 996 997 ret = float16_round_to_int(x, fp_status); 998 999 /* Suppress any inexact exceptions the conversion produced */ 1000 if (!(old_flags & float_flag_inexact)) { 1001 new_flags = get_float_exception_flags(fp_status); 1002 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1003 } 1004 1005 return ret; 1006 } 1007 1008 float32 HELPER(rints)(float32 x, void *fp_status) 1009 { 1010 int old_flags = get_float_exception_flags(fp_status), new_flags; 1011 float32 ret; 1012 1013 ret = float32_round_to_int(x, fp_status); 1014 1015 /* Suppress any inexact exceptions the conversion produced */ 1016 if (!(old_flags & float_flag_inexact)) { 1017 new_flags = get_float_exception_flags(fp_status); 1018 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1019 } 1020 1021 return ret; 1022 } 1023 1024 float64 HELPER(rintd)(float64 x, void *fp_status) 1025 { 1026 int old_flags = get_float_exception_flags(fp_status), new_flags; 1027 float64 ret; 1028 1029 ret = float64_round_to_int(x, fp_status); 1030 1031 new_flags = get_float_exception_flags(fp_status); 1032 1033 /* Suppress any inexact exceptions the conversion produced */ 1034 if (!(old_flags & float_flag_inexact)) { 1035 new_flags = get_float_exception_flags(fp_status); 1036 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1037 } 1038 1039 return ret; 1040 } 1041 1042 /* Convert ARM rounding mode to softfloat */ 1043 int arm_rmode_to_sf(int rmode) 1044 { 1045 switch (rmode) { 1046 case FPROUNDING_TIEAWAY: 1047 rmode = float_round_ties_away; 1048 break; 1049 case FPROUNDING_ODD: 1050 /* FIXME: add support for TIEAWAY and ODD */ 1051 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", 1052 rmode); 1053 /* fall through for now */ 1054 case FPROUNDING_TIEEVEN: 1055 default: 1056 rmode = float_round_nearest_even; 1057 break; 1058 case FPROUNDING_POSINF: 1059 rmode = float_round_up; 1060 break; 1061 case FPROUNDING_NEGINF: 1062 rmode = float_round_down; 1063 break; 1064 case FPROUNDING_ZERO: 1065 rmode = float_round_to_zero; 1066 break; 1067 } 1068 return rmode; 1069 } 1070 1071 /* 1072 * Implement float64 to int32_t conversion without saturation; 1073 * the result is supplied modulo 2^32. 1074 */ 1075 uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) 1076 { 1077 float_status *status = vstatus; 1078 uint32_t exp, sign; 1079 uint64_t frac; 1080 uint32_t inexact = 1; /* !Z */ 1081 1082 sign = extract64(value, 63, 1); 1083 exp = extract64(value, 52, 11); 1084 frac = extract64(value, 0, 52); 1085 1086 if (exp == 0) { 1087 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ 1088 inexact = sign; 1089 if (frac != 0) { 1090 if (status->flush_inputs_to_zero) { 1091 float_raise(float_flag_input_denormal, status); 1092 } else { 1093 float_raise(float_flag_inexact, status); 1094 inexact = 1; 1095 } 1096 } 1097 frac = 0; 1098 } else if (exp == 0x7ff) { 1099 /* This operation raises Invalid for both NaN and overflow (Inf). */ 1100 float_raise(float_flag_invalid, status); 1101 frac = 0; 1102 } else { 1103 int true_exp = exp - 1023; 1104 int shift = true_exp - 52; 1105 1106 /* Restore implicit bit. */ 1107 frac |= 1ull << 52; 1108 1109 /* Shift the fraction into place. */ 1110 if (shift >= 0) { 1111 /* The number is so large we must shift the fraction left. */ 1112 if (shift >= 64) { 1113 /* The fraction is shifted out entirely. */ 1114 frac = 0; 1115 } else { 1116 frac <<= shift; 1117 } 1118 } else if (shift > -64) { 1119 /* Normal case -- shift right and notice if bits shift out. */ 1120 inexact = (frac << (64 + shift)) != 0; 1121 frac >>= -shift; 1122 } else { 1123 /* The fraction is shifted out entirely. */ 1124 frac = 0; 1125 } 1126 1127 /* Notice overflow or inexact exceptions. */ 1128 if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) { 1129 /* Overflow, for which this operation raises invalid. */ 1130 float_raise(float_flag_invalid, status); 1131 inexact = 1; 1132 } else if (inexact) { 1133 float_raise(float_flag_inexact, status); 1134 } 1135 1136 /* Honor the sign. */ 1137 if (sign) { 1138 frac = -frac; 1139 } 1140 } 1141 1142 /* Pack the result and the env->ZF representation of Z together. */ 1143 return deposit64(frac, 32, 32, inexact); 1144 } 1145 1146 uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) 1147 { 1148 uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status); 1149 uint32_t result = pair; 1150 uint32_t z = (pair >> 32) == 0; 1151 1152 /* Store Z, clear NCV, in FPSCR.NZCV. */ 1153 env->vfp.xregs[ARM_VFP_FPSCR] 1154 = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z); 1155 1156 return result; 1157 } 1158 1159 /* Round a float32 to an integer that fits in int32_t or int64_t. */ 1160 static float32 frint_s(float32 f, float_status *fpst, int intsize) 1161 { 1162 int old_flags = get_float_exception_flags(fpst); 1163 uint32_t exp = extract32(f, 23, 8); 1164 1165 if (unlikely(exp == 0xff)) { 1166 /* NaN or Inf. */ 1167 goto overflow; 1168 } 1169 1170 /* Round and re-extract the exponent. */ 1171 f = float32_round_to_int(f, fpst); 1172 exp = extract32(f, 23, 8); 1173 1174 /* Validate the range of the result. */ 1175 if (exp < 126 + intsize) { 1176 /* abs(F) <= INT{N}_MAX */ 1177 return f; 1178 } 1179 if (exp == 126 + intsize) { 1180 uint32_t sign = extract32(f, 31, 1); 1181 uint32_t frac = extract32(f, 0, 23); 1182 if (sign && frac == 0) { 1183 /* F == INT{N}_MIN */ 1184 return f; 1185 } 1186 } 1187 1188 overflow: 1189 /* 1190 * Raise Invalid and return INT{N}_MIN as a float. Revert any 1191 * inexact exception float32_round_to_int may have raised. 1192 */ 1193 set_float_exception_flags(old_flags | float_flag_invalid, fpst); 1194 return (0x100u + 126u + intsize) << 23; 1195 } 1196 1197 float32 HELPER(frint32_s)(float32 f, void *fpst) 1198 { 1199 return frint_s(f, fpst, 32); 1200 } 1201 1202 float32 HELPER(frint64_s)(float32 f, void *fpst) 1203 { 1204 return frint_s(f, fpst, 64); 1205 } 1206 1207 /* Round a float64 to an integer that fits in int32_t or int64_t. */ 1208 static float64 frint_d(float64 f, float_status *fpst, int intsize) 1209 { 1210 int old_flags = get_float_exception_flags(fpst); 1211 uint32_t exp = extract64(f, 52, 11); 1212 1213 if (unlikely(exp == 0x7ff)) { 1214 /* NaN or Inf. */ 1215 goto overflow; 1216 } 1217 1218 /* Round and re-extract the exponent. */ 1219 f = float64_round_to_int(f, fpst); 1220 exp = extract64(f, 52, 11); 1221 1222 /* Validate the range of the result. */ 1223 if (exp < 1022 + intsize) { 1224 /* abs(F) <= INT{N}_MAX */ 1225 return f; 1226 } 1227 if (exp == 1022 + intsize) { 1228 uint64_t sign = extract64(f, 63, 1); 1229 uint64_t frac = extract64(f, 0, 52); 1230 if (sign && frac == 0) { 1231 /* F == INT{N}_MIN */ 1232 return f; 1233 } 1234 } 1235 1236 overflow: 1237 /* 1238 * Raise Invalid and return INT{N}_MIN as a float. Revert any 1239 * inexact exception float64_round_to_int may have raised. 1240 */ 1241 set_float_exception_flags(old_flags | float_flag_invalid, fpst); 1242 return (uint64_t)(0x800 + 1022 + intsize) << 52; 1243 } 1244 1245 float64 HELPER(frint32_d)(float64 f, void *fpst) 1246 { 1247 return frint_d(f, fpst, 32); 1248 } 1249 1250 float64 HELPER(frint64_d)(float64 f, void *fpst) 1251 { 1252 return frint_d(f, fpst, 64); 1253 } 1254 1255 void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg) 1256 { 1257 uint32_t syndrome; 1258 1259 switch (reg) { 1260 case ARM_VFP_MVFR0: 1261 case ARM_VFP_MVFR1: 1262 case ARM_VFP_MVFR2: 1263 if (!(arm_hcr_el2_eff(env) & HCR_TID3)) { 1264 return; 1265 } 1266 break; 1267 case ARM_VFP_FPSID: 1268 if (!(arm_hcr_el2_eff(env) & HCR_TID0)) { 1269 return; 1270 } 1271 break; 1272 default: 1273 g_assert_not_reached(); 1274 } 1275 1276 syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT) 1277 | ARM_EL_IL 1278 | (1 << 24) | (0xe << 20) | (7 << 14) 1279 | (reg << 10) | (rt << 5) | 1); 1280 1281 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); 1282 } 1283 1284 #endif 1285