1 /* 2 * ARM VFP floating-point operations 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "internals.h" 24 #include "cpu-features.h" 25 #ifdef CONFIG_TCG 26 #include "qemu/log.h" 27 #include "fpu/softfloat.h" 28 #endif 29 30 /* VFP support. We follow the convention used for VFP instructions: 31 Single precision routines have a "s" suffix, double precision a 32 "d" suffix. */ 33 34 #ifdef CONFIG_TCG 35 36 /* Convert host exception flags to vfp form. */ 37 static inline int vfp_exceptbits_from_host(int host_bits) 38 { 39 int target_bits = 0; 40 41 if (host_bits & float_flag_invalid) { 42 target_bits |= 1; 43 } 44 if (host_bits & float_flag_divbyzero) { 45 target_bits |= 2; 46 } 47 if (host_bits & float_flag_overflow) { 48 target_bits |= 4; 49 } 50 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { 51 target_bits |= 8; 52 } 53 if (host_bits & float_flag_inexact) { 54 target_bits |= 0x10; 55 } 56 if (host_bits & float_flag_input_denormal) { 57 target_bits |= 0x80; 58 } 59 return target_bits; 60 } 61 62 static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) 63 { 64 uint32_t i; 65 66 i = get_float_exception_flags(&env->vfp.fp_status); 67 i |= get_float_exception_flags(&env->vfp.standard_fp_status); 68 /* FZ16 does not generate an input denormal exception. */ 69 i |= (get_float_exception_flags(&env->vfp.fp_status_f16) 70 & ~float_flag_input_denormal); 71 i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16) 72 & ~float_flag_input_denormal); 73 return vfp_exceptbits_from_host(i); 74 } 75 76 static void vfp_clear_float_status_exc_flags(CPUARMState *env) 77 { 78 /* 79 * Clear out all the exception-flag information in the float_status 80 * values. The caller should have arranged for env->vfp.fpsr to 81 * be the architecturally up-to-date exception flag information first. 82 */ 83 set_float_exception_flags(0, &env->vfp.fp_status); 84 set_float_exception_flags(0, &env->vfp.fp_status_f16); 85 set_float_exception_flags(0, &env->vfp.standard_fp_status); 86 set_float_exception_flags(0, &env->vfp.standard_fp_status_f16); 87 } 88 89 static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) 90 { 91 uint64_t changed = env->vfp.fpcr; 92 93 changed ^= val; 94 changed &= mask; 95 if (changed & (3 << 22)) { 96 int i = (val >> 22) & 3; 97 switch (i) { 98 case FPROUNDING_TIEEVEN: 99 i = float_round_nearest_even; 100 break; 101 case FPROUNDING_POSINF: 102 i = float_round_up; 103 break; 104 case FPROUNDING_NEGINF: 105 i = float_round_down; 106 break; 107 case FPROUNDING_ZERO: 108 i = float_round_to_zero; 109 break; 110 } 111 set_float_rounding_mode(i, &env->vfp.fp_status); 112 set_float_rounding_mode(i, &env->vfp.fp_status_f16); 113 } 114 if (changed & FPCR_FZ16) { 115 bool ftz_enabled = val & FPCR_FZ16; 116 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); 117 set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); 118 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); 119 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); 120 } 121 if (changed & FPCR_FZ) { 122 bool ftz_enabled = val & FPCR_FZ; 123 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); 124 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); 125 } 126 if (changed & FPCR_DN) { 127 bool dnan_enabled = val & FPCR_DN; 128 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); 129 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); 130 } 131 } 132 133 #else 134 135 static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) 136 { 137 return 0; 138 } 139 140 static void vfp_clear_float_status_exc_flags(CPUARMState *env) 141 { 142 } 143 144 static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) 145 { 146 } 147 148 #endif 149 150 uint32_t vfp_get_fpcr(CPUARMState *env) 151 { 152 uint32_t fpcr = env->vfp.fpcr 153 | (env->vfp.vec_len << 16) 154 | (env->vfp.vec_stride << 20); 155 156 /* 157 * M-profile LTPSIZE is the same bits [18:16] as A-profile Len; whichever 158 * of the two is not applicable to this CPU will always be zero. 159 */ 160 fpcr |= env->v7m.ltpsize << 16; 161 162 return fpcr; 163 } 164 165 uint32_t vfp_get_fpsr(CPUARMState *env) 166 { 167 uint32_t fpsr = env->vfp.fpsr; 168 uint32_t i; 169 170 fpsr |= vfp_get_fpsr_from_host(env); 171 172 i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3]; 173 fpsr |= i ? FPSR_QC : 0; 174 return fpsr; 175 } 176 177 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) 178 { 179 return (vfp_get_fpcr(env) & FPSCR_FPCR_MASK) | 180 (vfp_get_fpsr(env) & FPSCR_FPSR_MASK); 181 } 182 183 uint32_t vfp_get_fpscr(CPUARMState *env) 184 { 185 return HELPER(vfp_get_fpscr)(env); 186 } 187 188 void vfp_set_fpsr(CPUARMState *env, uint32_t val) 189 { 190 ARMCPU *cpu = env_archcpu(env); 191 192 if (arm_feature(env, ARM_FEATURE_NEON) || 193 cpu_isar_feature(aa32_mve, cpu)) { 194 /* 195 * The bit we set within vfp.qc[] is arbitrary; the array as a 196 * whole being zero/non-zero is what counts. 197 */ 198 env->vfp.qc[0] = val & FPSR_QC; 199 env->vfp.qc[1] = 0; 200 env->vfp.qc[2] = 0; 201 env->vfp.qc[3] = 0; 202 } 203 204 /* 205 * NZCV lives only in env->vfp.fpsr. The cumulative exception flags 206 * IOC|DZC|OFC|UFC|IXC|IDC also live in env->vfp.fpsr, with possible 207 * extra pending exception information that hasn't yet been folded in 208 * living in the float_status values (for TCG). 209 * Since this FPSR write gives us the up to date values of the exception 210 * flags, we want to store into vfp.fpsr the NZCV and CEXC bits, zeroing 211 * anything else. We also need to clear out the float_status exception 212 * information so that the next vfp_get_fpsr does not fold in stale data. 213 */ 214 val &= FPSR_NZCV_MASK | FPSR_CEXC_MASK; 215 env->vfp.fpsr = val; 216 vfp_clear_float_status_exc_flags(env); 217 } 218 219 static void vfp_set_fpcr_masked(CPUARMState *env, uint32_t val, uint32_t mask) 220 { 221 /* 222 * We only set FPCR bits defined by mask, and leave the others alone. 223 * We assume the mask is sensible (e.g. doesn't try to set only 224 * part of a field) 225 */ 226 ARMCPU *cpu = env_archcpu(env); 227 228 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ 229 if (!cpu_isar_feature(any_fp16, cpu)) { 230 val &= ~FPCR_FZ16; 231 } 232 233 if (!cpu_isar_feature(aa64_ebf16, cpu)) { 234 val &= ~FPCR_EBF; 235 } 236 237 vfp_set_fpcr_to_host(env, val, mask); 238 239 if (mask & (FPCR_LEN_MASK | FPCR_STRIDE_MASK)) { 240 if (!arm_feature(env, ARM_FEATURE_M)) { 241 /* 242 * Short-vector length and stride; on M-profile these bits 243 * are used for different purposes. 244 * We can't make this conditional be "if MVFR0.FPShVec != 0", 245 * because in v7A no-short-vector-support cores still had to 246 * allow Stride/Len to be written with the only effect that 247 * some insns are required to UNDEF if the guest sets them. 248 */ 249 env->vfp.vec_len = extract32(val, 16, 3); 250 env->vfp.vec_stride = extract32(val, 20, 2); 251 } else if (cpu_isar_feature(aa32_mve, cpu)) { 252 env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT, 253 FPCR_LTPSIZE_LENGTH); 254 } 255 } 256 257 /* 258 * We don't implement trapped exception handling, so the 259 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) 260 * 261 * The FPCR bits we keep in vfp.fpcr are AHP, DN, FZ, RMode, EBF 262 * and FZ16. Len, Stride and LTPSIZE we just handled. Store those bits 263 * there, and zero any of the other FPCR bits and the RES0 and RAZ/WI 264 * bits. 265 */ 266 val &= FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16 | FPCR_EBF; 267 env->vfp.fpcr &= ~mask; 268 env->vfp.fpcr |= val; 269 } 270 271 void vfp_set_fpcr(CPUARMState *env, uint32_t val) 272 { 273 vfp_set_fpcr_masked(env, val, MAKE_64BIT_MASK(0, 32)); 274 } 275 276 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 277 { 278 vfp_set_fpcr_masked(env, val, FPSCR_FPCR_MASK); 279 vfp_set_fpsr(env, val & FPSCR_FPSR_MASK); 280 } 281 282 void vfp_set_fpscr(CPUARMState *env, uint32_t val) 283 { 284 HELPER(vfp_set_fpscr)(env, val); 285 } 286 287 #ifdef CONFIG_TCG 288 289 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) 290 291 #define VFP_BINOP(name) \ 292 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \ 293 { \ 294 float_status *fpst = fpstp; \ 295 return float16_ ## name(a, b, fpst); \ 296 } \ 297 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ 298 { \ 299 float_status *fpst = fpstp; \ 300 return float32_ ## name(a, b, fpst); \ 301 } \ 302 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ 303 { \ 304 float_status *fpst = fpstp; \ 305 return float64_ ## name(a, b, fpst); \ 306 } 307 VFP_BINOP(add) 308 VFP_BINOP(sub) 309 VFP_BINOP(mul) 310 VFP_BINOP(div) 311 VFP_BINOP(min) 312 VFP_BINOP(max) 313 VFP_BINOP(minnum) 314 VFP_BINOP(maxnum) 315 #undef VFP_BINOP 316 317 dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env) 318 { 319 return float16_sqrt(a, &env->vfp.fp_status_f16); 320 } 321 322 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) 323 { 324 return float32_sqrt(a, &env->vfp.fp_status); 325 } 326 327 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) 328 { 329 return float64_sqrt(a, &env->vfp.fp_status); 330 } 331 332 static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp) 333 { 334 uint32_t flags; 335 switch (cmp) { 336 case float_relation_equal: 337 flags = 0x6; 338 break; 339 case float_relation_less: 340 flags = 0x8; 341 break; 342 case float_relation_greater: 343 flags = 0x2; 344 break; 345 case float_relation_unordered: 346 flags = 0x3; 347 break; 348 default: 349 g_assert_not_reached(); 350 } 351 env->vfp.fpsr = deposit64(env->vfp.fpsr, 28, 4, flags); /* NZCV */ 352 } 353 354 /* XXX: check quiet/signaling case */ 355 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \ 356 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ 357 { \ 358 softfloat_to_vfp_compare(env, \ 359 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \ 360 } \ 361 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ 362 { \ 363 softfloat_to_vfp_compare(env, \ 364 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \ 365 } 366 DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16) 367 DO_VFP_cmp(s, float32, float32, fp_status) 368 DO_VFP_cmp(d, float64, float64, fp_status) 369 #undef DO_VFP_cmp 370 371 /* Integer to float and float to integer conversions */ 372 373 #define CONV_ITOF(name, ftype, fsz, sign) \ 374 ftype HELPER(name)(uint32_t x, void *fpstp) \ 375 { \ 376 float_status *fpst = fpstp; \ 377 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ 378 } 379 380 #define CONV_FTOI(name, ftype, fsz, sign, round) \ 381 sign##int32_t HELPER(name)(ftype x, void *fpstp) \ 382 { \ 383 float_status *fpst = fpstp; \ 384 if (float##fsz##_is_any_nan(x)) { \ 385 float_raise(float_flag_invalid, fpst); \ 386 return 0; \ 387 } \ 388 return float##fsz##_to_##sign##int32##round(x, fpst); \ 389 } 390 391 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \ 392 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \ 393 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \ 394 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero) 395 396 FLOAT_CONVS(si, h, uint32_t, 16, ) 397 FLOAT_CONVS(si, s, float32, 32, ) 398 FLOAT_CONVS(si, d, float64, 64, ) 399 FLOAT_CONVS(ui, h, uint32_t, 16, u) 400 FLOAT_CONVS(ui, s, float32, 32, u) 401 FLOAT_CONVS(ui, d, float64, 64, u) 402 403 #undef CONV_ITOF 404 #undef CONV_FTOI 405 #undef FLOAT_CONVS 406 407 /* floating point conversion */ 408 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) 409 { 410 return float32_to_float64(x, &env->vfp.fp_status); 411 } 412 413 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) 414 { 415 return float64_to_float32(x, &env->vfp.fp_status); 416 } 417 418 uint32_t HELPER(bfcvt)(float32 x, void *status) 419 { 420 return float32_to_bfloat16(x, status); 421 } 422 423 uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status) 424 { 425 bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status); 426 bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status); 427 return deposit32(lo, 16, 16, hi); 428 } 429 430 /* 431 * VFP3 fixed point conversion. The AArch32 versions of fix-to-float 432 * must always round-to-nearest; the AArch64 ones honour the FPSCR 433 * rounding mode. (For AArch32 Neon the standard-FPSCR is set to 434 * round-to-nearest so either helper will work.) AArch32 float-to-fix 435 * must round-to-zero. 436 */ 437 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 438 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ 439 void *fpstp) \ 440 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); } 441 442 #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \ 443 ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \ 444 uint32_t shift, \ 445 void *fpstp) \ 446 { \ 447 ftype ret; \ 448 float_status *fpst = fpstp; \ 449 FloatRoundMode oldmode = fpst->float_rounding_mode; \ 450 fpst->float_rounding_mode = float_round_nearest_even; \ 451 ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \ 452 fpst->float_rounding_mode = oldmode; \ 453 return ret; \ 454 } 455 456 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \ 457 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \ 458 void *fpst) \ 459 { \ 460 if (unlikely(float##fsz##_is_any_nan(x))) { \ 461 float_raise(float_flag_invalid, fpst); \ 462 return 0; \ 463 } \ 464 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \ 465 } 466 467 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \ 468 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 469 VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \ 470 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 471 float_round_to_zero, _round_to_zero) \ 472 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 473 get_float_rounding_mode(fpst), ) 474 475 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \ 476 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 477 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 478 get_float_rounding_mode(fpst), ) 479 480 VFP_CONV_FIX(sh, d, 64, float64, 64, int16) 481 VFP_CONV_FIX(sl, d, 64, float64, 64, int32) 482 VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64) 483 VFP_CONV_FIX(uh, d, 64, float64, 64, uint16) 484 VFP_CONV_FIX(ul, d, 64, float64, 64, uint32) 485 VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64) 486 VFP_CONV_FIX(sh, s, 32, float32, 32, int16) 487 VFP_CONV_FIX(sl, s, 32, float32, 32, int32) 488 VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64) 489 VFP_CONV_FIX(uh, s, 32, float32, 32, uint16) 490 VFP_CONV_FIX(ul, s, 32, float32, 32, uint32) 491 VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64) 492 VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16) 493 VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32) 494 VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64) 495 VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16) 496 VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32) 497 VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64) 498 499 #undef VFP_CONV_FIX 500 #undef VFP_CONV_FIX_FLOAT 501 #undef VFP_CONV_FLOAT_FIX_ROUND 502 #undef VFP_CONV_FIX_A64 503 504 /* Set the current fp rounding mode and return the old one. 505 * The argument is a softfloat float_round_ value. 506 */ 507 uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) 508 { 509 float_status *fp_status = fpstp; 510 511 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 512 set_float_rounding_mode(rmode, fp_status); 513 514 return prev_rmode; 515 } 516 517 /* Half precision conversions. */ 518 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode) 519 { 520 /* Squash FZ16 to 0 for the duration of conversion. In this case, 521 * it would affect flushing input denormals. 522 */ 523 float_status *fpst = fpstp; 524 bool save = get_flush_inputs_to_zero(fpst); 525 set_flush_inputs_to_zero(false, fpst); 526 float32 r = float16_to_float32(a, !ahp_mode, fpst); 527 set_flush_inputs_to_zero(save, fpst); 528 return r; 529 } 530 531 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) 532 { 533 /* Squash FZ16 to 0 for the duration of conversion. In this case, 534 * it would affect flushing output denormals. 535 */ 536 float_status *fpst = fpstp; 537 bool save = get_flush_to_zero(fpst); 538 set_flush_to_zero(false, fpst); 539 float16 r = float32_to_float16(a, !ahp_mode, fpst); 540 set_flush_to_zero(save, fpst); 541 return r; 542 } 543 544 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode) 545 { 546 /* Squash FZ16 to 0 for the duration of conversion. In this case, 547 * it would affect flushing input denormals. 548 */ 549 float_status *fpst = fpstp; 550 bool save = get_flush_inputs_to_zero(fpst); 551 set_flush_inputs_to_zero(false, fpst); 552 float64 r = float16_to_float64(a, !ahp_mode, fpst); 553 set_flush_inputs_to_zero(save, fpst); 554 return r; 555 } 556 557 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) 558 { 559 /* Squash FZ16 to 0 for the duration of conversion. In this case, 560 * it would affect flushing output denormals. 561 */ 562 float_status *fpst = fpstp; 563 bool save = get_flush_to_zero(fpst); 564 set_flush_to_zero(false, fpst); 565 float16 r = float64_to_float16(a, !ahp_mode, fpst); 566 set_flush_to_zero(save, fpst); 567 return r; 568 } 569 570 /* NEON helpers. */ 571 572 /* Constants 256 and 512 are used in some helpers; we avoid relying on 573 * int->float conversions at run-time. */ 574 #define float64_256 make_float64(0x4070000000000000LL) 575 #define float64_512 make_float64(0x4080000000000000LL) 576 #define float16_maxnorm make_float16(0x7bff) 577 #define float32_maxnorm make_float32(0x7f7fffff) 578 #define float64_maxnorm make_float64(0x7fefffffffffffffLL) 579 580 /* Reciprocal functions 581 * 582 * The algorithm that must be used to calculate the estimate 583 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate 584 */ 585 586 /* See RecipEstimate() 587 * 588 * input is a 9 bit fixed point number 589 * input range 256 .. 511 for a number from 0.5 <= x < 1.0. 590 * result range 256 .. 511 for a number from 1.0 to 511/256. 591 */ 592 593 static int recip_estimate(int input) 594 { 595 int a, b, r; 596 assert(256 <= input && input < 512); 597 a = (input * 2) + 1; 598 b = (1 << 19) / a; 599 r = (b + 1) >> 1; 600 assert(256 <= r && r < 512); 601 return r; 602 } 603 604 /* 605 * Common wrapper to call recip_estimate 606 * 607 * The parameters are exponent and 64 bit fraction (without implicit 608 * bit) where the binary point is nominally at bit 52. Returns a 609 * float64 which can then be rounded to the appropriate size by the 610 * callee. 611 */ 612 613 static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac) 614 { 615 uint32_t scaled, estimate; 616 uint64_t result_frac; 617 int result_exp; 618 619 /* Handle sub-normals */ 620 if (*exp == 0) { 621 if (extract64(frac, 51, 1) == 0) { 622 *exp = -1; 623 frac <<= 2; 624 } else { 625 frac <<= 1; 626 } 627 } 628 629 /* scaled = UInt('1':fraction<51:44>) */ 630 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); 631 estimate = recip_estimate(scaled); 632 633 result_exp = exp_off - *exp; 634 result_frac = deposit64(0, 44, 8, estimate); 635 if (result_exp == 0) { 636 result_frac = deposit64(result_frac >> 1, 51, 1, 1); 637 } else if (result_exp == -1) { 638 result_frac = deposit64(result_frac >> 2, 50, 2, 1); 639 result_exp = 0; 640 } 641 642 *exp = result_exp; 643 644 return result_frac; 645 } 646 647 static bool round_to_inf(float_status *fpst, bool sign_bit) 648 { 649 switch (fpst->float_rounding_mode) { 650 case float_round_nearest_even: /* Round to Nearest */ 651 return true; 652 case float_round_up: /* Round to +Inf */ 653 return !sign_bit; 654 case float_round_down: /* Round to -Inf */ 655 return sign_bit; 656 case float_round_to_zero: /* Round to Zero */ 657 return false; 658 default: 659 g_assert_not_reached(); 660 } 661 } 662 663 uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) 664 { 665 float_status *fpst = fpstp; 666 float16 f16 = float16_squash_input_denormal(input, fpst); 667 uint32_t f16_val = float16_val(f16); 668 uint32_t f16_sign = float16_is_neg(f16); 669 int f16_exp = extract32(f16_val, 10, 5); 670 uint32_t f16_frac = extract32(f16_val, 0, 10); 671 uint64_t f64_frac; 672 673 if (float16_is_any_nan(f16)) { 674 float16 nan = f16; 675 if (float16_is_signaling_nan(f16, fpst)) { 676 float_raise(float_flag_invalid, fpst); 677 if (!fpst->default_nan_mode) { 678 nan = float16_silence_nan(f16, fpst); 679 } 680 } 681 if (fpst->default_nan_mode) { 682 nan = float16_default_nan(fpst); 683 } 684 return nan; 685 } else if (float16_is_infinity(f16)) { 686 return float16_set_sign(float16_zero, float16_is_neg(f16)); 687 } else if (float16_is_zero(f16)) { 688 float_raise(float_flag_divbyzero, fpst); 689 return float16_set_sign(float16_infinity, float16_is_neg(f16)); 690 } else if (float16_abs(f16) < (1 << 8)) { 691 /* Abs(value) < 2.0^-16 */ 692 float_raise(float_flag_overflow | float_flag_inexact, fpst); 693 if (round_to_inf(fpst, f16_sign)) { 694 return float16_set_sign(float16_infinity, f16_sign); 695 } else { 696 return float16_set_sign(float16_maxnorm, f16_sign); 697 } 698 } else if (f16_exp >= 29 && fpst->flush_to_zero) { 699 float_raise(float_flag_underflow, fpst); 700 return float16_set_sign(float16_zero, float16_is_neg(f16)); 701 } 702 703 f64_frac = call_recip_estimate(&f16_exp, 29, 704 ((uint64_t) f16_frac) << (52 - 10)); 705 706 /* result = sign : result_exp<4:0> : fraction<51:42> */ 707 f16_val = deposit32(0, 15, 1, f16_sign); 708 f16_val = deposit32(f16_val, 10, 5, f16_exp); 709 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10)); 710 return make_float16(f16_val); 711 } 712 713 float32 HELPER(recpe_f32)(float32 input, void *fpstp) 714 { 715 float_status *fpst = fpstp; 716 float32 f32 = float32_squash_input_denormal(input, fpst); 717 uint32_t f32_val = float32_val(f32); 718 bool f32_sign = float32_is_neg(f32); 719 int f32_exp = extract32(f32_val, 23, 8); 720 uint32_t f32_frac = extract32(f32_val, 0, 23); 721 uint64_t f64_frac; 722 723 if (float32_is_any_nan(f32)) { 724 float32 nan = f32; 725 if (float32_is_signaling_nan(f32, fpst)) { 726 float_raise(float_flag_invalid, fpst); 727 if (!fpst->default_nan_mode) { 728 nan = float32_silence_nan(f32, fpst); 729 } 730 } 731 if (fpst->default_nan_mode) { 732 nan = float32_default_nan(fpst); 733 } 734 return nan; 735 } else if (float32_is_infinity(f32)) { 736 return float32_set_sign(float32_zero, float32_is_neg(f32)); 737 } else if (float32_is_zero(f32)) { 738 float_raise(float_flag_divbyzero, fpst); 739 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 740 } else if (float32_abs(f32) < (1ULL << 21)) { 741 /* Abs(value) < 2.0^-128 */ 742 float_raise(float_flag_overflow | float_flag_inexact, fpst); 743 if (round_to_inf(fpst, f32_sign)) { 744 return float32_set_sign(float32_infinity, f32_sign); 745 } else { 746 return float32_set_sign(float32_maxnorm, f32_sign); 747 } 748 } else if (f32_exp >= 253 && fpst->flush_to_zero) { 749 float_raise(float_flag_underflow, fpst); 750 return float32_set_sign(float32_zero, float32_is_neg(f32)); 751 } 752 753 f64_frac = call_recip_estimate(&f32_exp, 253, 754 ((uint64_t) f32_frac) << (52 - 23)); 755 756 /* result = sign : result_exp<7:0> : fraction<51:29> */ 757 f32_val = deposit32(0, 31, 1, f32_sign); 758 f32_val = deposit32(f32_val, 23, 8, f32_exp); 759 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)); 760 return make_float32(f32_val); 761 } 762 763 float64 HELPER(recpe_f64)(float64 input, void *fpstp) 764 { 765 float_status *fpst = fpstp; 766 float64 f64 = float64_squash_input_denormal(input, fpst); 767 uint64_t f64_val = float64_val(f64); 768 bool f64_sign = float64_is_neg(f64); 769 int f64_exp = extract64(f64_val, 52, 11); 770 uint64_t f64_frac = extract64(f64_val, 0, 52); 771 772 /* Deal with any special cases */ 773 if (float64_is_any_nan(f64)) { 774 float64 nan = f64; 775 if (float64_is_signaling_nan(f64, fpst)) { 776 float_raise(float_flag_invalid, fpst); 777 if (!fpst->default_nan_mode) { 778 nan = float64_silence_nan(f64, fpst); 779 } 780 } 781 if (fpst->default_nan_mode) { 782 nan = float64_default_nan(fpst); 783 } 784 return nan; 785 } else if (float64_is_infinity(f64)) { 786 return float64_set_sign(float64_zero, float64_is_neg(f64)); 787 } else if (float64_is_zero(f64)) { 788 float_raise(float_flag_divbyzero, fpst); 789 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 790 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { 791 /* Abs(value) < 2.0^-1024 */ 792 float_raise(float_flag_overflow | float_flag_inexact, fpst); 793 if (round_to_inf(fpst, f64_sign)) { 794 return float64_set_sign(float64_infinity, f64_sign); 795 } else { 796 return float64_set_sign(float64_maxnorm, f64_sign); 797 } 798 } else if (f64_exp >= 2045 && fpst->flush_to_zero) { 799 float_raise(float_flag_underflow, fpst); 800 return float64_set_sign(float64_zero, float64_is_neg(f64)); 801 } 802 803 f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac); 804 805 /* result = sign : result_exp<10:0> : fraction<51:0>; */ 806 f64_val = deposit64(0, 63, 1, f64_sign); 807 f64_val = deposit64(f64_val, 52, 11, f64_exp); 808 f64_val = deposit64(f64_val, 0, 52, f64_frac); 809 return make_float64(f64_val); 810 } 811 812 /* The algorithm that must be used to calculate the estimate 813 * is specified by the ARM ARM. 814 */ 815 816 static int do_recip_sqrt_estimate(int a) 817 { 818 int b, estimate; 819 820 assert(128 <= a && a < 512); 821 if (a < 256) { 822 a = a * 2 + 1; 823 } else { 824 a = (a >> 1) << 1; 825 a = (a + 1) * 2; 826 } 827 b = 512; 828 while (a * (b + 1) * (b + 1) < (1 << 28)) { 829 b += 1; 830 } 831 estimate = (b + 1) / 2; 832 assert(256 <= estimate && estimate < 512); 833 834 return estimate; 835 } 836 837 838 static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac) 839 { 840 int estimate; 841 uint32_t scaled; 842 843 if (*exp == 0) { 844 while (extract64(frac, 51, 1) == 0) { 845 frac = frac << 1; 846 *exp -= 1; 847 } 848 frac = extract64(frac, 0, 51) << 1; 849 } 850 851 if (*exp & 1) { 852 /* scaled = UInt('01':fraction<51:45>) */ 853 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); 854 } else { 855 /* scaled = UInt('1':fraction<51:44>) */ 856 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); 857 } 858 estimate = do_recip_sqrt_estimate(scaled); 859 860 *exp = (exp_off - *exp) / 2; 861 return extract64(estimate, 0, 8) << 44; 862 } 863 864 uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) 865 { 866 float_status *s = fpstp; 867 float16 f16 = float16_squash_input_denormal(input, s); 868 uint16_t val = float16_val(f16); 869 bool f16_sign = float16_is_neg(f16); 870 int f16_exp = extract32(val, 10, 5); 871 uint16_t f16_frac = extract32(val, 0, 10); 872 uint64_t f64_frac; 873 874 if (float16_is_any_nan(f16)) { 875 float16 nan = f16; 876 if (float16_is_signaling_nan(f16, s)) { 877 float_raise(float_flag_invalid, s); 878 if (!s->default_nan_mode) { 879 nan = float16_silence_nan(f16, fpstp); 880 } 881 } 882 if (s->default_nan_mode) { 883 nan = float16_default_nan(s); 884 } 885 return nan; 886 } else if (float16_is_zero(f16)) { 887 float_raise(float_flag_divbyzero, s); 888 return float16_set_sign(float16_infinity, f16_sign); 889 } else if (f16_sign) { 890 float_raise(float_flag_invalid, s); 891 return float16_default_nan(s); 892 } else if (float16_is_infinity(f16)) { 893 return float16_zero; 894 } 895 896 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 897 * preserving the parity of the exponent. */ 898 899 f64_frac = ((uint64_t) f16_frac) << (52 - 10); 900 901 f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac); 902 903 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */ 904 val = deposit32(0, 15, 1, f16_sign); 905 val = deposit32(val, 10, 5, f16_exp); 906 val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8)); 907 return make_float16(val); 908 } 909 910 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) 911 { 912 float_status *s = fpstp; 913 float32 f32 = float32_squash_input_denormal(input, s); 914 uint32_t val = float32_val(f32); 915 uint32_t f32_sign = float32_is_neg(f32); 916 int f32_exp = extract32(val, 23, 8); 917 uint32_t f32_frac = extract32(val, 0, 23); 918 uint64_t f64_frac; 919 920 if (float32_is_any_nan(f32)) { 921 float32 nan = f32; 922 if (float32_is_signaling_nan(f32, s)) { 923 float_raise(float_flag_invalid, s); 924 if (!s->default_nan_mode) { 925 nan = float32_silence_nan(f32, fpstp); 926 } 927 } 928 if (s->default_nan_mode) { 929 nan = float32_default_nan(s); 930 } 931 return nan; 932 } else if (float32_is_zero(f32)) { 933 float_raise(float_flag_divbyzero, s); 934 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 935 } else if (float32_is_neg(f32)) { 936 float_raise(float_flag_invalid, s); 937 return float32_default_nan(s); 938 } else if (float32_is_infinity(f32)) { 939 return float32_zero; 940 } 941 942 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 943 * preserving the parity of the exponent. */ 944 945 f64_frac = ((uint64_t) f32_frac) << 29; 946 947 f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac); 948 949 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */ 950 val = deposit32(0, 31, 1, f32_sign); 951 val = deposit32(val, 23, 8, f32_exp); 952 val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8)); 953 return make_float32(val); 954 } 955 956 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) 957 { 958 float_status *s = fpstp; 959 float64 f64 = float64_squash_input_denormal(input, s); 960 uint64_t val = float64_val(f64); 961 bool f64_sign = float64_is_neg(f64); 962 int f64_exp = extract64(val, 52, 11); 963 uint64_t f64_frac = extract64(val, 0, 52); 964 965 if (float64_is_any_nan(f64)) { 966 float64 nan = f64; 967 if (float64_is_signaling_nan(f64, s)) { 968 float_raise(float_flag_invalid, s); 969 if (!s->default_nan_mode) { 970 nan = float64_silence_nan(f64, fpstp); 971 } 972 } 973 if (s->default_nan_mode) { 974 nan = float64_default_nan(s); 975 } 976 return nan; 977 } else if (float64_is_zero(f64)) { 978 float_raise(float_flag_divbyzero, s); 979 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 980 } else if (float64_is_neg(f64)) { 981 float_raise(float_flag_invalid, s); 982 return float64_default_nan(s); 983 } else if (float64_is_infinity(f64)) { 984 return float64_zero; 985 } 986 987 f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac); 988 989 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */ 990 val = deposit64(0, 61, 1, f64_sign); 991 val = deposit64(val, 52, 11, f64_exp); 992 val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8)); 993 return make_float64(val); 994 } 995 996 uint32_t HELPER(recpe_u32)(uint32_t a) 997 { 998 int input, estimate; 999 1000 if ((a & 0x80000000) == 0) { 1001 return 0xffffffff; 1002 } 1003 1004 input = extract32(a, 23, 9); 1005 estimate = recip_estimate(input); 1006 1007 return deposit32(0, (32 - 9), 9, estimate); 1008 } 1009 1010 uint32_t HELPER(rsqrte_u32)(uint32_t a) 1011 { 1012 int estimate; 1013 1014 if ((a & 0xc0000000) == 0) { 1015 return 0xffffffff; 1016 } 1017 1018 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9)); 1019 1020 return deposit32(0, 23, 9, estimate); 1021 } 1022 1023 /* VFPv4 fused multiply-accumulate */ 1024 dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b, 1025 dh_ctype_f16 c, void *fpstp) 1026 { 1027 float_status *fpst = fpstp; 1028 return float16_muladd(a, b, c, 0, fpst); 1029 } 1030 1031 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) 1032 { 1033 float_status *fpst = fpstp; 1034 return float32_muladd(a, b, c, 0, fpst); 1035 } 1036 1037 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) 1038 { 1039 float_status *fpst = fpstp; 1040 return float64_muladd(a, b, c, 0, fpst); 1041 } 1042 1043 /* ARMv8 round to integral */ 1044 dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status) 1045 { 1046 return float16_round_to_int(x, fp_status); 1047 } 1048 1049 float32 HELPER(rints_exact)(float32 x, void *fp_status) 1050 { 1051 return float32_round_to_int(x, fp_status); 1052 } 1053 1054 float64 HELPER(rintd_exact)(float64 x, void *fp_status) 1055 { 1056 return float64_round_to_int(x, fp_status); 1057 } 1058 1059 dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status) 1060 { 1061 int old_flags = get_float_exception_flags(fp_status), new_flags; 1062 float16 ret; 1063 1064 ret = float16_round_to_int(x, fp_status); 1065 1066 /* Suppress any inexact exceptions the conversion produced */ 1067 if (!(old_flags & float_flag_inexact)) { 1068 new_flags = get_float_exception_flags(fp_status); 1069 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1070 } 1071 1072 return ret; 1073 } 1074 1075 float32 HELPER(rints)(float32 x, void *fp_status) 1076 { 1077 int old_flags = get_float_exception_flags(fp_status), new_flags; 1078 float32 ret; 1079 1080 ret = float32_round_to_int(x, fp_status); 1081 1082 /* Suppress any inexact exceptions the conversion produced */ 1083 if (!(old_flags & float_flag_inexact)) { 1084 new_flags = get_float_exception_flags(fp_status); 1085 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1086 } 1087 1088 return ret; 1089 } 1090 1091 float64 HELPER(rintd)(float64 x, void *fp_status) 1092 { 1093 int old_flags = get_float_exception_flags(fp_status), new_flags; 1094 float64 ret; 1095 1096 ret = float64_round_to_int(x, fp_status); 1097 1098 new_flags = get_float_exception_flags(fp_status); 1099 1100 /* Suppress any inexact exceptions the conversion produced */ 1101 if (!(old_flags & float_flag_inexact)) { 1102 new_flags = get_float_exception_flags(fp_status); 1103 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1104 } 1105 1106 return ret; 1107 } 1108 1109 /* Convert ARM rounding mode to softfloat */ 1110 const FloatRoundMode arm_rmode_to_sf_map[] = { 1111 [FPROUNDING_TIEEVEN] = float_round_nearest_even, 1112 [FPROUNDING_POSINF] = float_round_up, 1113 [FPROUNDING_NEGINF] = float_round_down, 1114 [FPROUNDING_ZERO] = float_round_to_zero, 1115 [FPROUNDING_TIEAWAY] = float_round_ties_away, 1116 [FPROUNDING_ODD] = float_round_to_odd, 1117 }; 1118 1119 /* 1120 * Implement float64 to int32_t conversion without saturation; 1121 * the result is supplied modulo 2^32. 1122 */ 1123 uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) 1124 { 1125 float_status *status = vstatus; 1126 uint32_t frac, e_old, e_new; 1127 bool inexact; 1128 1129 e_old = get_float_exception_flags(status); 1130 set_float_exception_flags(0, status); 1131 frac = float64_to_int32_modulo(value, float_round_to_zero, status); 1132 e_new = get_float_exception_flags(status); 1133 set_float_exception_flags(e_old | e_new, status); 1134 1135 /* Normal inexact, denormal with flush-to-zero, or overflow or NaN */ 1136 inexact = e_new & (float_flag_inexact | 1137 float_flag_input_denormal | 1138 float_flag_invalid); 1139 1140 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ 1141 inexact |= value == float64_chs(float64_zero); 1142 1143 /* Pack the result and the env->ZF representation of Z together. */ 1144 return deposit64(frac, 32, 32, inexact); 1145 } 1146 1147 uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) 1148 { 1149 uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status); 1150 uint32_t result = pair; 1151 uint32_t z = (pair >> 32) == 0; 1152 1153 /* Store Z, clear NCV, in FPSCR.NZCV. */ 1154 env->vfp.fpsr = (env->vfp.fpsr & ~FPSR_NZCV_MASK) | (z * FPSR_Z); 1155 1156 return result; 1157 } 1158 1159 /* Round a float32 to an integer that fits in int32_t or int64_t. */ 1160 static float32 frint_s(float32 f, float_status *fpst, int intsize) 1161 { 1162 int old_flags = get_float_exception_flags(fpst); 1163 uint32_t exp = extract32(f, 23, 8); 1164 1165 if (unlikely(exp == 0xff)) { 1166 /* NaN or Inf. */ 1167 goto overflow; 1168 } 1169 1170 /* Round and re-extract the exponent. */ 1171 f = float32_round_to_int(f, fpst); 1172 exp = extract32(f, 23, 8); 1173 1174 /* Validate the range of the result. */ 1175 if (exp < 126 + intsize) { 1176 /* abs(F) <= INT{N}_MAX */ 1177 return f; 1178 } 1179 if (exp == 126 + intsize) { 1180 uint32_t sign = extract32(f, 31, 1); 1181 uint32_t frac = extract32(f, 0, 23); 1182 if (sign && frac == 0) { 1183 /* F == INT{N}_MIN */ 1184 return f; 1185 } 1186 } 1187 1188 overflow: 1189 /* 1190 * Raise Invalid and return INT{N}_MIN as a float. Revert any 1191 * inexact exception float32_round_to_int may have raised. 1192 */ 1193 set_float_exception_flags(old_flags | float_flag_invalid, fpst); 1194 return (0x100u + 126u + intsize) << 23; 1195 } 1196 1197 float32 HELPER(frint32_s)(float32 f, void *fpst) 1198 { 1199 return frint_s(f, fpst, 32); 1200 } 1201 1202 float32 HELPER(frint64_s)(float32 f, void *fpst) 1203 { 1204 return frint_s(f, fpst, 64); 1205 } 1206 1207 /* Round a float64 to an integer that fits in int32_t or int64_t. */ 1208 static float64 frint_d(float64 f, float_status *fpst, int intsize) 1209 { 1210 int old_flags = get_float_exception_flags(fpst); 1211 uint32_t exp = extract64(f, 52, 11); 1212 1213 if (unlikely(exp == 0x7ff)) { 1214 /* NaN or Inf. */ 1215 goto overflow; 1216 } 1217 1218 /* Round and re-extract the exponent. */ 1219 f = float64_round_to_int(f, fpst); 1220 exp = extract64(f, 52, 11); 1221 1222 /* Validate the range of the result. */ 1223 if (exp < 1022 + intsize) { 1224 /* abs(F) <= INT{N}_MAX */ 1225 return f; 1226 } 1227 if (exp == 1022 + intsize) { 1228 uint64_t sign = extract64(f, 63, 1); 1229 uint64_t frac = extract64(f, 0, 52); 1230 if (sign && frac == 0) { 1231 /* F == INT{N}_MIN */ 1232 return f; 1233 } 1234 } 1235 1236 overflow: 1237 /* 1238 * Raise Invalid and return INT{N}_MIN as a float. Revert any 1239 * inexact exception float64_round_to_int may have raised. 1240 */ 1241 set_float_exception_flags(old_flags | float_flag_invalid, fpst); 1242 return (uint64_t)(0x800 + 1022 + intsize) << 52; 1243 } 1244 1245 float64 HELPER(frint32_d)(float64 f, void *fpst) 1246 { 1247 return frint_d(f, fpst, 32); 1248 } 1249 1250 float64 HELPER(frint64_d)(float64 f, void *fpst) 1251 { 1252 return frint_d(f, fpst, 64); 1253 } 1254 1255 void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg) 1256 { 1257 uint32_t syndrome; 1258 1259 switch (reg) { 1260 case ARM_VFP_MVFR0: 1261 case ARM_VFP_MVFR1: 1262 case ARM_VFP_MVFR2: 1263 if (!(arm_hcr_el2_eff(env) & HCR_TID3)) { 1264 return; 1265 } 1266 break; 1267 case ARM_VFP_FPSID: 1268 if (!(arm_hcr_el2_eff(env) & HCR_TID0)) { 1269 return; 1270 } 1271 break; 1272 default: 1273 g_assert_not_reached(); 1274 } 1275 1276 syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT) 1277 | ARM_EL_IL 1278 | (1 << 24) | (0xe << 20) | (7 << 14) 1279 | (reg << 10) | (rt << 5) | 1); 1280 1281 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); 1282 } 1283 1284 #endif 1285