1 /* 2 * ARM VFP floating-point operations 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "internals.h" 24 #include "cpu-features.h" 25 #ifdef CONFIG_TCG 26 #include "qemu/log.h" 27 #include "fpu/softfloat.h" 28 #endif 29 30 /* VFP support. We follow the convention used for VFP instructions: 31 Single precision routines have a "s" suffix, double precision a 32 "d" suffix. */ 33 34 #ifdef CONFIG_TCG 35 36 /* Convert host exception flags to vfp form. */ 37 static inline int vfp_exceptbits_from_host(int host_bits) 38 { 39 int target_bits = 0; 40 41 if (host_bits & float_flag_invalid) { 42 target_bits |= 1; 43 } 44 if (host_bits & float_flag_divbyzero) { 45 target_bits |= 2; 46 } 47 if (host_bits & float_flag_overflow) { 48 target_bits |= 4; 49 } 50 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { 51 target_bits |= 8; 52 } 53 if (host_bits & float_flag_inexact) { 54 target_bits |= 0x10; 55 } 56 if (host_bits & float_flag_input_denormal) { 57 target_bits |= 0x80; 58 } 59 return target_bits; 60 } 61 62 static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) 63 { 64 uint32_t i; 65 66 i = get_float_exception_flags(&env->vfp.fp_status); 67 i |= get_float_exception_flags(&env->vfp.standard_fp_status); 68 /* FZ16 does not generate an input denormal exception. */ 69 i |= (get_float_exception_flags(&env->vfp.fp_status_f16) 70 & ~float_flag_input_denormal); 71 i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16) 72 & ~float_flag_input_denormal); 73 return vfp_exceptbits_from_host(i); 74 } 75 76 static void vfp_clear_float_status_exc_flags(CPUARMState *env) 77 { 78 /* 79 * Clear out all the exception-flag information in the float_status 80 * values. The caller should have arranged for env->vfp.fpsr to 81 * be the architecturally up-to-date exception flag information first. 82 */ 83 set_float_exception_flags(0, &env->vfp.fp_status); 84 set_float_exception_flags(0, &env->vfp.fp_status_f16); 85 set_float_exception_flags(0, &env->vfp.standard_fp_status); 86 set_float_exception_flags(0, &env->vfp.standard_fp_status_f16); 87 } 88 89 static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) 90 { 91 uint64_t changed = env->vfp.fpcr; 92 93 changed ^= val; 94 changed &= mask; 95 if (changed & (3 << 22)) { 96 int i = (val >> 22) & 3; 97 switch (i) { 98 case FPROUNDING_TIEEVEN: 99 i = float_round_nearest_even; 100 break; 101 case FPROUNDING_POSINF: 102 i = float_round_up; 103 break; 104 case FPROUNDING_NEGINF: 105 i = float_round_down; 106 break; 107 case FPROUNDING_ZERO: 108 i = float_round_to_zero; 109 break; 110 } 111 set_float_rounding_mode(i, &env->vfp.fp_status); 112 set_float_rounding_mode(i, &env->vfp.fp_status_f16); 113 } 114 if (changed & FPCR_FZ16) { 115 bool ftz_enabled = val & FPCR_FZ16; 116 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); 117 set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); 118 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); 119 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); 120 } 121 if (changed & FPCR_FZ) { 122 bool ftz_enabled = val & FPCR_FZ; 123 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); 124 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); 125 } 126 if (changed & FPCR_DN) { 127 bool dnan_enabled = val & FPCR_DN; 128 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); 129 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); 130 } 131 } 132 133 #else 134 135 static uint32_t vfp_get_fpsr_from_host(CPUARMState *env) 136 { 137 return 0; 138 } 139 140 static void vfp_clear_float_status_exc_flags(CPUARMState *env) 141 { 142 } 143 144 static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) 145 { 146 } 147 148 #endif 149 150 uint32_t vfp_get_fpcr(CPUARMState *env) 151 { 152 uint32_t fpcr = env->vfp.fpcr 153 | (env->vfp.vec_len << 16) 154 | (env->vfp.vec_stride << 20); 155 156 /* 157 * M-profile LTPSIZE is the same bits [18:16] as A-profile Len; whichever 158 * of the two is not applicable to this CPU will always be zero. 159 */ 160 fpcr |= env->v7m.ltpsize << 16; 161 162 return fpcr; 163 } 164 165 uint32_t vfp_get_fpsr(CPUARMState *env) 166 { 167 uint32_t fpsr = env->vfp.fpsr; 168 uint32_t i; 169 170 fpsr |= vfp_get_fpsr_from_host(env); 171 172 i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3]; 173 fpsr |= i ? FPSR_QC : 0; 174 return fpsr; 175 } 176 177 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) 178 { 179 return (vfp_get_fpcr(env) & FPSCR_FPCR_MASK) | 180 (vfp_get_fpsr(env) & FPSCR_FPSR_MASK); 181 } 182 183 uint32_t vfp_get_fpscr(CPUARMState *env) 184 { 185 return HELPER(vfp_get_fpscr)(env); 186 } 187 188 void vfp_set_fpsr(CPUARMState *env, uint32_t val) 189 { 190 ARMCPU *cpu = env_archcpu(env); 191 192 if (arm_feature(env, ARM_FEATURE_NEON) || 193 cpu_isar_feature(aa32_mve, cpu)) { 194 /* 195 * The bit we set within vfp.qc[] is arbitrary; the array as a 196 * whole being zero/non-zero is what counts. 197 */ 198 env->vfp.qc[0] = val & FPSR_QC; 199 env->vfp.qc[1] = 0; 200 env->vfp.qc[2] = 0; 201 env->vfp.qc[3] = 0; 202 } 203 204 /* 205 * NZCV lives only in env->vfp.fpsr. The cumulative exception flags 206 * IOC|DZC|OFC|UFC|IXC|IDC also live in env->vfp.fpsr, with possible 207 * extra pending exception information that hasn't yet been folded in 208 * living in the float_status values (for TCG). 209 * Since this FPSR write gives us the up to date values of the exception 210 * flags, we want to store into vfp.fpsr the NZCV and CEXC bits, zeroing 211 * anything else. We also need to clear out the float_status exception 212 * information so that the next vfp_get_fpsr does not fold in stale data. 213 */ 214 val &= FPSR_NZCV_MASK | FPSR_CEXC_MASK; 215 env->vfp.fpsr = val; 216 vfp_clear_float_status_exc_flags(env); 217 } 218 219 static void vfp_set_fpcr_masked(CPUARMState *env, uint32_t val, uint32_t mask) 220 { 221 /* 222 * We only set FPCR bits defined by mask, and leave the others alone. 223 * We assume the mask is sensible (e.g. doesn't try to set only 224 * part of a field) 225 */ 226 ARMCPU *cpu = env_archcpu(env); 227 228 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ 229 if (!cpu_isar_feature(any_fp16, cpu)) { 230 val &= ~FPCR_FZ16; 231 } 232 233 vfp_set_fpcr_to_host(env, val, mask); 234 235 if (mask & (FPCR_LEN_MASK | FPCR_STRIDE_MASK)) { 236 if (!arm_feature(env, ARM_FEATURE_M)) { 237 /* 238 * Short-vector length and stride; on M-profile these bits 239 * are used for different purposes. 240 * We can't make this conditional be "if MVFR0.FPShVec != 0", 241 * because in v7A no-short-vector-support cores still had to 242 * allow Stride/Len to be written with the only effect that 243 * some insns are required to UNDEF if the guest sets them. 244 */ 245 env->vfp.vec_len = extract32(val, 16, 3); 246 env->vfp.vec_stride = extract32(val, 20, 2); 247 } else if (cpu_isar_feature(aa32_mve, cpu)) { 248 env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT, 249 FPCR_LTPSIZE_LENGTH); 250 } 251 } 252 253 /* 254 * We don't implement trapped exception handling, so the 255 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) 256 * 257 * The FPCR bits we keep in vfp.fpcr are AHP, DN, FZ, RMode 258 * and FZ16. Len, Stride and LTPSIZE we just handled. Store those bits 259 * there, and zero any of the other FPCR bits and the RES0 and RAZ/WI 260 * bits. 261 */ 262 val &= FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16; 263 env->vfp.fpcr &= ~mask; 264 env->vfp.fpcr |= val; 265 } 266 267 void vfp_set_fpcr(CPUARMState *env, uint32_t val) 268 { 269 vfp_set_fpcr_masked(env, val, MAKE_64BIT_MASK(0, 32)); 270 } 271 272 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 273 { 274 vfp_set_fpcr_masked(env, val, FPSCR_FPCR_MASK); 275 vfp_set_fpsr(env, val & FPSCR_FPSR_MASK); 276 } 277 278 void vfp_set_fpscr(CPUARMState *env, uint32_t val) 279 { 280 HELPER(vfp_set_fpscr)(env, val); 281 } 282 283 #ifdef CONFIG_TCG 284 285 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) 286 287 #define VFP_BINOP(name) \ 288 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \ 289 { \ 290 float_status *fpst = fpstp; \ 291 return float16_ ## name(a, b, fpst); \ 292 } \ 293 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ 294 { \ 295 float_status *fpst = fpstp; \ 296 return float32_ ## name(a, b, fpst); \ 297 } \ 298 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ 299 { \ 300 float_status *fpst = fpstp; \ 301 return float64_ ## name(a, b, fpst); \ 302 } 303 VFP_BINOP(add) 304 VFP_BINOP(sub) 305 VFP_BINOP(mul) 306 VFP_BINOP(div) 307 VFP_BINOP(min) 308 VFP_BINOP(max) 309 VFP_BINOP(minnum) 310 VFP_BINOP(maxnum) 311 #undef VFP_BINOP 312 313 dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env) 314 { 315 return float16_sqrt(a, &env->vfp.fp_status_f16); 316 } 317 318 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) 319 { 320 return float32_sqrt(a, &env->vfp.fp_status); 321 } 322 323 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) 324 { 325 return float64_sqrt(a, &env->vfp.fp_status); 326 } 327 328 static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp) 329 { 330 uint32_t flags; 331 switch (cmp) { 332 case float_relation_equal: 333 flags = 0x6; 334 break; 335 case float_relation_less: 336 flags = 0x8; 337 break; 338 case float_relation_greater: 339 flags = 0x2; 340 break; 341 case float_relation_unordered: 342 flags = 0x3; 343 break; 344 default: 345 g_assert_not_reached(); 346 } 347 env->vfp.fpsr = deposit64(env->vfp.fpsr, 28, 4, flags); /* NZCV */ 348 } 349 350 /* XXX: check quiet/signaling case */ 351 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \ 352 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ 353 { \ 354 softfloat_to_vfp_compare(env, \ 355 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \ 356 } \ 357 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ 358 { \ 359 softfloat_to_vfp_compare(env, \ 360 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \ 361 } 362 DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16) 363 DO_VFP_cmp(s, float32, float32, fp_status) 364 DO_VFP_cmp(d, float64, float64, fp_status) 365 #undef DO_VFP_cmp 366 367 /* Integer to float and float to integer conversions */ 368 369 #define CONV_ITOF(name, ftype, fsz, sign) \ 370 ftype HELPER(name)(uint32_t x, void *fpstp) \ 371 { \ 372 float_status *fpst = fpstp; \ 373 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ 374 } 375 376 #define CONV_FTOI(name, ftype, fsz, sign, round) \ 377 sign##int32_t HELPER(name)(ftype x, void *fpstp) \ 378 { \ 379 float_status *fpst = fpstp; \ 380 if (float##fsz##_is_any_nan(x)) { \ 381 float_raise(float_flag_invalid, fpst); \ 382 return 0; \ 383 } \ 384 return float##fsz##_to_##sign##int32##round(x, fpst); \ 385 } 386 387 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \ 388 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \ 389 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \ 390 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero) 391 392 FLOAT_CONVS(si, h, uint32_t, 16, ) 393 FLOAT_CONVS(si, s, float32, 32, ) 394 FLOAT_CONVS(si, d, float64, 64, ) 395 FLOAT_CONVS(ui, h, uint32_t, 16, u) 396 FLOAT_CONVS(ui, s, float32, 32, u) 397 FLOAT_CONVS(ui, d, float64, 64, u) 398 399 #undef CONV_ITOF 400 #undef CONV_FTOI 401 #undef FLOAT_CONVS 402 403 /* floating point conversion */ 404 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) 405 { 406 return float32_to_float64(x, &env->vfp.fp_status); 407 } 408 409 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) 410 { 411 return float64_to_float32(x, &env->vfp.fp_status); 412 } 413 414 uint32_t HELPER(bfcvt)(float32 x, void *status) 415 { 416 return float32_to_bfloat16(x, status); 417 } 418 419 uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status) 420 { 421 bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status); 422 bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status); 423 return deposit32(lo, 16, 16, hi); 424 } 425 426 /* 427 * VFP3 fixed point conversion. The AArch32 versions of fix-to-float 428 * must always round-to-nearest; the AArch64 ones honour the FPSCR 429 * rounding mode. (For AArch32 Neon the standard-FPSCR is set to 430 * round-to-nearest so either helper will work.) AArch32 float-to-fix 431 * must round-to-zero. 432 */ 433 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 434 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ 435 void *fpstp) \ 436 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); } 437 438 #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \ 439 ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \ 440 uint32_t shift, \ 441 void *fpstp) \ 442 { \ 443 ftype ret; \ 444 float_status *fpst = fpstp; \ 445 FloatRoundMode oldmode = fpst->float_rounding_mode; \ 446 fpst->float_rounding_mode = float_round_nearest_even; \ 447 ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \ 448 fpst->float_rounding_mode = oldmode; \ 449 return ret; \ 450 } 451 452 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \ 453 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \ 454 void *fpst) \ 455 { \ 456 if (unlikely(float##fsz##_is_any_nan(x))) { \ 457 float_raise(float_flag_invalid, fpst); \ 458 return 0; \ 459 } \ 460 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \ 461 } 462 463 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \ 464 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 465 VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \ 466 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 467 float_round_to_zero, _round_to_zero) \ 468 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 469 get_float_rounding_mode(fpst), ) 470 471 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \ 472 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 473 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 474 get_float_rounding_mode(fpst), ) 475 476 VFP_CONV_FIX(sh, d, 64, float64, 64, int16) 477 VFP_CONV_FIX(sl, d, 64, float64, 64, int32) 478 VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64) 479 VFP_CONV_FIX(uh, d, 64, float64, 64, uint16) 480 VFP_CONV_FIX(ul, d, 64, float64, 64, uint32) 481 VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64) 482 VFP_CONV_FIX(sh, s, 32, float32, 32, int16) 483 VFP_CONV_FIX(sl, s, 32, float32, 32, int32) 484 VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64) 485 VFP_CONV_FIX(uh, s, 32, float32, 32, uint16) 486 VFP_CONV_FIX(ul, s, 32, float32, 32, uint32) 487 VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64) 488 VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16) 489 VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32) 490 VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64) 491 VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16) 492 VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32) 493 VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64) 494 495 #undef VFP_CONV_FIX 496 #undef VFP_CONV_FIX_FLOAT 497 #undef VFP_CONV_FLOAT_FIX_ROUND 498 #undef VFP_CONV_FIX_A64 499 500 /* Set the current fp rounding mode and return the old one. 501 * The argument is a softfloat float_round_ value. 502 */ 503 uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) 504 { 505 float_status *fp_status = fpstp; 506 507 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 508 set_float_rounding_mode(rmode, fp_status); 509 510 return prev_rmode; 511 } 512 513 /* Half precision conversions. */ 514 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode) 515 { 516 /* Squash FZ16 to 0 for the duration of conversion. In this case, 517 * it would affect flushing input denormals. 518 */ 519 float_status *fpst = fpstp; 520 bool save = get_flush_inputs_to_zero(fpst); 521 set_flush_inputs_to_zero(false, fpst); 522 float32 r = float16_to_float32(a, !ahp_mode, fpst); 523 set_flush_inputs_to_zero(save, fpst); 524 return r; 525 } 526 527 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) 528 { 529 /* Squash FZ16 to 0 for the duration of conversion. In this case, 530 * it would affect flushing output denormals. 531 */ 532 float_status *fpst = fpstp; 533 bool save = get_flush_to_zero(fpst); 534 set_flush_to_zero(false, fpst); 535 float16 r = float32_to_float16(a, !ahp_mode, fpst); 536 set_flush_to_zero(save, fpst); 537 return r; 538 } 539 540 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode) 541 { 542 /* Squash FZ16 to 0 for the duration of conversion. In this case, 543 * it would affect flushing input denormals. 544 */ 545 float_status *fpst = fpstp; 546 bool save = get_flush_inputs_to_zero(fpst); 547 set_flush_inputs_to_zero(false, fpst); 548 float64 r = float16_to_float64(a, !ahp_mode, fpst); 549 set_flush_inputs_to_zero(save, fpst); 550 return r; 551 } 552 553 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) 554 { 555 /* Squash FZ16 to 0 for the duration of conversion. In this case, 556 * it would affect flushing output denormals. 557 */ 558 float_status *fpst = fpstp; 559 bool save = get_flush_to_zero(fpst); 560 set_flush_to_zero(false, fpst); 561 float16 r = float64_to_float16(a, !ahp_mode, fpst); 562 set_flush_to_zero(save, fpst); 563 return r; 564 } 565 566 /* NEON helpers. */ 567 568 /* Constants 256 and 512 are used in some helpers; we avoid relying on 569 * int->float conversions at run-time. */ 570 #define float64_256 make_float64(0x4070000000000000LL) 571 #define float64_512 make_float64(0x4080000000000000LL) 572 #define float16_maxnorm make_float16(0x7bff) 573 #define float32_maxnorm make_float32(0x7f7fffff) 574 #define float64_maxnorm make_float64(0x7fefffffffffffffLL) 575 576 /* Reciprocal functions 577 * 578 * The algorithm that must be used to calculate the estimate 579 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate 580 */ 581 582 /* See RecipEstimate() 583 * 584 * input is a 9 bit fixed point number 585 * input range 256 .. 511 for a number from 0.5 <= x < 1.0. 586 * result range 256 .. 511 for a number from 1.0 to 511/256. 587 */ 588 589 static int recip_estimate(int input) 590 { 591 int a, b, r; 592 assert(256 <= input && input < 512); 593 a = (input * 2) + 1; 594 b = (1 << 19) / a; 595 r = (b + 1) >> 1; 596 assert(256 <= r && r < 512); 597 return r; 598 } 599 600 /* 601 * Common wrapper to call recip_estimate 602 * 603 * The parameters are exponent and 64 bit fraction (without implicit 604 * bit) where the binary point is nominally at bit 52. Returns a 605 * float64 which can then be rounded to the appropriate size by the 606 * callee. 607 */ 608 609 static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac) 610 { 611 uint32_t scaled, estimate; 612 uint64_t result_frac; 613 int result_exp; 614 615 /* Handle sub-normals */ 616 if (*exp == 0) { 617 if (extract64(frac, 51, 1) == 0) { 618 *exp = -1; 619 frac <<= 2; 620 } else { 621 frac <<= 1; 622 } 623 } 624 625 /* scaled = UInt('1':fraction<51:44>) */ 626 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); 627 estimate = recip_estimate(scaled); 628 629 result_exp = exp_off - *exp; 630 result_frac = deposit64(0, 44, 8, estimate); 631 if (result_exp == 0) { 632 result_frac = deposit64(result_frac >> 1, 51, 1, 1); 633 } else if (result_exp == -1) { 634 result_frac = deposit64(result_frac >> 2, 50, 2, 1); 635 result_exp = 0; 636 } 637 638 *exp = result_exp; 639 640 return result_frac; 641 } 642 643 static bool round_to_inf(float_status *fpst, bool sign_bit) 644 { 645 switch (fpst->float_rounding_mode) { 646 case float_round_nearest_even: /* Round to Nearest */ 647 return true; 648 case float_round_up: /* Round to +Inf */ 649 return !sign_bit; 650 case float_round_down: /* Round to -Inf */ 651 return sign_bit; 652 case float_round_to_zero: /* Round to Zero */ 653 return false; 654 default: 655 g_assert_not_reached(); 656 } 657 } 658 659 uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) 660 { 661 float_status *fpst = fpstp; 662 float16 f16 = float16_squash_input_denormal(input, fpst); 663 uint32_t f16_val = float16_val(f16); 664 uint32_t f16_sign = float16_is_neg(f16); 665 int f16_exp = extract32(f16_val, 10, 5); 666 uint32_t f16_frac = extract32(f16_val, 0, 10); 667 uint64_t f64_frac; 668 669 if (float16_is_any_nan(f16)) { 670 float16 nan = f16; 671 if (float16_is_signaling_nan(f16, fpst)) { 672 float_raise(float_flag_invalid, fpst); 673 if (!fpst->default_nan_mode) { 674 nan = float16_silence_nan(f16, fpst); 675 } 676 } 677 if (fpst->default_nan_mode) { 678 nan = float16_default_nan(fpst); 679 } 680 return nan; 681 } else if (float16_is_infinity(f16)) { 682 return float16_set_sign(float16_zero, float16_is_neg(f16)); 683 } else if (float16_is_zero(f16)) { 684 float_raise(float_flag_divbyzero, fpst); 685 return float16_set_sign(float16_infinity, float16_is_neg(f16)); 686 } else if (float16_abs(f16) < (1 << 8)) { 687 /* Abs(value) < 2.0^-16 */ 688 float_raise(float_flag_overflow | float_flag_inexact, fpst); 689 if (round_to_inf(fpst, f16_sign)) { 690 return float16_set_sign(float16_infinity, f16_sign); 691 } else { 692 return float16_set_sign(float16_maxnorm, f16_sign); 693 } 694 } else if (f16_exp >= 29 && fpst->flush_to_zero) { 695 float_raise(float_flag_underflow, fpst); 696 return float16_set_sign(float16_zero, float16_is_neg(f16)); 697 } 698 699 f64_frac = call_recip_estimate(&f16_exp, 29, 700 ((uint64_t) f16_frac) << (52 - 10)); 701 702 /* result = sign : result_exp<4:0> : fraction<51:42> */ 703 f16_val = deposit32(0, 15, 1, f16_sign); 704 f16_val = deposit32(f16_val, 10, 5, f16_exp); 705 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10)); 706 return make_float16(f16_val); 707 } 708 709 float32 HELPER(recpe_f32)(float32 input, void *fpstp) 710 { 711 float_status *fpst = fpstp; 712 float32 f32 = float32_squash_input_denormal(input, fpst); 713 uint32_t f32_val = float32_val(f32); 714 bool f32_sign = float32_is_neg(f32); 715 int f32_exp = extract32(f32_val, 23, 8); 716 uint32_t f32_frac = extract32(f32_val, 0, 23); 717 uint64_t f64_frac; 718 719 if (float32_is_any_nan(f32)) { 720 float32 nan = f32; 721 if (float32_is_signaling_nan(f32, fpst)) { 722 float_raise(float_flag_invalid, fpst); 723 if (!fpst->default_nan_mode) { 724 nan = float32_silence_nan(f32, fpst); 725 } 726 } 727 if (fpst->default_nan_mode) { 728 nan = float32_default_nan(fpst); 729 } 730 return nan; 731 } else if (float32_is_infinity(f32)) { 732 return float32_set_sign(float32_zero, float32_is_neg(f32)); 733 } else if (float32_is_zero(f32)) { 734 float_raise(float_flag_divbyzero, fpst); 735 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 736 } else if (float32_abs(f32) < (1ULL << 21)) { 737 /* Abs(value) < 2.0^-128 */ 738 float_raise(float_flag_overflow | float_flag_inexact, fpst); 739 if (round_to_inf(fpst, f32_sign)) { 740 return float32_set_sign(float32_infinity, f32_sign); 741 } else { 742 return float32_set_sign(float32_maxnorm, f32_sign); 743 } 744 } else if (f32_exp >= 253 && fpst->flush_to_zero) { 745 float_raise(float_flag_underflow, fpst); 746 return float32_set_sign(float32_zero, float32_is_neg(f32)); 747 } 748 749 f64_frac = call_recip_estimate(&f32_exp, 253, 750 ((uint64_t) f32_frac) << (52 - 23)); 751 752 /* result = sign : result_exp<7:0> : fraction<51:29> */ 753 f32_val = deposit32(0, 31, 1, f32_sign); 754 f32_val = deposit32(f32_val, 23, 8, f32_exp); 755 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)); 756 return make_float32(f32_val); 757 } 758 759 float64 HELPER(recpe_f64)(float64 input, void *fpstp) 760 { 761 float_status *fpst = fpstp; 762 float64 f64 = float64_squash_input_denormal(input, fpst); 763 uint64_t f64_val = float64_val(f64); 764 bool f64_sign = float64_is_neg(f64); 765 int f64_exp = extract64(f64_val, 52, 11); 766 uint64_t f64_frac = extract64(f64_val, 0, 52); 767 768 /* Deal with any special cases */ 769 if (float64_is_any_nan(f64)) { 770 float64 nan = f64; 771 if (float64_is_signaling_nan(f64, fpst)) { 772 float_raise(float_flag_invalid, fpst); 773 if (!fpst->default_nan_mode) { 774 nan = float64_silence_nan(f64, fpst); 775 } 776 } 777 if (fpst->default_nan_mode) { 778 nan = float64_default_nan(fpst); 779 } 780 return nan; 781 } else if (float64_is_infinity(f64)) { 782 return float64_set_sign(float64_zero, float64_is_neg(f64)); 783 } else if (float64_is_zero(f64)) { 784 float_raise(float_flag_divbyzero, fpst); 785 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 786 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { 787 /* Abs(value) < 2.0^-1024 */ 788 float_raise(float_flag_overflow | float_flag_inexact, fpst); 789 if (round_to_inf(fpst, f64_sign)) { 790 return float64_set_sign(float64_infinity, f64_sign); 791 } else { 792 return float64_set_sign(float64_maxnorm, f64_sign); 793 } 794 } else if (f64_exp >= 2045 && fpst->flush_to_zero) { 795 float_raise(float_flag_underflow, fpst); 796 return float64_set_sign(float64_zero, float64_is_neg(f64)); 797 } 798 799 f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac); 800 801 /* result = sign : result_exp<10:0> : fraction<51:0>; */ 802 f64_val = deposit64(0, 63, 1, f64_sign); 803 f64_val = deposit64(f64_val, 52, 11, f64_exp); 804 f64_val = deposit64(f64_val, 0, 52, f64_frac); 805 return make_float64(f64_val); 806 } 807 808 /* The algorithm that must be used to calculate the estimate 809 * is specified by the ARM ARM. 810 */ 811 812 static int do_recip_sqrt_estimate(int a) 813 { 814 int b, estimate; 815 816 assert(128 <= a && a < 512); 817 if (a < 256) { 818 a = a * 2 + 1; 819 } else { 820 a = (a >> 1) << 1; 821 a = (a + 1) * 2; 822 } 823 b = 512; 824 while (a * (b + 1) * (b + 1) < (1 << 28)) { 825 b += 1; 826 } 827 estimate = (b + 1) / 2; 828 assert(256 <= estimate && estimate < 512); 829 830 return estimate; 831 } 832 833 834 static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac) 835 { 836 int estimate; 837 uint32_t scaled; 838 839 if (*exp == 0) { 840 while (extract64(frac, 51, 1) == 0) { 841 frac = frac << 1; 842 *exp -= 1; 843 } 844 frac = extract64(frac, 0, 51) << 1; 845 } 846 847 if (*exp & 1) { 848 /* scaled = UInt('01':fraction<51:45>) */ 849 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); 850 } else { 851 /* scaled = UInt('1':fraction<51:44>) */ 852 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); 853 } 854 estimate = do_recip_sqrt_estimate(scaled); 855 856 *exp = (exp_off - *exp) / 2; 857 return extract64(estimate, 0, 8) << 44; 858 } 859 860 uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) 861 { 862 float_status *s = fpstp; 863 float16 f16 = float16_squash_input_denormal(input, s); 864 uint16_t val = float16_val(f16); 865 bool f16_sign = float16_is_neg(f16); 866 int f16_exp = extract32(val, 10, 5); 867 uint16_t f16_frac = extract32(val, 0, 10); 868 uint64_t f64_frac; 869 870 if (float16_is_any_nan(f16)) { 871 float16 nan = f16; 872 if (float16_is_signaling_nan(f16, s)) { 873 float_raise(float_flag_invalid, s); 874 if (!s->default_nan_mode) { 875 nan = float16_silence_nan(f16, fpstp); 876 } 877 } 878 if (s->default_nan_mode) { 879 nan = float16_default_nan(s); 880 } 881 return nan; 882 } else if (float16_is_zero(f16)) { 883 float_raise(float_flag_divbyzero, s); 884 return float16_set_sign(float16_infinity, f16_sign); 885 } else if (f16_sign) { 886 float_raise(float_flag_invalid, s); 887 return float16_default_nan(s); 888 } else if (float16_is_infinity(f16)) { 889 return float16_zero; 890 } 891 892 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 893 * preserving the parity of the exponent. */ 894 895 f64_frac = ((uint64_t) f16_frac) << (52 - 10); 896 897 f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac); 898 899 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */ 900 val = deposit32(0, 15, 1, f16_sign); 901 val = deposit32(val, 10, 5, f16_exp); 902 val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8)); 903 return make_float16(val); 904 } 905 906 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) 907 { 908 float_status *s = fpstp; 909 float32 f32 = float32_squash_input_denormal(input, s); 910 uint32_t val = float32_val(f32); 911 uint32_t f32_sign = float32_is_neg(f32); 912 int f32_exp = extract32(val, 23, 8); 913 uint32_t f32_frac = extract32(val, 0, 23); 914 uint64_t f64_frac; 915 916 if (float32_is_any_nan(f32)) { 917 float32 nan = f32; 918 if (float32_is_signaling_nan(f32, s)) { 919 float_raise(float_flag_invalid, s); 920 if (!s->default_nan_mode) { 921 nan = float32_silence_nan(f32, fpstp); 922 } 923 } 924 if (s->default_nan_mode) { 925 nan = float32_default_nan(s); 926 } 927 return nan; 928 } else if (float32_is_zero(f32)) { 929 float_raise(float_flag_divbyzero, s); 930 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 931 } else if (float32_is_neg(f32)) { 932 float_raise(float_flag_invalid, s); 933 return float32_default_nan(s); 934 } else if (float32_is_infinity(f32)) { 935 return float32_zero; 936 } 937 938 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 939 * preserving the parity of the exponent. */ 940 941 f64_frac = ((uint64_t) f32_frac) << 29; 942 943 f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac); 944 945 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */ 946 val = deposit32(0, 31, 1, f32_sign); 947 val = deposit32(val, 23, 8, f32_exp); 948 val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8)); 949 return make_float32(val); 950 } 951 952 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) 953 { 954 float_status *s = fpstp; 955 float64 f64 = float64_squash_input_denormal(input, s); 956 uint64_t val = float64_val(f64); 957 bool f64_sign = float64_is_neg(f64); 958 int f64_exp = extract64(val, 52, 11); 959 uint64_t f64_frac = extract64(val, 0, 52); 960 961 if (float64_is_any_nan(f64)) { 962 float64 nan = f64; 963 if (float64_is_signaling_nan(f64, s)) { 964 float_raise(float_flag_invalid, s); 965 if (!s->default_nan_mode) { 966 nan = float64_silence_nan(f64, fpstp); 967 } 968 } 969 if (s->default_nan_mode) { 970 nan = float64_default_nan(s); 971 } 972 return nan; 973 } else if (float64_is_zero(f64)) { 974 float_raise(float_flag_divbyzero, s); 975 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 976 } else if (float64_is_neg(f64)) { 977 float_raise(float_flag_invalid, s); 978 return float64_default_nan(s); 979 } else if (float64_is_infinity(f64)) { 980 return float64_zero; 981 } 982 983 f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac); 984 985 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */ 986 val = deposit64(0, 61, 1, f64_sign); 987 val = deposit64(val, 52, 11, f64_exp); 988 val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8)); 989 return make_float64(val); 990 } 991 992 uint32_t HELPER(recpe_u32)(uint32_t a) 993 { 994 int input, estimate; 995 996 if ((a & 0x80000000) == 0) { 997 return 0xffffffff; 998 } 999 1000 input = extract32(a, 23, 9); 1001 estimate = recip_estimate(input); 1002 1003 return deposit32(0, (32 - 9), 9, estimate); 1004 } 1005 1006 uint32_t HELPER(rsqrte_u32)(uint32_t a) 1007 { 1008 int estimate; 1009 1010 if ((a & 0xc0000000) == 0) { 1011 return 0xffffffff; 1012 } 1013 1014 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9)); 1015 1016 return deposit32(0, 23, 9, estimate); 1017 } 1018 1019 /* VFPv4 fused multiply-accumulate */ 1020 dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b, 1021 dh_ctype_f16 c, void *fpstp) 1022 { 1023 float_status *fpst = fpstp; 1024 return float16_muladd(a, b, c, 0, fpst); 1025 } 1026 1027 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) 1028 { 1029 float_status *fpst = fpstp; 1030 return float32_muladd(a, b, c, 0, fpst); 1031 } 1032 1033 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) 1034 { 1035 float_status *fpst = fpstp; 1036 return float64_muladd(a, b, c, 0, fpst); 1037 } 1038 1039 /* ARMv8 round to integral */ 1040 dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status) 1041 { 1042 return float16_round_to_int(x, fp_status); 1043 } 1044 1045 float32 HELPER(rints_exact)(float32 x, void *fp_status) 1046 { 1047 return float32_round_to_int(x, fp_status); 1048 } 1049 1050 float64 HELPER(rintd_exact)(float64 x, void *fp_status) 1051 { 1052 return float64_round_to_int(x, fp_status); 1053 } 1054 1055 dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status) 1056 { 1057 int old_flags = get_float_exception_flags(fp_status), new_flags; 1058 float16 ret; 1059 1060 ret = float16_round_to_int(x, fp_status); 1061 1062 /* Suppress any inexact exceptions the conversion produced */ 1063 if (!(old_flags & float_flag_inexact)) { 1064 new_flags = get_float_exception_flags(fp_status); 1065 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1066 } 1067 1068 return ret; 1069 } 1070 1071 float32 HELPER(rints)(float32 x, void *fp_status) 1072 { 1073 int old_flags = get_float_exception_flags(fp_status), new_flags; 1074 float32 ret; 1075 1076 ret = float32_round_to_int(x, fp_status); 1077 1078 /* Suppress any inexact exceptions the conversion produced */ 1079 if (!(old_flags & float_flag_inexact)) { 1080 new_flags = get_float_exception_flags(fp_status); 1081 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1082 } 1083 1084 return ret; 1085 } 1086 1087 float64 HELPER(rintd)(float64 x, void *fp_status) 1088 { 1089 int old_flags = get_float_exception_flags(fp_status), new_flags; 1090 float64 ret; 1091 1092 ret = float64_round_to_int(x, fp_status); 1093 1094 new_flags = get_float_exception_flags(fp_status); 1095 1096 /* Suppress any inexact exceptions the conversion produced */ 1097 if (!(old_flags & float_flag_inexact)) { 1098 new_flags = get_float_exception_flags(fp_status); 1099 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1100 } 1101 1102 return ret; 1103 } 1104 1105 /* Convert ARM rounding mode to softfloat */ 1106 const FloatRoundMode arm_rmode_to_sf_map[] = { 1107 [FPROUNDING_TIEEVEN] = float_round_nearest_even, 1108 [FPROUNDING_POSINF] = float_round_up, 1109 [FPROUNDING_NEGINF] = float_round_down, 1110 [FPROUNDING_ZERO] = float_round_to_zero, 1111 [FPROUNDING_TIEAWAY] = float_round_ties_away, 1112 [FPROUNDING_ODD] = float_round_to_odd, 1113 }; 1114 1115 /* 1116 * Implement float64 to int32_t conversion without saturation; 1117 * the result is supplied modulo 2^32. 1118 */ 1119 uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) 1120 { 1121 float_status *status = vstatus; 1122 uint32_t frac, e_old, e_new; 1123 bool inexact; 1124 1125 e_old = get_float_exception_flags(status); 1126 set_float_exception_flags(0, status); 1127 frac = float64_to_int32_modulo(value, float_round_to_zero, status); 1128 e_new = get_float_exception_flags(status); 1129 set_float_exception_flags(e_old | e_new, status); 1130 1131 /* Normal inexact, denormal with flush-to-zero, or overflow or NaN */ 1132 inexact = e_new & (float_flag_inexact | 1133 float_flag_input_denormal | 1134 float_flag_invalid); 1135 1136 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ 1137 inexact |= value == float64_chs(float64_zero); 1138 1139 /* Pack the result and the env->ZF representation of Z together. */ 1140 return deposit64(frac, 32, 32, inexact); 1141 } 1142 1143 uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) 1144 { 1145 uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status); 1146 uint32_t result = pair; 1147 uint32_t z = (pair >> 32) == 0; 1148 1149 /* Store Z, clear NCV, in FPSCR.NZCV. */ 1150 env->vfp.fpsr = (env->vfp.fpsr & ~FPSR_NZCV_MASK) | (z * FPSR_Z); 1151 1152 return result; 1153 } 1154 1155 /* Round a float32 to an integer that fits in int32_t or int64_t. */ 1156 static float32 frint_s(float32 f, float_status *fpst, int intsize) 1157 { 1158 int old_flags = get_float_exception_flags(fpst); 1159 uint32_t exp = extract32(f, 23, 8); 1160 1161 if (unlikely(exp == 0xff)) { 1162 /* NaN or Inf. */ 1163 goto overflow; 1164 } 1165 1166 /* Round and re-extract the exponent. */ 1167 f = float32_round_to_int(f, fpst); 1168 exp = extract32(f, 23, 8); 1169 1170 /* Validate the range of the result. */ 1171 if (exp < 126 + intsize) { 1172 /* abs(F) <= INT{N}_MAX */ 1173 return f; 1174 } 1175 if (exp == 126 + intsize) { 1176 uint32_t sign = extract32(f, 31, 1); 1177 uint32_t frac = extract32(f, 0, 23); 1178 if (sign && frac == 0) { 1179 /* F == INT{N}_MIN */ 1180 return f; 1181 } 1182 } 1183 1184 overflow: 1185 /* 1186 * Raise Invalid and return INT{N}_MIN as a float. Revert any 1187 * inexact exception float32_round_to_int may have raised. 1188 */ 1189 set_float_exception_flags(old_flags | float_flag_invalid, fpst); 1190 return (0x100u + 126u + intsize) << 23; 1191 } 1192 1193 float32 HELPER(frint32_s)(float32 f, void *fpst) 1194 { 1195 return frint_s(f, fpst, 32); 1196 } 1197 1198 float32 HELPER(frint64_s)(float32 f, void *fpst) 1199 { 1200 return frint_s(f, fpst, 64); 1201 } 1202 1203 /* Round a float64 to an integer that fits in int32_t or int64_t. */ 1204 static float64 frint_d(float64 f, float_status *fpst, int intsize) 1205 { 1206 int old_flags = get_float_exception_flags(fpst); 1207 uint32_t exp = extract64(f, 52, 11); 1208 1209 if (unlikely(exp == 0x7ff)) { 1210 /* NaN or Inf. */ 1211 goto overflow; 1212 } 1213 1214 /* Round and re-extract the exponent. */ 1215 f = float64_round_to_int(f, fpst); 1216 exp = extract64(f, 52, 11); 1217 1218 /* Validate the range of the result. */ 1219 if (exp < 1022 + intsize) { 1220 /* abs(F) <= INT{N}_MAX */ 1221 return f; 1222 } 1223 if (exp == 1022 + intsize) { 1224 uint64_t sign = extract64(f, 63, 1); 1225 uint64_t frac = extract64(f, 0, 52); 1226 if (sign && frac == 0) { 1227 /* F == INT{N}_MIN */ 1228 return f; 1229 } 1230 } 1231 1232 overflow: 1233 /* 1234 * Raise Invalid and return INT{N}_MIN as a float. Revert any 1235 * inexact exception float64_round_to_int may have raised. 1236 */ 1237 set_float_exception_flags(old_flags | float_flag_invalid, fpst); 1238 return (uint64_t)(0x800 + 1022 + intsize) << 52; 1239 } 1240 1241 float64 HELPER(frint32_d)(float64 f, void *fpst) 1242 { 1243 return frint_d(f, fpst, 32); 1244 } 1245 1246 float64 HELPER(frint64_d)(float64 f, void *fpst) 1247 { 1248 return frint_d(f, fpst, 64); 1249 } 1250 1251 void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg) 1252 { 1253 uint32_t syndrome; 1254 1255 switch (reg) { 1256 case ARM_VFP_MVFR0: 1257 case ARM_VFP_MVFR1: 1258 case ARM_VFP_MVFR2: 1259 if (!(arm_hcr_el2_eff(env) & HCR_TID3)) { 1260 return; 1261 } 1262 break; 1263 case ARM_VFP_FPSID: 1264 if (!(arm_hcr_el2_eff(env) & HCR_TID0)) { 1265 return; 1266 } 1267 break; 1268 default: 1269 g_assert_not_reached(); 1270 } 1271 1272 syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT) 1273 | ARM_EL_IL 1274 | (1 << 24) | (0xe << 20) | (7 << 14) 1275 | (reg << 10) | (rt << 5) | 1); 1276 1277 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); 1278 } 1279 1280 #endif 1281