1 /*
2 * ARM VFP floating-point operations
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "internals.h"
24 #include "cpu-features.h"
25 #ifdef CONFIG_TCG
26 #include "qemu/log.h"
27 #include "fpu/softfloat.h"
28 #endif
29
30 /* VFP support. We follow the convention used for VFP instructions:
31 Single precision routines have a "s" suffix, double precision a
32 "d" suffix. */
33
34 #ifdef CONFIG_TCG
35
36 /* Convert host exception flags to vfp form. */
vfp_exceptbits_from_host(int host_bits)37 static inline int vfp_exceptbits_from_host(int host_bits)
38 {
39 int target_bits = 0;
40
41 if (host_bits & float_flag_invalid) {
42 target_bits |= 1;
43 }
44 if (host_bits & float_flag_divbyzero) {
45 target_bits |= 2;
46 }
47 if (host_bits & float_flag_overflow) {
48 target_bits |= 4;
49 }
50 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
51 target_bits |= 8;
52 }
53 if (host_bits & float_flag_inexact) {
54 target_bits |= 0x10;
55 }
56 if (host_bits & float_flag_input_denormal) {
57 target_bits |= 0x80;
58 }
59 return target_bits;
60 }
61
62 /* Convert vfp exception flags to target form. */
vfp_exceptbits_to_host(int target_bits)63 static inline int vfp_exceptbits_to_host(int target_bits)
64 {
65 int host_bits = 0;
66
67 if (target_bits & 1) {
68 host_bits |= float_flag_invalid;
69 }
70 if (target_bits & 2) {
71 host_bits |= float_flag_divbyzero;
72 }
73 if (target_bits & 4) {
74 host_bits |= float_flag_overflow;
75 }
76 if (target_bits & 8) {
77 host_bits |= float_flag_underflow;
78 }
79 if (target_bits & 0x10) {
80 host_bits |= float_flag_inexact;
81 }
82 if (target_bits & 0x80) {
83 host_bits |= float_flag_input_denormal;
84 }
85 return host_bits;
86 }
87
vfp_get_fpsr_from_host(CPUARMState * env)88 static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
89 {
90 uint32_t i;
91
92 i = get_float_exception_flags(&env->vfp.fp_status);
93 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
94 /* FZ16 does not generate an input denormal exception. */
95 i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
96 & ~float_flag_input_denormal);
97 i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16)
98 & ~float_flag_input_denormal);
99 return vfp_exceptbits_from_host(i);
100 }
101
vfp_set_fpsr_to_host(CPUARMState * env,uint32_t val)102 static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val)
103 {
104 /*
105 * The exception flags are ORed together when we read fpscr so we
106 * only need to preserve the current state in one of our
107 * float_status values.
108 */
109 int i = vfp_exceptbits_to_host(val);
110 set_float_exception_flags(i, &env->vfp.fp_status);
111 set_float_exception_flags(0, &env->vfp.fp_status_f16);
112 set_float_exception_flags(0, &env->vfp.standard_fp_status);
113 set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
114 }
115
vfp_set_fpcr_to_host(CPUARMState * env,uint32_t val,uint32_t mask)116 static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
117 {
118 uint64_t changed = env->vfp.fpcr;
119
120 changed ^= val;
121 changed &= mask;
122 if (changed & (3 << 22)) {
123 int i = (val >> 22) & 3;
124 switch (i) {
125 case FPROUNDING_TIEEVEN:
126 i = float_round_nearest_even;
127 break;
128 case FPROUNDING_POSINF:
129 i = float_round_up;
130 break;
131 case FPROUNDING_NEGINF:
132 i = float_round_down;
133 break;
134 case FPROUNDING_ZERO:
135 i = float_round_to_zero;
136 break;
137 }
138 set_float_rounding_mode(i, &env->vfp.fp_status);
139 set_float_rounding_mode(i, &env->vfp.fp_status_f16);
140 }
141 if (changed & FPCR_FZ16) {
142 bool ftz_enabled = val & FPCR_FZ16;
143 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
144 set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
145 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
146 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
147 }
148 if (changed & FPCR_FZ) {
149 bool ftz_enabled = val & FPCR_FZ;
150 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
151 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
152 }
153 if (changed & FPCR_DN) {
154 bool dnan_enabled = val & FPCR_DN;
155 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
156 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
157 }
158 }
159
160 #else
161
vfp_get_fpsr_from_host(CPUARMState * env)162 static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
163 {
164 return 0;
165 }
166
vfp_set_fpsr_to_host(CPUARMState * env,uint32_t val)167 static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val)
168 {
169 }
170
vfp_set_fpcr_to_host(CPUARMState * env,uint32_t val,uint32_t mask)171 static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
172 {
173 }
174
175 #endif
176
vfp_get_fpcr(CPUARMState * env)177 uint32_t vfp_get_fpcr(CPUARMState *env)
178 {
179 uint32_t fpcr = env->vfp.fpcr
180 | (env->vfp.vec_len << 16)
181 | (env->vfp.vec_stride << 20);
182
183 /*
184 * M-profile LTPSIZE is the same bits [18:16] as A-profile Len; whichever
185 * of the two is not applicable to this CPU will always be zero.
186 */
187 fpcr |= env->v7m.ltpsize << 16;
188
189 return fpcr;
190 }
191
vfp_get_fpsr(CPUARMState * env)192 uint32_t vfp_get_fpsr(CPUARMState *env)
193 {
194 uint32_t fpsr = env->vfp.fpsr;
195 uint32_t i;
196
197 fpsr |= vfp_get_fpsr_from_host(env);
198
199 i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
200 fpsr |= i ? FPSR_QC : 0;
201 return fpsr;
202 }
203
HELPER(vfp_get_fpscr)204 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
205 {
206 return (vfp_get_fpcr(env) & FPSCR_FPCR_MASK) |
207 (vfp_get_fpsr(env) & FPSCR_FPSR_MASK);
208 }
209
vfp_get_fpscr(CPUARMState * env)210 uint32_t vfp_get_fpscr(CPUARMState *env)
211 {
212 return HELPER(vfp_get_fpscr)(env);
213 }
214
vfp_set_fpsr(CPUARMState * env,uint32_t val)215 void vfp_set_fpsr(CPUARMState *env, uint32_t val)
216 {
217 ARMCPU *cpu = env_archcpu(env);
218
219 vfp_set_fpsr_to_host(env, val);
220
221 if (arm_feature(env, ARM_FEATURE_NEON) ||
222 cpu_isar_feature(aa32_mve, cpu)) {
223 /*
224 * The bit we set within vfp.qc[] is arbitrary; the array as a
225 * whole being zero/non-zero is what counts.
226 */
227 env->vfp.qc[0] = val & FPSR_QC;
228 env->vfp.qc[1] = 0;
229 env->vfp.qc[2] = 0;
230 env->vfp.qc[3] = 0;
231 }
232
233 /*
234 * The only FPSR bits we keep in vfp.fpsr are NZCV:
235 * the exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
236 * fp_status, and QC is in vfp.qc[]. Store the NZCV bits there,
237 * and zero any of the other FPSR bits.
238 */
239 val &= FPSR_NZCV_MASK;
240 env->vfp.fpsr = val;
241 }
242
vfp_set_fpcr_masked(CPUARMState * env,uint32_t val,uint32_t mask)243 static void vfp_set_fpcr_masked(CPUARMState *env, uint32_t val, uint32_t mask)
244 {
245 /*
246 * We only set FPCR bits defined by mask, and leave the others alone.
247 * We assume the mask is sensible (e.g. doesn't try to set only
248 * part of a field)
249 */
250 ARMCPU *cpu = env_archcpu(env);
251
252 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
253 if (!cpu_isar_feature(any_fp16, cpu)) {
254 val &= ~FPCR_FZ16;
255 }
256
257 vfp_set_fpcr_to_host(env, val, mask);
258
259 if (mask & (FPCR_LEN_MASK | FPCR_STRIDE_MASK)) {
260 if (!arm_feature(env, ARM_FEATURE_M)) {
261 /*
262 * Short-vector length and stride; on M-profile these bits
263 * are used for different purposes.
264 * We can't make this conditional be "if MVFR0.FPShVec != 0",
265 * because in v7A no-short-vector-support cores still had to
266 * allow Stride/Len to be written with the only effect that
267 * some insns are required to UNDEF if the guest sets them.
268 */
269 env->vfp.vec_len = extract32(val, 16, 3);
270 env->vfp.vec_stride = extract32(val, 20, 2);
271 } else if (cpu_isar_feature(aa32_mve, cpu)) {
272 env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT,
273 FPCR_LTPSIZE_LENGTH);
274 }
275 }
276
277 /*
278 * We don't implement trapped exception handling, so the
279 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
280 *
281 * The FPCR bits we keep in vfp.fpcr are AHP, DN, FZ, RMode
282 * and FZ16. Len, Stride and LTPSIZE we just handled. Store those bits
283 * there, and zero any of the other FPCR bits and the RES0 and RAZ/WI
284 * bits.
285 */
286 val &= FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16;
287 env->vfp.fpcr &= ~mask;
288 env->vfp.fpcr |= val;
289 }
290
vfp_set_fpcr(CPUARMState * env,uint32_t val)291 void vfp_set_fpcr(CPUARMState *env, uint32_t val)
292 {
293 vfp_set_fpcr_masked(env, val, MAKE_64BIT_MASK(0, 32));
294 }
295
HELPER(vfp_set_fpscr)296 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
297 {
298 vfp_set_fpcr_masked(env, val, FPSCR_FPCR_MASK);
299 vfp_set_fpsr(env, val & FPSCR_FPSR_MASK);
300 }
301
vfp_set_fpscr(CPUARMState * env,uint32_t val)302 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
303 {
304 HELPER(vfp_set_fpscr)(env, val);
305 }
306
307 #ifdef CONFIG_TCG
308
309 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
310
311 #define VFP_BINOP(name) \
312 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
313 { \
314 float_status *fpst = fpstp; \
315 return float16_ ## name(a, b, fpst); \
316 } \
317 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
318 { \
319 float_status *fpst = fpstp; \
320 return float32_ ## name(a, b, fpst); \
321 } \
322 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
323 { \
324 float_status *fpst = fpstp; \
325 return float64_ ## name(a, b, fpst); \
326 }
327 VFP_BINOP(add)
VFP_BINOP(sub)328 VFP_BINOP(sub)
329 VFP_BINOP(mul)
330 VFP_BINOP(div)
331 VFP_BINOP(min)
332 VFP_BINOP(max)
333 VFP_BINOP(minnum)
334 VFP_BINOP(maxnum)
335 #undef VFP_BINOP
336
337 dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env)
338 {
339 return float16_sqrt(a, &env->vfp.fp_status_f16);
340 }
341
VFP_HELPER(sqrt,s)342 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
343 {
344 return float32_sqrt(a, &env->vfp.fp_status);
345 }
346
VFP_HELPER(sqrt,d)347 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
348 {
349 return float64_sqrt(a, &env->vfp.fp_status);
350 }
351
softfloat_to_vfp_compare(CPUARMState * env,FloatRelation cmp)352 static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
353 {
354 uint32_t flags;
355 switch (cmp) {
356 case float_relation_equal:
357 flags = 0x6;
358 break;
359 case float_relation_less:
360 flags = 0x8;
361 break;
362 case float_relation_greater:
363 flags = 0x2;
364 break;
365 case float_relation_unordered:
366 flags = 0x3;
367 break;
368 default:
369 g_assert_not_reached();
370 }
371 env->vfp.fpsr = deposit64(env->vfp.fpsr, 28, 4, flags); /* NZCV */
372 }
373
374 /* XXX: check quiet/signaling case */
375 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \
376 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
377 { \
378 softfloat_to_vfp_compare(env, \
379 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \
380 } \
381 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
382 { \
383 softfloat_to_vfp_compare(env, \
384 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
385 }
DO_VFP_cmp(h,float16,dh_ctype_f16,fp_status_f16)386 DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16)
387 DO_VFP_cmp(s, float32, float32, fp_status)
388 DO_VFP_cmp(d, float64, float64, fp_status)
389 #undef DO_VFP_cmp
390
391 /* Integer to float and float to integer conversions */
392
393 #define CONV_ITOF(name, ftype, fsz, sign) \
394 ftype HELPER(name)(uint32_t x, void *fpstp) \
395 { \
396 float_status *fpst = fpstp; \
397 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
398 }
399
400 #define CONV_FTOI(name, ftype, fsz, sign, round) \
401 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
402 { \
403 float_status *fpst = fpstp; \
404 if (float##fsz##_is_any_nan(x)) { \
405 float_raise(float_flag_invalid, fpst); \
406 return 0; \
407 } \
408 return float##fsz##_to_##sign##int32##round(x, fpst); \
409 }
410
411 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
412 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
413 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
414 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
415
416 FLOAT_CONVS(si, h, uint32_t, 16, )
417 FLOAT_CONVS(si, s, float32, 32, )
418 FLOAT_CONVS(si, d, float64, 64, )
419 FLOAT_CONVS(ui, h, uint32_t, 16, u)
420 FLOAT_CONVS(ui, s, float32, 32, u)
421 FLOAT_CONVS(ui, d, float64, 64, u)
422
423 #undef CONV_ITOF
424 #undef CONV_FTOI
425 #undef FLOAT_CONVS
426
427 /* floating point conversion */
428 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
429 {
430 return float32_to_float64(x, &env->vfp.fp_status);
431 }
432
VFP_HELPER(fcvts,d)433 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
434 {
435 return float64_to_float32(x, &env->vfp.fp_status);
436 }
437
HELPER(bfcvt)438 uint32_t HELPER(bfcvt)(float32 x, void *status)
439 {
440 return float32_to_bfloat16(x, status);
441 }
442
HELPER(bfcvt_pair)443 uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status)
444 {
445 bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status);
446 bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status);
447 return deposit32(lo, 16, 16, hi);
448 }
449
450 /*
451 * VFP3 fixed point conversion. The AArch32 versions of fix-to-float
452 * must always round-to-nearest; the AArch64 ones honour the FPSCR
453 * rounding mode. (For AArch32 Neon the standard-FPSCR is set to
454 * round-to-nearest so either helper will work.) AArch32 float-to-fix
455 * must round-to-zero.
456 */
457 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
458 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
459 void *fpstp) \
460 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
461
462 #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
463 ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \
464 uint32_t shift, \
465 void *fpstp) \
466 { \
467 ftype ret; \
468 float_status *fpst = fpstp; \
469 FloatRoundMode oldmode = fpst->float_rounding_mode; \
470 fpst->float_rounding_mode = float_round_nearest_even; \
471 ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \
472 fpst->float_rounding_mode = oldmode; \
473 return ret; \
474 }
475
476 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
477 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
478 void *fpst) \
479 { \
480 if (unlikely(float##fsz##_is_any_nan(x))) { \
481 float_raise(float_flag_invalid, fpst); \
482 return 0; \
483 } \
484 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
485 }
486
487 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \
488 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
489 VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
490 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
491 float_round_to_zero, _round_to_zero) \
492 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
493 get_float_rounding_mode(fpst), )
494
495 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \
496 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
497 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
498 get_float_rounding_mode(fpst), )
499
500 VFP_CONV_FIX(sh, d, 64, float64, 64, int16)
501 VFP_CONV_FIX(sl, d, 64, float64, 64, int32)
502 VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64)
503 VFP_CONV_FIX(uh, d, 64, float64, 64, uint16)
504 VFP_CONV_FIX(ul, d, 64, float64, 64, uint32)
505 VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64)
506 VFP_CONV_FIX(sh, s, 32, float32, 32, int16)
507 VFP_CONV_FIX(sl, s, 32, float32, 32, int32)
508 VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64)
509 VFP_CONV_FIX(uh, s, 32, float32, 32, uint16)
510 VFP_CONV_FIX(ul, s, 32, float32, 32, uint32)
511 VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64)
512 VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16)
513 VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32)
514 VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64)
515 VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16)
516 VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32)
517 VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64)
518
519 #undef VFP_CONV_FIX
520 #undef VFP_CONV_FIX_FLOAT
521 #undef VFP_CONV_FLOAT_FIX_ROUND
522 #undef VFP_CONV_FIX_A64
523
524 /* Set the current fp rounding mode and return the old one.
525 * The argument is a softfloat float_round_ value.
526 */
HELPER(set_rmode)527 uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
528 {
529 float_status *fp_status = fpstp;
530
531 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
532 set_float_rounding_mode(rmode, fp_status);
533
534 return prev_rmode;
535 }
536
537 /* Half precision conversions. */
HELPER(vfp_fcvt_f16_to_f32)538 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
539 {
540 /* Squash FZ16 to 0 for the duration of conversion. In this case,
541 * it would affect flushing input denormals.
542 */
543 float_status *fpst = fpstp;
544 bool save = get_flush_inputs_to_zero(fpst);
545 set_flush_inputs_to_zero(false, fpst);
546 float32 r = float16_to_float32(a, !ahp_mode, fpst);
547 set_flush_inputs_to_zero(save, fpst);
548 return r;
549 }
550
HELPER(vfp_fcvt_f32_to_f16)551 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
552 {
553 /* Squash FZ16 to 0 for the duration of conversion. In this case,
554 * it would affect flushing output denormals.
555 */
556 float_status *fpst = fpstp;
557 bool save = get_flush_to_zero(fpst);
558 set_flush_to_zero(false, fpst);
559 float16 r = float32_to_float16(a, !ahp_mode, fpst);
560 set_flush_to_zero(save, fpst);
561 return r;
562 }
563
HELPER(vfp_fcvt_f16_to_f64)564 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
565 {
566 /* Squash FZ16 to 0 for the duration of conversion. In this case,
567 * it would affect flushing input denormals.
568 */
569 float_status *fpst = fpstp;
570 bool save = get_flush_inputs_to_zero(fpst);
571 set_flush_inputs_to_zero(false, fpst);
572 float64 r = float16_to_float64(a, !ahp_mode, fpst);
573 set_flush_inputs_to_zero(save, fpst);
574 return r;
575 }
576
HELPER(vfp_fcvt_f64_to_f16)577 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
578 {
579 /* Squash FZ16 to 0 for the duration of conversion. In this case,
580 * it would affect flushing output denormals.
581 */
582 float_status *fpst = fpstp;
583 bool save = get_flush_to_zero(fpst);
584 set_flush_to_zero(false, fpst);
585 float16 r = float64_to_float16(a, !ahp_mode, fpst);
586 set_flush_to_zero(save, fpst);
587 return r;
588 }
589
590 /* NEON helpers. */
591
592 /* Constants 256 and 512 are used in some helpers; we avoid relying on
593 * int->float conversions at run-time. */
594 #define float64_256 make_float64(0x4070000000000000LL)
595 #define float64_512 make_float64(0x4080000000000000LL)
596 #define float16_maxnorm make_float16(0x7bff)
597 #define float32_maxnorm make_float32(0x7f7fffff)
598 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
599
600 /* Reciprocal functions
601 *
602 * The algorithm that must be used to calculate the estimate
603 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
604 */
605
606 /* See RecipEstimate()
607 *
608 * input is a 9 bit fixed point number
609 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
610 * result range 256 .. 511 for a number from 1.0 to 511/256.
611 */
612
recip_estimate(int input)613 static int recip_estimate(int input)
614 {
615 int a, b, r;
616 assert(256 <= input && input < 512);
617 a = (input * 2) + 1;
618 b = (1 << 19) / a;
619 r = (b + 1) >> 1;
620 assert(256 <= r && r < 512);
621 return r;
622 }
623
624 /*
625 * Common wrapper to call recip_estimate
626 *
627 * The parameters are exponent and 64 bit fraction (without implicit
628 * bit) where the binary point is nominally at bit 52. Returns a
629 * float64 which can then be rounded to the appropriate size by the
630 * callee.
631 */
632
call_recip_estimate(int * exp,int exp_off,uint64_t frac)633 static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
634 {
635 uint32_t scaled, estimate;
636 uint64_t result_frac;
637 int result_exp;
638
639 /* Handle sub-normals */
640 if (*exp == 0) {
641 if (extract64(frac, 51, 1) == 0) {
642 *exp = -1;
643 frac <<= 2;
644 } else {
645 frac <<= 1;
646 }
647 }
648
649 /* scaled = UInt('1':fraction<51:44>) */
650 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
651 estimate = recip_estimate(scaled);
652
653 result_exp = exp_off - *exp;
654 result_frac = deposit64(0, 44, 8, estimate);
655 if (result_exp == 0) {
656 result_frac = deposit64(result_frac >> 1, 51, 1, 1);
657 } else if (result_exp == -1) {
658 result_frac = deposit64(result_frac >> 2, 50, 2, 1);
659 result_exp = 0;
660 }
661
662 *exp = result_exp;
663
664 return result_frac;
665 }
666
round_to_inf(float_status * fpst,bool sign_bit)667 static bool round_to_inf(float_status *fpst, bool sign_bit)
668 {
669 switch (fpst->float_rounding_mode) {
670 case float_round_nearest_even: /* Round to Nearest */
671 return true;
672 case float_round_up: /* Round to +Inf */
673 return !sign_bit;
674 case float_round_down: /* Round to -Inf */
675 return sign_bit;
676 case float_round_to_zero: /* Round to Zero */
677 return false;
678 default:
679 g_assert_not_reached();
680 }
681 }
682
HELPER(recpe_f16)683 uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
684 {
685 float_status *fpst = fpstp;
686 float16 f16 = float16_squash_input_denormal(input, fpst);
687 uint32_t f16_val = float16_val(f16);
688 uint32_t f16_sign = float16_is_neg(f16);
689 int f16_exp = extract32(f16_val, 10, 5);
690 uint32_t f16_frac = extract32(f16_val, 0, 10);
691 uint64_t f64_frac;
692
693 if (float16_is_any_nan(f16)) {
694 float16 nan = f16;
695 if (float16_is_signaling_nan(f16, fpst)) {
696 float_raise(float_flag_invalid, fpst);
697 if (!fpst->default_nan_mode) {
698 nan = float16_silence_nan(f16, fpst);
699 }
700 }
701 if (fpst->default_nan_mode) {
702 nan = float16_default_nan(fpst);
703 }
704 return nan;
705 } else if (float16_is_infinity(f16)) {
706 return float16_set_sign(float16_zero, float16_is_neg(f16));
707 } else if (float16_is_zero(f16)) {
708 float_raise(float_flag_divbyzero, fpst);
709 return float16_set_sign(float16_infinity, float16_is_neg(f16));
710 } else if (float16_abs(f16) < (1 << 8)) {
711 /* Abs(value) < 2.0^-16 */
712 float_raise(float_flag_overflow | float_flag_inexact, fpst);
713 if (round_to_inf(fpst, f16_sign)) {
714 return float16_set_sign(float16_infinity, f16_sign);
715 } else {
716 return float16_set_sign(float16_maxnorm, f16_sign);
717 }
718 } else if (f16_exp >= 29 && fpst->flush_to_zero) {
719 float_raise(float_flag_underflow, fpst);
720 return float16_set_sign(float16_zero, float16_is_neg(f16));
721 }
722
723 f64_frac = call_recip_estimate(&f16_exp, 29,
724 ((uint64_t) f16_frac) << (52 - 10));
725
726 /* result = sign : result_exp<4:0> : fraction<51:42> */
727 f16_val = deposit32(0, 15, 1, f16_sign);
728 f16_val = deposit32(f16_val, 10, 5, f16_exp);
729 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
730 return make_float16(f16_val);
731 }
732
HELPER(recpe_f32)733 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
734 {
735 float_status *fpst = fpstp;
736 float32 f32 = float32_squash_input_denormal(input, fpst);
737 uint32_t f32_val = float32_val(f32);
738 bool f32_sign = float32_is_neg(f32);
739 int f32_exp = extract32(f32_val, 23, 8);
740 uint32_t f32_frac = extract32(f32_val, 0, 23);
741 uint64_t f64_frac;
742
743 if (float32_is_any_nan(f32)) {
744 float32 nan = f32;
745 if (float32_is_signaling_nan(f32, fpst)) {
746 float_raise(float_flag_invalid, fpst);
747 if (!fpst->default_nan_mode) {
748 nan = float32_silence_nan(f32, fpst);
749 }
750 }
751 if (fpst->default_nan_mode) {
752 nan = float32_default_nan(fpst);
753 }
754 return nan;
755 } else if (float32_is_infinity(f32)) {
756 return float32_set_sign(float32_zero, float32_is_neg(f32));
757 } else if (float32_is_zero(f32)) {
758 float_raise(float_flag_divbyzero, fpst);
759 return float32_set_sign(float32_infinity, float32_is_neg(f32));
760 } else if (float32_abs(f32) < (1ULL << 21)) {
761 /* Abs(value) < 2.0^-128 */
762 float_raise(float_flag_overflow | float_flag_inexact, fpst);
763 if (round_to_inf(fpst, f32_sign)) {
764 return float32_set_sign(float32_infinity, f32_sign);
765 } else {
766 return float32_set_sign(float32_maxnorm, f32_sign);
767 }
768 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
769 float_raise(float_flag_underflow, fpst);
770 return float32_set_sign(float32_zero, float32_is_neg(f32));
771 }
772
773 f64_frac = call_recip_estimate(&f32_exp, 253,
774 ((uint64_t) f32_frac) << (52 - 23));
775
776 /* result = sign : result_exp<7:0> : fraction<51:29> */
777 f32_val = deposit32(0, 31, 1, f32_sign);
778 f32_val = deposit32(f32_val, 23, 8, f32_exp);
779 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
780 return make_float32(f32_val);
781 }
782
HELPER(recpe_f64)783 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
784 {
785 float_status *fpst = fpstp;
786 float64 f64 = float64_squash_input_denormal(input, fpst);
787 uint64_t f64_val = float64_val(f64);
788 bool f64_sign = float64_is_neg(f64);
789 int f64_exp = extract64(f64_val, 52, 11);
790 uint64_t f64_frac = extract64(f64_val, 0, 52);
791
792 /* Deal with any special cases */
793 if (float64_is_any_nan(f64)) {
794 float64 nan = f64;
795 if (float64_is_signaling_nan(f64, fpst)) {
796 float_raise(float_flag_invalid, fpst);
797 if (!fpst->default_nan_mode) {
798 nan = float64_silence_nan(f64, fpst);
799 }
800 }
801 if (fpst->default_nan_mode) {
802 nan = float64_default_nan(fpst);
803 }
804 return nan;
805 } else if (float64_is_infinity(f64)) {
806 return float64_set_sign(float64_zero, float64_is_neg(f64));
807 } else if (float64_is_zero(f64)) {
808 float_raise(float_flag_divbyzero, fpst);
809 return float64_set_sign(float64_infinity, float64_is_neg(f64));
810 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
811 /* Abs(value) < 2.0^-1024 */
812 float_raise(float_flag_overflow | float_flag_inexact, fpst);
813 if (round_to_inf(fpst, f64_sign)) {
814 return float64_set_sign(float64_infinity, f64_sign);
815 } else {
816 return float64_set_sign(float64_maxnorm, f64_sign);
817 }
818 } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
819 float_raise(float_flag_underflow, fpst);
820 return float64_set_sign(float64_zero, float64_is_neg(f64));
821 }
822
823 f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
824
825 /* result = sign : result_exp<10:0> : fraction<51:0>; */
826 f64_val = deposit64(0, 63, 1, f64_sign);
827 f64_val = deposit64(f64_val, 52, 11, f64_exp);
828 f64_val = deposit64(f64_val, 0, 52, f64_frac);
829 return make_float64(f64_val);
830 }
831
832 /* The algorithm that must be used to calculate the estimate
833 * is specified by the ARM ARM.
834 */
835
do_recip_sqrt_estimate(int a)836 static int do_recip_sqrt_estimate(int a)
837 {
838 int b, estimate;
839
840 assert(128 <= a && a < 512);
841 if (a < 256) {
842 a = a * 2 + 1;
843 } else {
844 a = (a >> 1) << 1;
845 a = (a + 1) * 2;
846 }
847 b = 512;
848 while (a * (b + 1) * (b + 1) < (1 << 28)) {
849 b += 1;
850 }
851 estimate = (b + 1) / 2;
852 assert(256 <= estimate && estimate < 512);
853
854 return estimate;
855 }
856
857
recip_sqrt_estimate(int * exp,int exp_off,uint64_t frac)858 static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
859 {
860 int estimate;
861 uint32_t scaled;
862
863 if (*exp == 0) {
864 while (extract64(frac, 51, 1) == 0) {
865 frac = frac << 1;
866 *exp -= 1;
867 }
868 frac = extract64(frac, 0, 51) << 1;
869 }
870
871 if (*exp & 1) {
872 /* scaled = UInt('01':fraction<51:45>) */
873 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
874 } else {
875 /* scaled = UInt('1':fraction<51:44>) */
876 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
877 }
878 estimate = do_recip_sqrt_estimate(scaled);
879
880 *exp = (exp_off - *exp) / 2;
881 return extract64(estimate, 0, 8) << 44;
882 }
883
HELPER(rsqrte_f16)884 uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
885 {
886 float_status *s = fpstp;
887 float16 f16 = float16_squash_input_denormal(input, s);
888 uint16_t val = float16_val(f16);
889 bool f16_sign = float16_is_neg(f16);
890 int f16_exp = extract32(val, 10, 5);
891 uint16_t f16_frac = extract32(val, 0, 10);
892 uint64_t f64_frac;
893
894 if (float16_is_any_nan(f16)) {
895 float16 nan = f16;
896 if (float16_is_signaling_nan(f16, s)) {
897 float_raise(float_flag_invalid, s);
898 if (!s->default_nan_mode) {
899 nan = float16_silence_nan(f16, fpstp);
900 }
901 }
902 if (s->default_nan_mode) {
903 nan = float16_default_nan(s);
904 }
905 return nan;
906 } else if (float16_is_zero(f16)) {
907 float_raise(float_flag_divbyzero, s);
908 return float16_set_sign(float16_infinity, f16_sign);
909 } else if (f16_sign) {
910 float_raise(float_flag_invalid, s);
911 return float16_default_nan(s);
912 } else if (float16_is_infinity(f16)) {
913 return float16_zero;
914 }
915
916 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
917 * preserving the parity of the exponent. */
918
919 f64_frac = ((uint64_t) f16_frac) << (52 - 10);
920
921 f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
922
923 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
924 val = deposit32(0, 15, 1, f16_sign);
925 val = deposit32(val, 10, 5, f16_exp);
926 val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
927 return make_float16(val);
928 }
929
HELPER(rsqrte_f32)930 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
931 {
932 float_status *s = fpstp;
933 float32 f32 = float32_squash_input_denormal(input, s);
934 uint32_t val = float32_val(f32);
935 uint32_t f32_sign = float32_is_neg(f32);
936 int f32_exp = extract32(val, 23, 8);
937 uint32_t f32_frac = extract32(val, 0, 23);
938 uint64_t f64_frac;
939
940 if (float32_is_any_nan(f32)) {
941 float32 nan = f32;
942 if (float32_is_signaling_nan(f32, s)) {
943 float_raise(float_flag_invalid, s);
944 if (!s->default_nan_mode) {
945 nan = float32_silence_nan(f32, fpstp);
946 }
947 }
948 if (s->default_nan_mode) {
949 nan = float32_default_nan(s);
950 }
951 return nan;
952 } else if (float32_is_zero(f32)) {
953 float_raise(float_flag_divbyzero, s);
954 return float32_set_sign(float32_infinity, float32_is_neg(f32));
955 } else if (float32_is_neg(f32)) {
956 float_raise(float_flag_invalid, s);
957 return float32_default_nan(s);
958 } else if (float32_is_infinity(f32)) {
959 return float32_zero;
960 }
961
962 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
963 * preserving the parity of the exponent. */
964
965 f64_frac = ((uint64_t) f32_frac) << 29;
966
967 f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
968
969 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
970 val = deposit32(0, 31, 1, f32_sign);
971 val = deposit32(val, 23, 8, f32_exp);
972 val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
973 return make_float32(val);
974 }
975
HELPER(rsqrte_f64)976 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
977 {
978 float_status *s = fpstp;
979 float64 f64 = float64_squash_input_denormal(input, s);
980 uint64_t val = float64_val(f64);
981 bool f64_sign = float64_is_neg(f64);
982 int f64_exp = extract64(val, 52, 11);
983 uint64_t f64_frac = extract64(val, 0, 52);
984
985 if (float64_is_any_nan(f64)) {
986 float64 nan = f64;
987 if (float64_is_signaling_nan(f64, s)) {
988 float_raise(float_flag_invalid, s);
989 if (!s->default_nan_mode) {
990 nan = float64_silence_nan(f64, fpstp);
991 }
992 }
993 if (s->default_nan_mode) {
994 nan = float64_default_nan(s);
995 }
996 return nan;
997 } else if (float64_is_zero(f64)) {
998 float_raise(float_flag_divbyzero, s);
999 return float64_set_sign(float64_infinity, float64_is_neg(f64));
1000 } else if (float64_is_neg(f64)) {
1001 float_raise(float_flag_invalid, s);
1002 return float64_default_nan(s);
1003 } else if (float64_is_infinity(f64)) {
1004 return float64_zero;
1005 }
1006
1007 f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
1008
1009 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
1010 val = deposit64(0, 61, 1, f64_sign);
1011 val = deposit64(val, 52, 11, f64_exp);
1012 val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
1013 return make_float64(val);
1014 }
1015
HELPER(recpe_u32)1016 uint32_t HELPER(recpe_u32)(uint32_t a)
1017 {
1018 int input, estimate;
1019
1020 if ((a & 0x80000000) == 0) {
1021 return 0xffffffff;
1022 }
1023
1024 input = extract32(a, 23, 9);
1025 estimate = recip_estimate(input);
1026
1027 return deposit32(0, (32 - 9), 9, estimate);
1028 }
1029
HELPER(rsqrte_u32)1030 uint32_t HELPER(rsqrte_u32)(uint32_t a)
1031 {
1032 int estimate;
1033
1034 if ((a & 0xc0000000) == 0) {
1035 return 0xffffffff;
1036 }
1037
1038 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
1039
1040 return deposit32(0, 23, 9, estimate);
1041 }
1042
1043 /* VFPv4 fused multiply-accumulate */
VFP_HELPER(muladd,h)1044 dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b,
1045 dh_ctype_f16 c, void *fpstp)
1046 {
1047 float_status *fpst = fpstp;
1048 return float16_muladd(a, b, c, 0, fpst);
1049 }
1050
VFP_HELPER(muladd,s)1051 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
1052 {
1053 float_status *fpst = fpstp;
1054 return float32_muladd(a, b, c, 0, fpst);
1055 }
1056
VFP_HELPER(muladd,d)1057 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
1058 {
1059 float_status *fpst = fpstp;
1060 return float64_muladd(a, b, c, 0, fpst);
1061 }
1062
1063 /* ARMv8 round to integral */
HELPER(rinth_exact)1064 dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status)
1065 {
1066 return float16_round_to_int(x, fp_status);
1067 }
1068
HELPER(rints_exact)1069 float32 HELPER(rints_exact)(float32 x, void *fp_status)
1070 {
1071 return float32_round_to_int(x, fp_status);
1072 }
1073
HELPER(rintd_exact)1074 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
1075 {
1076 return float64_round_to_int(x, fp_status);
1077 }
1078
HELPER(rinth)1079 dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
1080 {
1081 int old_flags = get_float_exception_flags(fp_status), new_flags;
1082 float16 ret;
1083
1084 ret = float16_round_to_int(x, fp_status);
1085
1086 /* Suppress any inexact exceptions the conversion produced */
1087 if (!(old_flags & float_flag_inexact)) {
1088 new_flags = get_float_exception_flags(fp_status);
1089 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1090 }
1091
1092 return ret;
1093 }
1094
HELPER(rints)1095 float32 HELPER(rints)(float32 x, void *fp_status)
1096 {
1097 int old_flags = get_float_exception_flags(fp_status), new_flags;
1098 float32 ret;
1099
1100 ret = float32_round_to_int(x, fp_status);
1101
1102 /* Suppress any inexact exceptions the conversion produced */
1103 if (!(old_flags & float_flag_inexact)) {
1104 new_flags = get_float_exception_flags(fp_status);
1105 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1106 }
1107
1108 return ret;
1109 }
1110
HELPER(rintd)1111 float64 HELPER(rintd)(float64 x, void *fp_status)
1112 {
1113 int old_flags = get_float_exception_flags(fp_status), new_flags;
1114 float64 ret;
1115
1116 ret = float64_round_to_int(x, fp_status);
1117
1118 new_flags = get_float_exception_flags(fp_status);
1119
1120 /* Suppress any inexact exceptions the conversion produced */
1121 if (!(old_flags & float_flag_inexact)) {
1122 new_flags = get_float_exception_flags(fp_status);
1123 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1124 }
1125
1126 return ret;
1127 }
1128
1129 /* Convert ARM rounding mode to softfloat */
1130 const FloatRoundMode arm_rmode_to_sf_map[] = {
1131 [FPROUNDING_TIEEVEN] = float_round_nearest_even,
1132 [FPROUNDING_POSINF] = float_round_up,
1133 [FPROUNDING_NEGINF] = float_round_down,
1134 [FPROUNDING_ZERO] = float_round_to_zero,
1135 [FPROUNDING_TIEAWAY] = float_round_ties_away,
1136 [FPROUNDING_ODD] = float_round_to_odd,
1137 };
1138
1139 /*
1140 * Implement float64 to int32_t conversion without saturation;
1141 * the result is supplied modulo 2^32.
1142 */
HELPER(fjcvtzs)1143 uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
1144 {
1145 float_status *status = vstatus;
1146 uint32_t frac, e_old, e_new;
1147 bool inexact;
1148
1149 e_old = get_float_exception_flags(status);
1150 set_float_exception_flags(0, status);
1151 frac = float64_to_int32_modulo(value, float_round_to_zero, status);
1152 e_new = get_float_exception_flags(status);
1153 set_float_exception_flags(e_old | e_new, status);
1154
1155 /* Normal inexact, denormal with flush-to-zero, or overflow or NaN */
1156 inexact = e_new & (float_flag_inexact |
1157 float_flag_input_denormal |
1158 float_flag_invalid);
1159
1160 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1161 inexact |= value == float64_chs(float64_zero);
1162
1163 /* Pack the result and the env->ZF representation of Z together. */
1164 return deposit64(frac, 32, 32, inexact);
1165 }
1166
HELPER(vjcvt)1167 uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
1168 {
1169 uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status);
1170 uint32_t result = pair;
1171 uint32_t z = (pair >> 32) == 0;
1172
1173 /* Store Z, clear NCV, in FPSCR.NZCV. */
1174 env->vfp.fpsr = (env->vfp.fpsr & ~FPSR_NZCV_MASK) | (z * FPSR_Z);
1175
1176 return result;
1177 }
1178
1179 /* Round a float32 to an integer that fits in int32_t or int64_t. */
frint_s(float32 f,float_status * fpst,int intsize)1180 static float32 frint_s(float32 f, float_status *fpst, int intsize)
1181 {
1182 int old_flags = get_float_exception_flags(fpst);
1183 uint32_t exp = extract32(f, 23, 8);
1184
1185 if (unlikely(exp == 0xff)) {
1186 /* NaN or Inf. */
1187 goto overflow;
1188 }
1189
1190 /* Round and re-extract the exponent. */
1191 f = float32_round_to_int(f, fpst);
1192 exp = extract32(f, 23, 8);
1193
1194 /* Validate the range of the result. */
1195 if (exp < 126 + intsize) {
1196 /* abs(F) <= INT{N}_MAX */
1197 return f;
1198 }
1199 if (exp == 126 + intsize) {
1200 uint32_t sign = extract32(f, 31, 1);
1201 uint32_t frac = extract32(f, 0, 23);
1202 if (sign && frac == 0) {
1203 /* F == INT{N}_MIN */
1204 return f;
1205 }
1206 }
1207
1208 overflow:
1209 /*
1210 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1211 * inexact exception float32_round_to_int may have raised.
1212 */
1213 set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1214 return (0x100u + 126u + intsize) << 23;
1215 }
1216
HELPER(frint32_s)1217 float32 HELPER(frint32_s)(float32 f, void *fpst)
1218 {
1219 return frint_s(f, fpst, 32);
1220 }
1221
HELPER(frint64_s)1222 float32 HELPER(frint64_s)(float32 f, void *fpst)
1223 {
1224 return frint_s(f, fpst, 64);
1225 }
1226
1227 /* Round a float64 to an integer that fits in int32_t or int64_t. */
frint_d(float64 f,float_status * fpst,int intsize)1228 static float64 frint_d(float64 f, float_status *fpst, int intsize)
1229 {
1230 int old_flags = get_float_exception_flags(fpst);
1231 uint32_t exp = extract64(f, 52, 11);
1232
1233 if (unlikely(exp == 0x7ff)) {
1234 /* NaN or Inf. */
1235 goto overflow;
1236 }
1237
1238 /* Round and re-extract the exponent. */
1239 f = float64_round_to_int(f, fpst);
1240 exp = extract64(f, 52, 11);
1241
1242 /* Validate the range of the result. */
1243 if (exp < 1022 + intsize) {
1244 /* abs(F) <= INT{N}_MAX */
1245 return f;
1246 }
1247 if (exp == 1022 + intsize) {
1248 uint64_t sign = extract64(f, 63, 1);
1249 uint64_t frac = extract64(f, 0, 52);
1250 if (sign && frac == 0) {
1251 /* F == INT{N}_MIN */
1252 return f;
1253 }
1254 }
1255
1256 overflow:
1257 /*
1258 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1259 * inexact exception float64_round_to_int may have raised.
1260 */
1261 set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1262 return (uint64_t)(0x800 + 1022 + intsize) << 52;
1263 }
1264
HELPER(frint32_d)1265 float64 HELPER(frint32_d)(float64 f, void *fpst)
1266 {
1267 return frint_d(f, fpst, 32);
1268 }
1269
HELPER(frint64_d)1270 float64 HELPER(frint64_d)(float64 f, void *fpst)
1271 {
1272 return frint_d(f, fpst, 64);
1273 }
1274
HELPER(check_hcr_el2_trap)1275 void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg)
1276 {
1277 uint32_t syndrome;
1278
1279 switch (reg) {
1280 case ARM_VFP_MVFR0:
1281 case ARM_VFP_MVFR1:
1282 case ARM_VFP_MVFR2:
1283 if (!(arm_hcr_el2_eff(env) & HCR_TID3)) {
1284 return;
1285 }
1286 break;
1287 case ARM_VFP_FPSID:
1288 if (!(arm_hcr_el2_eff(env) & HCR_TID0)) {
1289 return;
1290 }
1291 break;
1292 default:
1293 g_assert_not_reached();
1294 }
1295
1296 syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT)
1297 | ARM_EL_IL
1298 | (1 << 24) | (0xe << 20) | (7 << 14)
1299 | (reg << 10) | (rt << 5) | 1);
1300
1301 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
1302 }
1303
1304 #endif
1305