xref: /openbmc/qemu/target/arm/tcg/vfp.decode (revision b8116f4c) 
1# AArch32 VFP instruction descriptions (conditional insns)
2#
3#  Copyright (c) 2019 Linaro, Ltd
4#
5# This library is free software; you can redistribute it and/or
6# modify it under the terms of the GNU Lesser General Public
7# License as published by the Free Software Foundation; either
8# version 2.1 of the License, or (at your option) any later version.
9#
10# This library is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13# Lesser General Public License for more details.
14#
15# You should have received a copy of the GNU Lesser General Public
16# License along with this library; if not, see <http://www.gnu.org/licenses/>.
17
18#
19# This file is processed by scripts/decodetree.py
20#
21# Encodings for the conditional VFP instructions are here:
22# generally anything matching A32
23#  cccc 11.. .... .... .... 101. .... ....
24# and T32
25#  1110 110. .... .... .... 101. .... ....
26#  1110 1110 .... .... .... 101. .... ....
27# (but those patterns might also cover some Neon instructions,
28# which do not live in this file.)
29
30# VFP registers have an odd encoding with a four-bit field
31# and a one-bit field which are assembled in different orders
32# depending on whether the register is double or single precision.
33# Each individual instruction function must do the checks for
34# "double register selected but CPU does not have double support"
35# and "double register number has bit 4 set but CPU does not
36# support D16-D31" (which should UNDEF).
37%vm_dp  5:1 0:4
38%vm_sp  0:4 5:1
39%vn_dp  7:1 16:4
40%vn_sp  16:4 7:1
41%vd_dp  22:1 12:4
42%vd_sp  12:4 22:1
43
44%vmov_idx_b     21:1 5:2
45%vmov_idx_h     21:1 6:1
46
47%vmov_imm 16:4 0:4
48
49@vfp_dnm_s   ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
50@vfp_dnm_d   ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
51
52@vfp_dm_ss   ................................ vm=%vm_sp vd=%vd_sp
53@vfp_dm_dd   ................................ vm=%vm_dp vd=%vd_dp
54@vfp_dm_ds   ................................ vm=%vm_sp vd=%vd_dp
55@vfp_dm_sd   ................................ vm=%vm_dp vd=%vd_sp
56
57# VMOV scalar to general-purpose register; note that this does
58# include some Neon cases.
59VMOV_to_gp   ---- 1110 u:1 1.        1 .... rt:4 1011 ... 1 0000 \
60             vn=%vn_dp size=0 index=%vmov_idx_b
61VMOV_to_gp   ---- 1110 u:1 0.        1 .... rt:4 1011 ..1 1 0000 \
62             vn=%vn_dp size=1 index=%vmov_idx_h
63VMOV_to_gp   ---- 1110 0   0 index:1 1 .... rt:4 1011 .00 1 0000 \
64             vn=%vn_dp size=2 u=0
65
66VMOV_from_gp ---- 1110 0 1.        0 .... rt:4 1011 ... 1 0000 \
67             vn=%vn_dp size=0 index=%vmov_idx_b
68VMOV_from_gp ---- 1110 0 0.        0 .... rt:4 1011 ..1 1 0000 \
69             vn=%vn_dp size=1 index=%vmov_idx_h
70VMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \
71             vn=%vn_dp size=2
72
73VDUP         ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
74             vn=%vn_dp
75
76VMSR_VMRS    ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
77VMOV_half    ---- 1110 000 l:1 .... rt:4 1001 . 001 0000    vn=%vn_sp
78VMOV_single  ---- 1110 000 l:1 .... rt:4 1010 . 001 0000    vn=%vn_sp
79
80VMOV_64_sp   ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 ....   vm=%vm_sp
81VMOV_64_dp   ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 ....   vm=%vm_dp
82
83VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8      vd=%vd_sp
84VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8      vd=%vd_sp
85VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8      vd=%vd_dp
86
87# We split the load/store multiple up into two patterns to avoid
88# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
89# grouping:
90#   P=0 U=0 W=0 is 64-bit VMOV
91#   P=1 W=0 is VLDR/VSTR
92#   P=U W=1 is UNDEF
93# leaving P=0 U=1 W=x and P=1 U=0 W=1 for load/store multiple.
94# These include FSTM/FLDM.
95VLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \
96             vd=%vd_sp p=0 u=1
97VLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \
98             vd=%vd_dp p=0 u=1
99
100VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \
101             vd=%vd_sp p=1 u=0 w=1
102VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
103             vd=%vd_dp p=1 u=0 w=1
104
105# 3-register VFP data-processing; bits [23,21:20,6] identify the operation.
106VMLA_hp      ---- 1110 0.00 .... .... 1001 .0.0 ....        @vfp_dnm_s
107VMLA_sp      ---- 1110 0.00 .... .... 1010 .0.0 ....        @vfp_dnm_s
108VMLA_dp      ---- 1110 0.00 .... .... 1011 .0.0 ....        @vfp_dnm_d
109
110VMLS_hp      ---- 1110 0.00 .... .... 1001 .1.0 ....        @vfp_dnm_s
111VMLS_sp      ---- 1110 0.00 .... .... 1010 .1.0 ....        @vfp_dnm_s
112VMLS_dp      ---- 1110 0.00 .... .... 1011 .1.0 ....        @vfp_dnm_d
113
114VNMLS_hp     ---- 1110 0.01 .... .... 1001 .0.0 ....        @vfp_dnm_s
115VNMLS_sp     ---- 1110 0.01 .... .... 1010 .0.0 ....        @vfp_dnm_s
116VNMLS_dp     ---- 1110 0.01 .... .... 1011 .0.0 ....        @vfp_dnm_d
117
118VNMLA_hp     ---- 1110 0.01 .... .... 1001 .1.0 ....        @vfp_dnm_s
119VNMLA_sp     ---- 1110 0.01 .... .... 1010 .1.0 ....        @vfp_dnm_s
120VNMLA_dp     ---- 1110 0.01 .... .... 1011 .1.0 ....        @vfp_dnm_d
121
122VMUL_hp      ---- 1110 0.10 .... .... 1001 .0.0 ....        @vfp_dnm_s
123VMUL_sp      ---- 1110 0.10 .... .... 1010 .0.0 ....        @vfp_dnm_s
124VMUL_dp      ---- 1110 0.10 .... .... 1011 .0.0 ....        @vfp_dnm_d
125
126VNMUL_hp     ---- 1110 0.10 .... .... 1001 .1.0 ....        @vfp_dnm_s
127VNMUL_sp     ---- 1110 0.10 .... .... 1010 .1.0 ....        @vfp_dnm_s
128VNMUL_dp     ---- 1110 0.10 .... .... 1011 .1.0 ....        @vfp_dnm_d
129
130VADD_hp      ---- 1110 0.11 .... .... 1001 .0.0 ....        @vfp_dnm_s
131VADD_sp      ---- 1110 0.11 .... .... 1010 .0.0 ....        @vfp_dnm_s
132VADD_dp      ---- 1110 0.11 .... .... 1011 .0.0 ....        @vfp_dnm_d
133
134VSUB_hp      ---- 1110 0.11 .... .... 1001 .1.0 ....        @vfp_dnm_s
135VSUB_sp      ---- 1110 0.11 .... .... 1010 .1.0 ....        @vfp_dnm_s
136VSUB_dp      ---- 1110 0.11 .... .... 1011 .1.0 ....        @vfp_dnm_d
137
138VDIV_hp      ---- 1110 1.00 .... .... 1001 .0.0 ....        @vfp_dnm_s
139VDIV_sp      ---- 1110 1.00 .... .... 1010 .0.0 ....        @vfp_dnm_s
140VDIV_dp      ---- 1110 1.00 .... .... 1011 .0.0 ....        @vfp_dnm_d
141
142VFMA_hp      ---- 1110 1.10 .... .... 1001 .0. 0 ....       @vfp_dnm_s
143VFMS_hp      ---- 1110 1.10 .... .... 1001 .1. 0 ....       @vfp_dnm_s
144VFNMA_hp     ---- 1110 1.01 .... .... 1001 .0. 0 ....       @vfp_dnm_s
145VFNMS_hp     ---- 1110 1.01 .... .... 1001 .1. 0 ....       @vfp_dnm_s
146
147VFMA_sp      ---- 1110 1.10 .... .... 1010 .0. 0 ....       @vfp_dnm_s
148VFMS_sp      ---- 1110 1.10 .... .... 1010 .1. 0 ....       @vfp_dnm_s
149VFNMA_sp     ---- 1110 1.01 .... .... 1010 .0. 0 ....       @vfp_dnm_s
150VFNMS_sp     ---- 1110 1.01 .... .... 1010 .1. 0 ....       @vfp_dnm_s
151
152VFMA_dp      ---- 1110 1.10 .... .... 1011 .0.0 ....        @vfp_dnm_d
153VFMS_dp      ---- 1110 1.10 .... .... 1011 .1.0 ....        @vfp_dnm_d
154VFNMA_dp     ---- 1110 1.01 .... .... 1011 .0.0 ....        @vfp_dnm_d
155VFNMS_dp     ---- 1110 1.01 .... .... 1011 .1.0 ....        @vfp_dnm_d
156
157VMOV_imm_hp  ---- 1110 1.11 .... .... 1001 0000 .... \
158             vd=%vd_sp imm=%vmov_imm
159VMOV_imm_sp  ---- 1110 1.11 .... .... 1010 0000 .... \
160             vd=%vd_sp imm=%vmov_imm
161VMOV_imm_dp  ---- 1110 1.11 .... .... 1011 0000 .... \
162             vd=%vd_dp imm=%vmov_imm
163
164VMOV_reg_sp  ---- 1110 1.11 0000 .... 1010 01.0 ....        @vfp_dm_ss
165VMOV_reg_dp  ---- 1110 1.11 0000 .... 1011 01.0 ....        @vfp_dm_dd
166
167VABS_hp      ---- 1110 1.11 0000 .... 1001 11.0 ....        @vfp_dm_ss
168VABS_sp      ---- 1110 1.11 0000 .... 1010 11.0 ....        @vfp_dm_ss
169VABS_dp      ---- 1110 1.11 0000 .... 1011 11.0 ....        @vfp_dm_dd
170
171VNEG_hp      ---- 1110 1.11 0001 .... 1001 01.0 ....        @vfp_dm_ss
172VNEG_sp      ---- 1110 1.11 0001 .... 1010 01.0 ....        @vfp_dm_ss
173VNEG_dp      ---- 1110 1.11 0001 .... 1011 01.0 ....        @vfp_dm_dd
174
175VSQRT_hp     ---- 1110 1.11 0001 .... 1001 11.0 ....        @vfp_dm_ss
176VSQRT_sp     ---- 1110 1.11 0001 .... 1010 11.0 ....        @vfp_dm_ss
177VSQRT_dp     ---- 1110 1.11 0001 .... 1011 11.0 ....        @vfp_dm_dd
178
179VCMP_hp      ---- 1110 1.11 010 z:1 .... 1001 e:1 1.0 .... \
180             vd=%vd_sp vm=%vm_sp
181VCMP_sp      ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \
182             vd=%vd_sp vm=%vm_sp
183VCMP_dp      ---- 1110 1.11 010 z:1 .... 1011 e:1 1.0 .... \
184             vd=%vd_dp vm=%vm_dp
185
186# VCVTT and VCVTB from f16: Vd format depends on size bit; Vm is always vm_sp
187VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \
188             vd=%vd_sp vm=%vm_sp
189VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \
190             vd=%vd_dp vm=%vm_sp
191
192# VCVTB and VCVTT to f16: Vd format is always vd_sp;
193# Vm format depends on size bit
194VCVT_b16_f32 ---- 1110 1.11 0011 .... 1001 t:1 1.0 .... \
195             vd=%vd_sp vm=%vm_sp
196VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \
197             vd=%vd_sp vm=%vm_sp
198VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \
199             vd=%vd_sp vm=%vm_dp
200
201VRINTR_hp    ---- 1110 1.11 0110 .... 1001 01.0 ....        @vfp_dm_ss
202VRINTR_sp    ---- 1110 1.11 0110 .... 1010 01.0 ....        @vfp_dm_ss
203VRINTR_dp    ---- 1110 1.11 0110 .... 1011 01.0 ....        @vfp_dm_dd
204
205VRINTZ_hp    ---- 1110 1.11 0110 .... 1001 11.0 ....        @vfp_dm_ss
206VRINTZ_sp    ---- 1110 1.11 0110 .... 1010 11.0 ....        @vfp_dm_ss
207VRINTZ_dp    ---- 1110 1.11 0110 .... 1011 11.0 ....        @vfp_dm_dd
208
209VRINTX_hp    ---- 1110 1.11 0111 .... 1001 01.0 ....        @vfp_dm_ss
210VRINTX_sp    ---- 1110 1.11 0111 .... 1010 01.0 ....        @vfp_dm_ss
211VRINTX_dp    ---- 1110 1.11 0111 .... 1011 01.0 ....        @vfp_dm_dd
212
213# VCVT between single and double:
214# Vm precision depends on size; Vd is its reverse
215VCVT_sp      ---- 1110 1.11 0111 .... 1010 11.0 ....        @vfp_dm_ds
216VCVT_dp      ---- 1110 1.11 0111 .... 1011 11.0 ....        @vfp_dm_sd
217
218# VCVT from integer to floating point: Vm always single; Vd depends on size
219VCVT_int_hp  ---- 1110 1.11 1000 .... 1001 s:1 1.0 .... \
220             vd=%vd_sp vm=%vm_sp
221VCVT_int_sp  ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \
222             vd=%vd_sp vm=%vm_sp
223VCVT_int_dp  ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \
224             vd=%vd_dp vm=%vm_sp
225
226# VJCVT is always dp to sp
227VJCVT        ---- 1110 1.11 1001 .... 1011 11.0 ....        @vfp_dm_sd
228
229# VCVT between floating-point and fixed-point. The immediate value
230# is in the same format as a Vm single-precision register number.
231# We assemble bits 18 (op), 16 (u) and 7 (sx) into a single opc field
232# for the convenience of the trans_VCVT_fix functions.
233%vcvt_fix_op 18:1 16:1 7:1
234VCVT_fix_hp  ---- 1110 1.11 1.1. .... 1001 .1.0 .... \
235             vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
236VCVT_fix_sp  ---- 1110 1.11 1.1. .... 1010 .1.0 .... \
237             vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
238VCVT_fix_dp  ---- 1110 1.11 1.1. .... 1011 .1.0 .... \
239             vd=%vd_dp imm=%vm_sp opc=%vcvt_fix_op
240
241# VCVT float to integer (VCVT and VCVTR): Vd always single; Vd depends on size
242VCVT_hp_int  ---- 1110 1.11 110 s:1 .... 1001 rz:1 1.0 .... \
243             vd=%vd_sp vm=%vm_sp
244VCVT_sp_int  ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \
245             vd=%vd_sp vm=%vm_sp
246VCVT_dp_int  ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
247             vd=%vd_sp vm=%vm_dp
248