1 /* 2 * AArch64 translation, common definitions. 3 * 4 * This library is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU Lesser General Public 6 * License as published by the Free Software Foundation; either 7 * version 2.1 of the License, or (at your option) any later version. 8 * 9 * This library is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU Lesser General Public 15 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef TARGET_ARM_TRANSLATE_A64_H 19 #define TARGET_ARM_TRANSLATE_A64_H 20 21 TCGv_i64 new_tmp_a64_zero(DisasContext *s); 22 TCGv_i64 cpu_reg(DisasContext *s, int reg); 23 TCGv_i64 cpu_reg_sp(DisasContext *s, int reg); 24 TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf); 25 TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf); 26 void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); 27 bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, 28 unsigned int imms, unsigned int immr); 29 bool sve_access_check(DisasContext *s); 30 bool sme_enabled_check(DisasContext *s); 31 bool sme_enabled_check_with_svcr(DisasContext *s, unsigned); 32 33 /* This function corresponds to CheckStreamingSVEEnabled. */ 34 static inline bool sme_sm_enabled_check(DisasContext *s) 35 { 36 return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK); 37 } 38 39 /* This function corresponds to CheckSMEAndZAEnabled. */ 40 static inline bool sme_za_enabled_check(DisasContext *s) 41 { 42 return sme_enabled_check_with_svcr(s, R_SVCR_ZA_MASK); 43 } 44 45 /* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */ 46 static inline bool sme_smza_enabled_check(DisasContext *s) 47 { 48 return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); 49 } 50 51 TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); 52 TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, 53 bool tag_checked, int log2_size); 54 TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, 55 bool tag_checked, int size); 56 57 /* We should have at some point before trying to access an FP register 58 * done the necessary access check, so assert that 59 * (a) we did the check and 60 * (b) we didn't then just plough ahead anyway if it failed. 61 * Print the instruction pattern in the abort message so we can figure 62 * out what we need to fix if a user encounters this problem in the wild. 63 */ 64 static inline void assert_fp_access_checked(DisasContext *s) 65 { 66 #ifdef CONFIG_DEBUG_TCG 67 if (unlikely(!s->fp_access_checked || s->fp_excp_el)) { 68 fprintf(stderr, "target-arm: FP access check missing for " 69 "instruction 0x%08x\n", s->insn); 70 abort(); 71 } 72 #endif 73 } 74 75 /* Return the offset into CPUARMState of an element of specified 76 * size, 'element' places in from the least significant end of 77 * the FP/vector register Qn. 78 */ 79 static inline int vec_reg_offset(DisasContext *s, int regno, 80 int element, MemOp size) 81 { 82 int element_size = 1 << size; 83 int offs = element * element_size; 84 #if HOST_BIG_ENDIAN 85 /* This is complicated slightly because vfp.zregs[n].d[0] is 86 * still the lowest and vfp.zregs[n].d[15] the highest of the 87 * 256 byte vector, even on big endian systems. 88 * 89 * Calculate the offset assuming fully little-endian, 90 * then XOR to account for the order of the 8-byte units. 91 * 92 * For 16 byte elements, the two 8 byte halves will not form a 93 * host int128 if the host is bigendian, since they're in the 94 * wrong order. However the only 16 byte operation we have is 95 * a move, so we can ignore this for the moment. More complicated 96 * operations will have to special case loading and storing from 97 * the zregs array. 98 */ 99 if (element_size < 8) { 100 offs ^= 8 - element_size; 101 } 102 #endif 103 offs += offsetof(CPUARMState, vfp.zregs[regno]); 104 assert_fp_access_checked(s); 105 return offs; 106 } 107 108 /* Return the offset info CPUARMState of the "whole" vector register Qn. */ 109 static inline int vec_full_reg_offset(DisasContext *s, int regno) 110 { 111 assert_fp_access_checked(s); 112 return offsetof(CPUARMState, vfp.zregs[regno]); 113 } 114 115 /* Return a newly allocated pointer to the vector register. */ 116 static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno) 117 { 118 TCGv_ptr ret = tcg_temp_new_ptr(); 119 tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno)); 120 return ret; 121 } 122 123 /* Return the byte size of the "whole" vector register, VL / 8. */ 124 static inline int vec_full_reg_size(DisasContext *s) 125 { 126 return s->vl; 127 } 128 129 /* Return the byte size of the vector register, SVL / 8. */ 130 static inline int streaming_vec_reg_size(DisasContext *s) 131 { 132 return s->svl; 133 } 134 135 /* 136 * Return the offset info CPUARMState of the predicate vector register Pn. 137 * Note for this purpose, FFR is P16. 138 */ 139 static inline int pred_full_reg_offset(DisasContext *s, int regno) 140 { 141 return offsetof(CPUARMState, vfp.pregs[regno]); 142 } 143 144 /* Return the byte size of the whole predicate register, VL / 64. */ 145 static inline int pred_full_reg_size(DisasContext *s) 146 { 147 return s->vl >> 3; 148 } 149 150 /* Return the byte size of the predicate register, SVL / 64. */ 151 static inline int streaming_pred_reg_size(DisasContext *s) 152 { 153 return s->svl >> 3; 154 } 155 156 /* 157 * Round up the size of a register to a size allowed by 158 * the tcg vector infrastructure. Any operation which uses this 159 * size may assume that the bits above pred_full_reg_size are zero, 160 * and must leave them the same way. 161 * 162 * Note that this is not needed for the vector registers as they 163 * are always properly sized for tcg vectors. 164 */ 165 static inline int size_for_gvec(int size) 166 { 167 if (size <= 8) { 168 return 8; 169 } else { 170 return QEMU_ALIGN_UP(size, 16); 171 } 172 } 173 174 static inline int pred_gvec_reg_size(DisasContext *s) 175 { 176 return size_for_gvec(pred_full_reg_size(s)); 177 } 178 179 /* Return a newly allocated pointer to the predicate register. */ 180 static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno) 181 { 182 TCGv_ptr ret = tcg_temp_new_ptr(); 183 tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno)); 184 return ret; 185 } 186 187 bool disas_sve(DisasContext *, uint32_t); 188 bool disas_sme(DisasContext *, uint32_t); 189 190 void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 191 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 192 void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 193 uint32_t rm_ofs, int64_t shift, 194 uint32_t opr_sz, uint32_t max_sz); 195 196 void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm); 197 void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm); 198 199 #endif /* TARGET_ARM_TRANSLATE_A64_H */ 200