1 /* 2 * AArch64 translation, common definitions. 3 * 4 * This library is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU Lesser General Public 6 * License as published by the Free Software Foundation; either 7 * version 2.1 of the License, or (at your option) any later version. 8 * 9 * This library is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU Lesser General Public 15 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef TARGET_ARM_TRANSLATE_A64_H 19 #define TARGET_ARM_TRANSLATE_A64_H 20 21 TCGv_i64 cpu_reg(DisasContext *s, int reg); 22 TCGv_i64 cpu_reg_sp(DisasContext *s, int reg); 23 TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf); 24 TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf); 25 void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); 26 bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, 27 unsigned int imms, unsigned int immr); 28 bool sve_access_check(DisasContext *s); 29 bool sme_enabled_check(DisasContext *s); 30 bool sme_enabled_check_with_svcr(DisasContext *s, unsigned); 31 uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs, 32 uint32_t msz, bool is_write, uint32_t data); 33 34 /* This function corresponds to CheckStreamingSVEEnabled. */ 35 static inline bool sme_sm_enabled_check(DisasContext *s) 36 { 37 return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK); 38 } 39 40 /* This function corresponds to CheckSMEAndZAEnabled. */ 41 static inline bool sme_za_enabled_check(DisasContext *s) 42 { 43 return sme_enabled_check_with_svcr(s, R_SVCR_ZA_MASK); 44 } 45 46 /* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */ 47 static inline bool sme_smza_enabled_check(DisasContext *s) 48 { 49 return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); 50 } 51 52 TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); 53 TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, 54 bool tag_checked, MemOp memop); 55 TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, 56 bool tag_checked, int total_size, MemOp memop); 57 58 /* We should have at some point before trying to access an FP register 59 * done the necessary access check, so assert that 60 * (a) we did the check and 61 * (b) we didn't then just plough ahead anyway if it failed. 62 * Print the instruction pattern in the abort message so we can figure 63 * out what we need to fix if a user encounters this problem in the wild. 64 */ 65 static inline void assert_fp_access_checked(DisasContext *s) 66 { 67 #ifdef CONFIG_DEBUG_TCG 68 if (unlikely(!s->fp_access_checked || s->fp_excp_el)) { 69 fprintf(stderr, "target-arm: FP access check missing for " 70 "instruction 0x%08x\n", s->insn); 71 abort(); 72 } 73 #endif 74 } 75 76 /* Return the offset into CPUARMState of an element of specified 77 * size, 'element' places in from the least significant end of 78 * the FP/vector register Qn. 79 */ 80 static inline int vec_reg_offset(DisasContext *s, int regno, 81 int element, MemOp size) 82 { 83 int element_size = 1 << size; 84 int offs = element * element_size; 85 #if HOST_BIG_ENDIAN 86 /* This is complicated slightly because vfp.zregs[n].d[0] is 87 * still the lowest and vfp.zregs[n].d[15] the highest of the 88 * 256 byte vector, even on big endian systems. 89 * 90 * Calculate the offset assuming fully little-endian, 91 * then XOR to account for the order of the 8-byte units. 92 * 93 * For 16 byte elements, the two 8 byte halves will not form a 94 * host int128 if the host is bigendian, since they're in the 95 * wrong order. However the only 16 byte operation we have is 96 * a move, so we can ignore this for the moment. More complicated 97 * operations will have to special case loading and storing from 98 * the zregs array. 99 */ 100 if (element_size < 8) { 101 offs ^= 8 - element_size; 102 } 103 #endif 104 offs += offsetof(CPUARMState, vfp.zregs[regno]); 105 assert_fp_access_checked(s); 106 return offs; 107 } 108 109 /* Return the offset info CPUARMState of the "whole" vector register Qn. */ 110 static inline int vec_full_reg_offset(DisasContext *s, int regno) 111 { 112 assert_fp_access_checked(s); 113 return offsetof(CPUARMState, vfp.zregs[regno]); 114 } 115 116 /* Return a newly allocated pointer to the vector register. */ 117 static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno) 118 { 119 TCGv_ptr ret = tcg_temp_new_ptr(); 120 tcg_gen_addi_ptr(ret, tcg_env, vec_full_reg_offset(s, regno)); 121 return ret; 122 } 123 124 /* Return the byte size of the "whole" vector register, VL / 8. */ 125 static inline int vec_full_reg_size(DisasContext *s) 126 { 127 return s->vl; 128 } 129 130 /* Return the byte size of the vector register, SVL / 8. */ 131 static inline int streaming_vec_reg_size(DisasContext *s) 132 { 133 return s->svl; 134 } 135 136 /* 137 * Return the offset info CPUARMState of the predicate vector register Pn. 138 * Note for this purpose, FFR is P16. 139 */ 140 static inline int pred_full_reg_offset(DisasContext *s, int regno) 141 { 142 return offsetof(CPUARMState, vfp.pregs[regno]); 143 } 144 145 /* Return the byte size of the whole predicate register, VL / 64. */ 146 static inline int pred_full_reg_size(DisasContext *s) 147 { 148 return s->vl >> 3; 149 } 150 151 /* Return the byte size of the predicate register, SVL / 64. */ 152 static inline int streaming_pred_reg_size(DisasContext *s) 153 { 154 return s->svl >> 3; 155 } 156 157 /* 158 * Round up the size of a register to a size allowed by 159 * the tcg vector infrastructure. Any operation which uses this 160 * size may assume that the bits above pred_full_reg_size are zero, 161 * and must leave them the same way. 162 * 163 * Note that this is not needed for the vector registers as they 164 * are always properly sized for tcg vectors. 165 */ 166 static inline int size_for_gvec(int size) 167 { 168 if (size <= 8) { 169 return 8; 170 } else { 171 return QEMU_ALIGN_UP(size, 16); 172 } 173 } 174 175 static inline int pred_gvec_reg_size(DisasContext *s) 176 { 177 return size_for_gvec(pred_full_reg_size(s)); 178 } 179 180 /* Return a newly allocated pointer to the predicate register. */ 181 static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno) 182 { 183 TCGv_ptr ret = tcg_temp_new_ptr(); 184 tcg_gen_addi_ptr(ret, tcg_env, pred_full_reg_offset(s, regno)); 185 return ret; 186 } 187 188 bool disas_sve(DisasContext *, uint32_t); 189 bool disas_sme(DisasContext *, uint32_t); 190 191 void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 192 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 193 void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 194 uint32_t rm_ofs, int64_t shift, 195 uint32_t opr_sz, uint32_t max_sz); 196 197 void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm); 198 void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm); 199 200 #endif /* TARGET_ARM_TRANSLATE_A64_H */ 201