xref: /openbmc/qemu/target/arm/tcg/translate-a32.h (revision 764a6ee9)
1 /*
2  *  AArch32 translation, common definitions.
3  *
4  * Copyright (c) 2021 Linaro, Ltd.
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef TARGET_ARM_TRANSLATE_A32_H
21 #define TARGET_ARM_TRANSLATE_A32_H
22 
23 /* Prototypes for autogenerated disassembler functions */
24 bool disas_m_nocp(DisasContext *dc, uint32_t insn);
25 bool disas_mve(DisasContext *dc, uint32_t insn);
26 bool disas_vfp(DisasContext *s, uint32_t insn);
27 bool disas_vfp_uncond(DisasContext *s, uint32_t insn);
28 bool disas_neon_dp(DisasContext *s, uint32_t insn);
29 bool disas_neon_ls(DisasContext *s, uint32_t insn);
30 bool disas_neon_shared(DisasContext *s, uint32_t insn);
31 
32 void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
33 void arm_gen_condlabel(DisasContext *s);
34 bool vfp_access_check(DisasContext *s);
35 bool vfp_access_check_m(DisasContext *s, bool skip_context_update);
36 void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop);
37 void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop);
38 void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop);
39 void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
40 TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
41 void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
42 void gen_set_condexec(DisasContext *s);
43 void gen_update_pc(DisasContext *s, target_long diff);
44 void gen_lookup_tb(DisasContext *s);
45 long vfp_reg_offset(bool dp, unsigned reg);
46 long neon_full_reg_offset(unsigned reg);
47 long neon_element_offset(int reg, int element, MemOp memop);
48 void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
49 void clear_eci_state(DisasContext *s);
50 bool mve_eci_check(DisasContext *s);
51 void mve_update_eci(DisasContext *s);
52 void mve_update_and_store_eci(DisasContext *s);
53 bool mve_skip_vmov(DisasContext *s, int vn, int index, int size);
54 
55 static inline TCGv_i32 load_cpu_offset(int offset)
56 {
57     TCGv_i32 tmp = tcg_temp_new_i32();
58     tcg_gen_ld_i32(tmp, tcg_env, offset);
59     return tmp;
60 }
61 
62 /* Load from a 32-bit field to a TCGv_i32 */
63 #define load_cpu_field(name)                                            \
64     ({                                                                  \
65         QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 4);        \
66         load_cpu_offset(offsetof(CPUARMState, name));                   \
67     })
68 
69 /* Load from the low half of a 64-bit field to a TCGv_i32 */
70 #define load_cpu_field_low32(name)                                      \
71     ({                                                                  \
72         QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 8);        \
73         load_cpu_offset(offsetoflow32(CPUARMState, name));              \
74     })
75 
76 void store_cpu_offset(TCGv_i32 var, int offset, int size);
77 
78 #define store_cpu_field(val, name)                                      \
79     ({                                                                  \
80         QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 4          \
81                           && sizeof_field(CPUARMState, name) != 1);     \
82         store_cpu_offset(val, offsetof(CPUARMState, name),              \
83                          sizeof_field(CPUARMState, name));              \
84     })
85 
86 /* Store to the low half of a 64-bit field from a TCGv_i32 */
87 #define store_cpu_field_low32(val, name)                                \
88     ({                                                                  \
89         QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 8);        \
90         store_cpu_offset(val, offsetoflow32(CPUARMState, name), 4);     \
91     })
92 
93 #define store_cpu_field_constant(val, name) \
94     store_cpu_field(tcg_constant_i32(val), name)
95 
96 /* Create a new temporary and set it to the value of a CPU register.  */
97 static inline TCGv_i32 load_reg(DisasContext *s, int reg)
98 {
99     TCGv_i32 tmp = tcg_temp_new_i32();
100     load_reg_var(s, tmp, reg);
101     return tmp;
102 }
103 
104 void store_reg(DisasContext *s, int reg, TCGv_i32 var);
105 
106 void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
107                               TCGv_i32 a32, int index, MemOp opc);
108 void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
109                               TCGv_i32 a32, int index, MemOp opc);
110 void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
111                               TCGv_i32 a32, int index, MemOp opc);
112 void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
113                               TCGv_i32 a32, int index, MemOp opc);
114 void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
115                      int index, MemOp opc);
116 void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
117                      int index, MemOp opc);
118 void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
119                      int index, MemOp opc);
120 void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
121                      int index, MemOp opc);
122 
123 #define DO_GEN_LD(SUFF, OPC)                                            \
124     static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
125                                          TCGv_i32 a32, int index)       \
126     {                                                                   \
127         gen_aa32_ld_i32(s, val, a32, index, OPC);                       \
128     }
129 
130 #define DO_GEN_ST(SUFF, OPC)                                            \
131     static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
132                                          TCGv_i32 a32, int index)       \
133     {                                                                   \
134         gen_aa32_st_i32(s, val, a32, index, OPC);                       \
135     }
136 
137 static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
138                                  TCGv_i32 a32, int index)
139 {
140     gen_aa32_ld_i64(s, val, a32, index, MO_UQ);
141 }
142 
143 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
144                                  TCGv_i32 a32, int index)
145 {
146     gen_aa32_st_i64(s, val, a32, index, MO_UQ);
147 }
148 
149 DO_GEN_LD(8u, MO_UB)
150 DO_GEN_LD(16u, MO_UW)
151 DO_GEN_LD(32u, MO_UL)
152 DO_GEN_ST(8, MO_UB)
153 DO_GEN_ST(16, MO_UW)
154 DO_GEN_ST(32, MO_UL)
155 
156 #undef DO_GEN_LD
157 #undef DO_GEN_ST
158 
159 #if defined(CONFIG_USER_ONLY)
160 #define IS_USER(s) 1
161 #else
162 #define IS_USER(s) (s->user)
163 #endif
164 
165 /* Set NZCV flags from the high 4 bits of var.  */
166 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
167 
168 /* Swap low and high halfwords.  */
169 static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
170 {
171     tcg_gen_rotri_i32(dest, var, 16);
172 }
173 
174 #endif
175