1# AArch64 SVE instruction descriptions 2# 3# Copyright (c) 2017 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22########################################################################### 23# Named fields. These are primarily for disjoint fields. 24 25%imm4_16_p1 16:4 !function=plus_1 26%imm6_22_5 22:1 5:5 27%imm7_22_16 22:2 16:5 28%imm8_16_10 16:5 10:3 29%imm9_16_10 16:s6 10:3 30%size_23 23:2 31%dtype_23_13 23:2 13:2 32%index3_22_19 22:1 19:2 33%index3_22_17 22:1 17:2 34%index3_19_11 19:2 11:1 35%index2_20_11 20:1 11:1 36 37# A combination of tsz:imm3 -- extract esize. 38%tszimm_esz 22:2 5:5 !function=tszimm_esz 39# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) 40%tszimm_shr 22:2 5:5 !function=tszimm_shr 41# A combination of tsz:imm3 -- extract (tsz:imm3) - esize 42%tszimm_shl 22:2 5:5 !function=tszimm_shl 43 44# Similarly for the tszh/tszl pair at 22/16 for zzi 45%tszimm16_esz 22:2 16:5 !function=tszimm_esz 46%tszimm16_shr 22:2 16:5 !function=tszimm_shr 47%tszimm16_shl 22:2 16:5 !function=tszimm_shl 48 49# Signed 8-bit immediate, optionally shifted left by 8. 50%sh8_i8s 5:9 !function=expand_imm_sh8s 51# Unsigned 8-bit immediate, optionally shifted left by 8. 52%sh8_i8u 5:9 !function=expand_imm_sh8u 53 54# Unsigned load of msz into esz=2, represented as a dtype. 55%msz_dtype 23:2 !function=msz_dtype 56 57# Either a copy of rd (at bit 0), or a different source 58# as propagated via the MOVPRFX instruction. 59%reg_movprfx 0:5 60 61%rn_ax2 6:4 !function=times_2 62 63%pnd 0:3 !function=plus_8 64%pnn 5:3 !function=plus_8 65 66########################################################################### 67# Named attribute sets. These are used to make nice(er) names 68# when creating helpers common to those for the individual 69# instruction patterns. 70 71&rr_esz rd rn esz 72&rri rd rn imm 73&rr_dbm rd rn dbm 74&rrri rd rn rm imm 75&rri_esz rd rn imm esz 76&rrri_esz rd rn rm imm esz 77&rrr_esz rd rn rm esz 78&rrx_esz rd rn rm index esz 79&rpr_esz rd pg rn esz 80&rpr_s rd pg rn s 81&rprr_s rd pg rn rm s 82&rprr_esz rd pg rn rm esz 83&rrrr_esz rd ra rn rm esz 84&rrxr_esz rd rn rm ra index esz 85&rprrr_esz rd pg rn rm ra esz 86&rpri_esz rd pg rn imm esz 87&ptrue rd esz pat s 88&incdec_cnt rd pat esz imm d u 89&incdec2_cnt rd rn pat esz imm d u 90&incdec_pred rd pg esz d u 91&incdec2_pred rd rn pg esz d u 92&rprr_load rd pg rn rm dtype nreg 93&rpri_load rd pg rn imm dtype nreg 94&rprr_store rd pg rn rm msz esz nreg 95&rpri_store rd pg rn imm msz esz nreg 96&rprr_gather_load rd pg rn rm esz msz u ff xs scale 97&rpri_gather_load rd pg rn imm esz msz u ff 98&rprr_scatter_store rd pg rn rm esz msz xs scale 99&rpri_scatter_store rd pg rn imm esz msz 100 101########################################################################### 102# Named instruction formats. These are generally used to 103# reduce the amount of duplication between instruction patterns. 104 105# Two operand with unused vector element size 106@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 107 108# Two operand 109@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz 110@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz 111@rd_rnx2 ........ ... ..... ...... ..... rd:5 &rr_esz rn=%rn_ax2 112 113# Two operand with governing predicate, flags setting 114@pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s 115@pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0 116 117# Three operand with unused vector element size 118@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 119 120# Three predicate operand, with governing predicate, flag setting 121@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s 122 123# Three operand, vector element size 124@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz 125@pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz 126@rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ 127 &rrr_esz rn=%reg_movprfx 128@rdn_rm_e0 ........ .. ...... ...... rm:5 rd:5 \ 129 &rrr_esz rn=%reg_movprfx esz=0 130@rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ 131 &rri_esz rn=%reg_movprfx imm=%sh8_i8u 132@rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ 133 &rri_esz rn=%reg_movprfx 134@rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ 135 &rri_esz rn=%reg_movprfx 136 137# Four operand, vector element size 138@rda_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 \ 139 &rrrr_esz ra=%reg_movprfx 140 141# Four operand with explicit vector element size 142@rda_rn_rm_ex ........ ... rm:5 ... ... rn:5 rd:5 \ 143 &rrrr_esz ra=%reg_movprfx 144@rdn_ra_rm_ex ........ ... rm:5 ... ... ra:5 rd:5 \ 145 &rrrr_esz rn=%reg_movprfx 146 147# Three operand with "memory" size, aka immediate left shift 148@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri 149 150# Two register operand, with governing predicate, vector element size 151@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ 152 &rprr_esz rn=%reg_movprfx 153@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ 154 &rprr_esz rm=%reg_movprfx 155@rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz 156@pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz 157 158# Three register operand, with governing predicate, vector element size 159@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ 160 &rprrr_esz ra=%reg_movprfx 161@rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ 162 &rprrr_esz rn=%reg_movprfx 163@rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \ 164 &rprrr_esz rn=%reg_movprfx 165@rd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 &rprr_esz 166 167# One register operand, with governing predicate, vector element size 168@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz 169@rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz 170@pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz 171 172# One register operand, with governing predicate, no vector element size 173@rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0 174 175# Two register operands with a 6-bit signed immediate. 176@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri 177 178# Two register operand, one immediate operand, with predicate, 179# element size encoded as TSZHL. 180@rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \ 181 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl 182@rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \ 183 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr 184 185# Similarly without predicate. 186@rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \ 187 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl 188@rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \ 189 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr 190 191# Two register operand, one immediate operand, with 4-bit predicate. 192# User must fill in imm. 193@rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ 194 &rpri_esz rn=%reg_movprfx 195 196# Two register operand, one one-bit floating-point operand. 197@rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \ 198 &rpri_esz rn=%reg_movprfx 199 200# Two register operand, one encoded bitmask. 201@rdn_dbm ........ .. .... dbm:13 rd:5 \ 202 &rr_dbm rn=%reg_movprfx 203 204# Predicate output, vector and immediate input, 205# controlling predicate, element size. 206@pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz 207@pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz 208 209# Basic Load/Store with 9-bit immediate offset 210@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ 211 &rri imm=%imm9_16_10 212@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ 213 &rri imm=%imm9_16_10 214 215# One register, pattern, and uint4+1. 216# User must fill in U and D. 217@incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ 218 &incdec_cnt imm=%imm4_16_p1 219@incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ 220 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx 221 222# One register, predicate. 223# User must fill in U and D. 224@incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred 225@incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ 226 &incdec2_pred rn=%reg_movprfx 227 228# Loads; user must fill in NREG. 229@rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load 230@rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load 231 232@rprr_load ....... .... rm:5 ... pg:3 rn:5 rd:5 &rprr_load 233@rpri_load ....... .... . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load 234 235@rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \ 236 &rprr_load dtype=%msz_dtype 237@rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \ 238 &rpri_load dtype=%msz_dtype 239 240# Gather Loads. 241@rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 242 &rprr_gather_load xs=2 243@rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 244 &rprr_gather_load 245@rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 246 &rprr_gather_load 247@rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ 248 &rprr_gather_load 249@rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 250 &rprr_gather_load xs=2 251@rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ 252 &rprr_gather_load xs=2 253@rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 254 &rpri_gather_load 255 256# Stores; user must fill in ESZ, MSZ, NREG as needed. 257@rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store 258@rpri_store ....... .. .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store 259@rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \ 260 &rprr_store nreg=0 261@rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \ 262 &rprr_scatter_store 263@rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \ 264 &rpri_scatter_store 265 266# Two registers and a scalar by N-bit index 267@rrx_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ 268 &rrx_esz index=%index3_22_19 269@rrx_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 &rrx_esz 270@rrx_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 &rrx_esz 271 272# Two registers and a scalar by N-bit index, alternate 273@rrx_3a ........ .. . .. rm:3 ...... rn:5 rd:5 \ 274 &rrx_esz index=%index3_19_11 275@rrx_2a ........ .. . . rm:4 ...... rn:5 rd:5 \ 276 &rrx_esz index=%index2_20_11 277 278# Three registers and a scalar by N-bit index 279@rrxr_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ 280 &rrxr_esz ra=%reg_movprfx index=%index3_22_19 281@rrxr_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 \ 282 &rrxr_esz ra=%reg_movprfx 283@rrxr_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 \ 284 &rrxr_esz ra=%reg_movprfx 285 286# Three registers and a scalar by N-bit index, alternate 287@rrxr_3a ........ .. ... rm:3 ...... rn:5 rd:5 \ 288 &rrxr_esz ra=%reg_movprfx index=%index3_19_11 289@rrxr_2a ........ .. .. rm:4 ...... rn:5 rd:5 \ 290 &rrxr_esz ra=%reg_movprfx index=%index2_20_11 291 292########################################################################### 293# Instruction patterns. Grouped according to the SVE encodingindex.xhtml. 294 295### SVE Integer Arithmetic - Binary Predicated Group 296 297# SVE bitwise logical vector operations (predicated) 298ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm 299EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm 300AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm 301BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm 302 303# SVE integer add/subtract vectors (predicated) 304ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm 305SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm 306SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR 307 308# SVE integer min/max/difference (predicated) 309SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm 310UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm 311SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm 312UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm 313SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm 314UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm 315 316# SVE integer multiply/divide (predicated) 317MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm 318SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm 319UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm 320# Note that divide requires size >= 2; below 2 is unallocated. 321SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm 322UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm 323SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR 324UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR 325 326### SVE Integer Reduction Group 327 328# SVE bitwise logical reduction (predicated) 329ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn 330EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn 331ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn 332 333# SVE2.1 bitwise logical reduction (quadwords) 334ORQV 00000100 .. 011 100 001 ... ..... ..... @rd_pg_rn 335EORQV 00000100 .. 011 101 001 ... ..... ..... @rd_pg_rn 336ANDQV 00000100 .. 011 110 001 ... ..... ..... @rd_pg_rn 337 338# SVE constructive prefix (predicated) 339MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn 340MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn 341 342# SVE integer add reduction (predicated) 343# Note that saddv requires size != 3. 344UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn 345SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn 346 347# SVE integer min/max reduction (predicated) 348SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn 349UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn 350SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn 351UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn 352 353# SVE2.1 segment reduction 354ADDQV 00000100 .. 000 101 001 ... ..... ..... @rd_pg_rn 355SMAXQV 00000100 .. 001 100 001 ... ..... ..... @rd_pg_rn 356SMINQV 00000100 .. 001 110 001 ... ..... ..... @rd_pg_rn 357UMAXQV 00000100 .. 001 101 001 ... ..... ..... @rd_pg_rn 358UMINQV 00000100 .. 001 111 001 ... ..... ..... @rd_pg_rn 359 360### SVE Shift by Immediate - Predicated Group 361 362# SVE bitwise shift by immediate (predicated) 363ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr 364LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr 365LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl 366ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr 367SQSHL_zpzi 00000100 .. 000 110 100 ... .. ... ..... @rdn_pg_tszimm_shl 368UQSHL_zpzi 00000100 .. 000 111 100 ... .. ... ..... @rdn_pg_tszimm_shl 369SRSHR 00000100 .. 001 100 100 ... .. ... ..... @rdn_pg_tszimm_shr 370URSHR 00000100 .. 001 101 100 ... .. ... ..... @rdn_pg_tszimm_shr 371SQSHLU 00000100 .. 001 111 100 ... .. ... ..... @rdn_pg_tszimm_shl 372 373# SVE bitwise shift by vector (predicated) 374ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm 375LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm 376LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm 377ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR 378LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR 379LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR 380 381# SVE bitwise shift by wide elements (predicated) 382# Note these require size != 3. 383ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm 384LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm 385LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm 386 387### SVE Integer Arithmetic - Unary Predicated Group 388 389# SVE unary bit operations (predicated) 390# Note esz != 0 for FABS and FNEG. 391CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn 392CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn 393CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn 394CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn 395NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn 396FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn 397FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn 398 399# SVE integer unary operations (predicated) 400# Note esz > original size for extensions. 401ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn 402NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn 403SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn 404UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn 405SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn 406UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn 407SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn 408UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn 409 410### SVE Floating Point Compare - Vectors Group 411 412# SVE floating-point compare vectors 413FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm 414FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm 415FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm 416FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm 417FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm 418FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm 419FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm 420 421### SVE Integer Multiply-Add Group 422 423# SVE integer multiply-add writing addend (predicated) 424MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm 425MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm 426 427# SVE integer multiply-add writing multiplicand (predicated) 428MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD 429MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB 430 431### SVE Integer Arithmetic - Unpredicated Group 432 433# SVE integer add/subtract vectors (unpredicated) 434ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm 435SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm 436SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm 437UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm 438SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm 439UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm 440 441### SVE Logical - Unpredicated Group 442 443# SVE bitwise logical operations (unpredicated) 444AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 445ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 446EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 447BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 448 449XAR 00000100 .. 1 ..... 001 101 rm:5 rd:5 &rrri_esz \ 450 rn=%reg_movprfx esz=%tszimm16_esz imm=%tszimm16_shr 451 452# SVE2 bitwise ternary operations 453EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_ex esz=0 454BSL 00000100 00 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0 455BCAX 00000100 01 1 ..... 001 110 ..... ..... @rdn_ra_rm_ex esz=0 456BSL1N 00000100 01 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0 457BSL2N 00000100 10 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0 458NBSL 00000100 11 1 ..... 001 111 ..... ..... @rdn_ra_rm_ex esz=0 459 460### SVE Index Generation Group 461 462# SVE index generation (immediate start, immediate increment) 463INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 464 465# SVE index generation (immediate start, register increment) 466INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 467 468# SVE index generation (register start, immediate increment) 469INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 470 471# SVE index generation (register start, register increment) 472INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm 473 474### SVE / Streaming SVE Stack Allocation Group 475 476# SVE stack frame adjustment 477ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 478ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6 479ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 480ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6 481 482# SVE stack frame size 483RDVL 00000100 101 11111 01010 imm:s6 rd:5 484RDSVL 00000100 101 11111 01011 imm:s6 rd:5 485 486### SVE Bitwise Shift - Unpredicated Group 487 488# SVE bitwise shift by immediate (unpredicated) 489ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr 490LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr 491LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl 492 493# SVE bitwise shift by wide elements (unpredicated) 494# Note esz != 3 495ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm 496LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm 497LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm 498 499### SVE Compute Vector Address Group 500 501# SVE vector address generation 502ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 503ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 504ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 505ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 506 507### SVE Integer Misc - Unpredicated Group 508 509# SVE constructive prefix (unpredicated) 510MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5 511 512# SVE floating-point exponential accelerator 513# Note esz != 0 514FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn 515 516# SVE floating-point trig select coefficient 517# Note esz != 0 518FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm 519 520### SVE Element Count Group 521 522# SVE element count 523CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 524 525# SVE inc/dec register by element count 526INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 527 528# SVE saturating inc/dec register by element count 529SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt 530SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt 531 532# SVE inc/dec vector by element count 533# Note this requires esz != 0. 534INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 535 536# SVE saturating inc/dec vector by element count 537# Note these require esz != 0. 538SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt 539 540### SVE Bitwise Immediate Group 541 542# SVE bitwise logical with immediate (unpredicated) 543ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm 544EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm 545AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm 546 547# SVE broadcast bitmask immediate 548DUPM 00000101 11 0000 dbm:13 rd:5 549 550### SVE Integer Wide Immediate - Predicated Group 551 552# SVE copy floating-point immediate (predicated) 553FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 554 555# SVE copy integer immediate (predicated) 556{ 557 INVALID 00000101 00 01 ---- 01 1 -------- ----- 558 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s 559} 560{ 561 INVALID 00000101 00 01 ---- 00 1 -------- ----- 562 CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s 563} 564 565### SVE Permute - Extract Group 566 567# SVE extract vector (destructive) 568EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ 569 &rrri rn=%reg_movprfx imm=%imm8_16_10 570 571# SVE2 extract vector (constructive) 572EXT_sve2 00000101 011 ..... 000 ... rn:5 rd:5 \ 573 &rri imm=%imm8_16_10 574 575### SVE Permute - Unpredicated Group 576 577# SVE broadcast general register 578DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn 579 580# SVE broadcast indexed element 581DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ 582 &rri imm=%imm7_22_16 583 584# SVE Permute Vector - one source quadwords 585DUPQ 00000101 001 imm:4 1 001001 rn:5 rd:5 &rri_esz esz=0 586DUPQ 00000101 001 imm:3 10 001001 rn:5 rd:5 &rri_esz esz=1 587DUPQ 00000101 001 imm:2 100 001001 rn:5 rd:5 &rri_esz esz=2 588DUPQ 00000101 001 imm:1 1000 001001 rn:5 rd:5 &rri_esz esz=3 589 590EXTQ 00000101 0110 imm:4 001001 rn:5 rd:5 &rri 591 592# SVE insert SIMD&FP scalar register 593INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm 594 595# SVE insert general register 596INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm 597 598# SVE reverse vector elements 599REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn 600 601# SVE move predicate to/from vector 602 603PMOV_pv 00000101 00 101 01 0001110 rn:5 0 rd:4 \ 604 &rri_esz esz=0 imm=0 605PMOV_pv 00000101 00 101 1 imm:1 0001110 rn:5 0 rd:4 &rri_esz esz=1 606PMOV_pv 00000101 01 101 imm:2 0001110 rn:5 0 rd:4 &rri_esz esz=2 607PMOV_pv 00000101 1. 101 .. 0001110 rn:5 0 rd:4 \ 608 &rri_esz esz=3 imm=%index3_22_17 609 610PMOV_vp 00000101 00 101 01 1001110 0 rn:4 rd:5 \ 611 &rri_esz esz=0 imm=0 612PMOV_vp 00000101 00 101 1 imm:1 1001110 0 rn:4 rd:5 &rri_esz esz=1 613PMOV_vp 00000101 01 101 imm:2 1001110 0 rn:4 rd:5 &rri_esz esz=2 614PMOV_vp 00000101 1. 101 .. 1001110 0 rn:4 rd:5 \ 615 &rri_esz esz=3 imm=%index3_22_17 616 617# SVE vector table lookup 618TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm 619 620# SVE unpack vector elements 621UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 622 623# SVE2 Table Lookup (three sources) 624 625TBL_sve2 00000101 .. 1 ..... 001010 ..... ..... @rd_rn_rm 626TBX 00000101 .. 1 ..... 001011 ..... ..... @rd_rn_rm 627 628### SVE Permute - Predicates Group 629 630# SVE permute predicate elements 631ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm 632ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm 633UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm 634UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm 635TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm 636TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm 637 638# SVE reverse predicate elements 639REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn 640 641# SVE unpack predicate elements 642PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 643PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 644 645### SVE Permute - Interleaving Group 646 647# SVE permute vector elements 648ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm 649ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm 650UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm 651UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm 652TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm 653TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm 654 655# SVE2 permute vector segments 656ZIP1_q 00000101 10 1 ..... 000 000 ..... ..... @rd_rn_rm_e0 657ZIP2_q 00000101 10 1 ..... 000 001 ..... ..... @rd_rn_rm_e0 658UZP1_q 00000101 10 1 ..... 000 010 ..... ..... @rd_rn_rm_e0 659UZP2_q 00000101 10 1 ..... 000 011 ..... ..... @rd_rn_rm_e0 660TRN1_q 00000101 10 1 ..... 000 110 ..... ..... @rd_rn_rm_e0 661TRN2_q 00000101 10 1 ..... 000 111 ..... ..... @rd_rn_rm_e0 662 663# SVE2.1 permute vector elements (quadwords) 664ZIPQ1 01000100 .. 0 ..... 111 000 ..... ..... @rd_rn_rm 665ZIPQ2 01000100 .. 0 ..... 111 001 ..... ..... @rd_rn_rm 666UZPQ1 01000100 .. 0 ..... 111 010 ..... ..... @rd_rn_rm 667UZPQ2 01000100 .. 0 ..... 111 011 ..... ..... @rd_rn_rm 668 669TBLQ 01000100 .. 0 ..... 111 110 ..... ..... @rd_rn_rm 670TBXQ 00000101 .. 1 ..... 001 101 ..... ..... @rd_rn_rm 671 672### SVE Permute - Predicated Group 673 674# SVE compress active elements 675# Note esz >= 2 676COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn 677 678# SVE conditionally broadcast element to vector 679CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm 680CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm 681 682# SVE conditionally copy element to SIMD&FP scalar 683CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn 684CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn 685 686# SVE conditionally copy element to general register 687CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn 688CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn 689 690# SVE copy element to SIMD&FP scalar register 691LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn 692LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn 693 694# SVE copy element to general register 695LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn 696LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn 697 698# SVE copy element from SIMD&FP scalar register 699CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn 700 701# SVE copy element from general register to vector (predicated) 702CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn 703 704# SVE reverse within elements 705# Note esz >= operation size 706REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn 707REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn 708REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn 709RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn 710REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_e0 711 712# SVE vector splice (predicated, destructive) 713SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm 714 715# SVE2 vector splice (predicated, constructive) 716SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn 717 718### SVE Select Vectors Group 719 720# SVE select vector elements (predicated) 721SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm 722 723### SVE Integer Compare - Vectors Group 724 725# SVE integer compare_vectors 726CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm 727CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm 728CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm 729CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm 730CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm 731CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm 732 733# SVE integer compare with wide elements 734# Note these require esz != 3. 735CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm 736CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm 737CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm 738CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm 739CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm 740CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm 741CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm 742CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm 743CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm 744CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm 745 746### SVE Integer Compare - Unsigned Immediate Group 747 748# SVE integer compare with unsigned immediate 749CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 750CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 751CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 752CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 753 754### SVE Integer Compare - Signed Immediate Group 755 756# SVE integer compare with signed immediate 757CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 758CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 759CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 760CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 761CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 762CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 763 764### SVE Predicate Logical Operations Group 765 766# SVE predicate logical operations 767AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s 768BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s 769EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s 770SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s 771ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s 772ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s 773NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s 774NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s 775 776### SVE Predicate Misc Group 777 778# SVE predicate test 779PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 780 781# SVE predicate initialize 782PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 783PTRUE_cnt 00100101 esz:2 1000000111100000010 ... rd=%pnd 784 785# SVE initialize FFR 786SETFFR 00100101 0010 1100 1001 0000 0000 0000 787 788# SVE zero predicate register 789PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 790 791# SVE predicate read from FFR (predicated) 792RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 793 794# SVE predicate read from FFR (unpredicated) 795RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 796 797# SVE FFR write from predicate (WRFFR) 798WRFFR 00100101 0010 1000 1001 000 rn:4 00000 799 800# SVE predicate first active 801PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 802 803# SVE predicate next active 804PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn 805 806### SVE Partition Break Group 807 808# SVE propagate break from previous partition 809BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s 810BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s 811 812# SVE partition break condition 813BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s 814BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s 815BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 816BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 817 818# SVE propagate break to next partition 819BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s 820 821### SVE Predicate Count Group 822 823# SVE predicate count 824CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn 825CNTP_c 00100101 esz:2 100 000 10 000 vl:1 1 rn:4 rd:5 826 827# SVE inc/dec register by predicate count 828INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 829 830# SVE inc/dec vector by predicate count 831INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 832 833# SVE saturating inc/dec register by predicate count 834SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred 835SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred 836 837# SVE saturating inc/dec vector by predicate count 838SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred 839 840### SVE Integer Compare - Scalars Group 841 842# SVE conditionally terminate scalars 843CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 844 845# SVE integer compare scalar count and limit 846&while esz rd rn rm sf u eq 847WHILE_lt 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 &while 848WHILE_gt 00100101 esz:2 1 rm:5 000 sf:1 u:1 0 rn:5 eq:1 rd:4 &while 849 850# SVE2 pointer conflict compare 851WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4 852 853# SVE2.1 predicate pair 854%pd_pair 1:3 !function=times_2 855@while_pair ........ esz:2 . rm:5 .... u:1 . rn:5 . ... eq:1 \ 856 &while rd=%pd_pair sf=1 857 858WHILE_lt_pair 00100101 .. 1 ..... 0101 . 1 ..... 1 ... . @while_pair 859WHILE_gt_pair 00100101 .. 1 ..... 0101 . 0 ..... 1 ... . @while_pair 860 861# SVE2.1 predicate as count 862@while_cnt ........ esz:2 . rm:5 .... u:1 . rn:5 . eq:1 ... \ 863 &while rd=%pnd sf=1 864 865WHILE_lt_cnt2 00100101 .. 1 ..... 0100 . 1 ..... 1 . ... @while_cnt 866WHILE_lt_cnt4 00100101 .. 1 ..... 0110 . 1 ..... 1 . ... @while_cnt 867WHILE_gt_cnt2 00100101 .. 1 ..... 0100 . 0 ..... 1 . ... @while_cnt 868WHILE_gt_cnt4 00100101 .. 1 ..... 0110 . 0 ..... 1 . ... @while_cnt 869 870# SVE2.1 extract mask predicate from predicate-as-counter 871&pext rd rn esz imm 872PEXT_1 00100101 esz:2 1 00000 0111 00 imm:2 ... 1 rd:4 &pext rn=%pnn 873PEXT_2 00100101 esz:2 1 00000 0111 010 imm:1 ... 1 rd:4 &pext rn=%pnn 874 875### SVE Integer Wide Immediate - Unpredicated Group 876 877# SVE broadcast floating-point immediate (unpredicated) 878FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 879 880# SVE broadcast integer immediate (unpredicated) 881{ 882 INVALID 00100101 00 111 00 011 1 -------- ----- 883 DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s 884} 885 886# SVE integer add/subtract immediate (unpredicated) 887{ 888 INVALID 00100101 00 100 000 11 1 -------- ----- 889 ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u 890} 891{ 892 INVALID 00100101 00 100 001 11 1 -------- ----- 893 SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u 894} 895{ 896 INVALID 00100101 00 100 011 11 1 -------- ----- 897 SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u 898} 899{ 900 INVALID 00100101 00 100 100 11 1 -------- ----- 901 SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u 902} 903{ 904 INVALID 00100101 00 100 101 11 1 -------- ----- 905 UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u 906} 907{ 908 INVALID 00100101 00 100 110 11 1 -------- ----- 909 SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u 910} 911{ 912 INVALID 00100101 00 100 111 11 1 -------- ----- 913 UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u 914} 915 916# SVE integer min/max immediate (unpredicated) 917SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s 918UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u 919SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s 920UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u 921 922# SVE integer multiply immediate (unpredicated) 923MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s 924 925# SVE integer dot product (unpredicated) 926DOT_zzzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 \ 927 ra=%reg_movprfx 928 929# SVE2 complex dot product (vectors) 930CDOT_zzzz 01000100 esz:2 0 rm:5 0001 rot:2 rn:5 rd:5 ra=%reg_movprfx 931 932#### SVE Multiply - Indexed 933 934# SVE integer dot product (indexed) 935SDOT_zzxw_4s 01000100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 936SDOT_zzxw_4d 01000100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 937UDOT_zzxw_4s 01000100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 938UDOT_zzxw_4d 01000100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 939 940SDOT_zzxw_2s 01000100 10 0 ..... 110010 ..... ..... @rrxr_2 esz=2 941UDOT_zzxw_2s 01000100 10 0 ..... 110011 ..... ..... @rrxr_2 esz=2 942 943# SVE2 integer multiply-add (indexed) 944MLA_zzxz_h 01000100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=1 945MLA_zzxz_s 01000100 10 1 ..... 000010 ..... ..... @rrxr_2 esz=2 946MLA_zzxz_d 01000100 11 1 ..... 000010 ..... ..... @rrxr_1 esz=3 947MLS_zzxz_h 01000100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=1 948MLS_zzxz_s 01000100 10 1 ..... 000011 ..... ..... @rrxr_2 esz=2 949MLS_zzxz_d 01000100 11 1 ..... 000011 ..... ..... @rrxr_1 esz=3 950 951# SVE2 saturating multiply-add high (indexed) 952SQRDMLAH_zzxz_h 01000100 0. 1 ..... 000100 ..... ..... @rrxr_3 esz=1 953SQRDMLAH_zzxz_s 01000100 10 1 ..... 000100 ..... ..... @rrxr_2 esz=2 954SQRDMLAH_zzxz_d 01000100 11 1 ..... 000100 ..... ..... @rrxr_1 esz=3 955SQRDMLSH_zzxz_h 01000100 0. 1 ..... 000101 ..... ..... @rrxr_3 esz=1 956SQRDMLSH_zzxz_s 01000100 10 1 ..... 000101 ..... ..... @rrxr_2 esz=2 957SQRDMLSH_zzxz_d 01000100 11 1 ..... 000101 ..... ..... @rrxr_1 esz=3 958 959# SVE mixed sign dot product (indexed) 960USDOT_zzxw_4s 01000100 10 1 ..... 000110 ..... ..... @rrxr_2 esz=2 961SUDOT_zzxw_4s 01000100 10 1 ..... 000111 ..... ..... @rrxr_2 esz=2 962 963# SVE2 saturating multiply-add (indexed) 964SQDMLALB_zzxw_s 01000100 10 1 ..... 0010.0 ..... ..... @rrxr_3a esz=2 965SQDMLALB_zzxw_d 01000100 11 1 ..... 0010.0 ..... ..... @rrxr_2a esz=3 966SQDMLALT_zzxw_s 01000100 10 1 ..... 0010.1 ..... ..... @rrxr_3a esz=2 967SQDMLALT_zzxw_d 01000100 11 1 ..... 0010.1 ..... ..... @rrxr_2a esz=3 968SQDMLSLB_zzxw_s 01000100 10 1 ..... 0011.0 ..... ..... @rrxr_3a esz=2 969SQDMLSLB_zzxw_d 01000100 11 1 ..... 0011.0 ..... ..... @rrxr_2a esz=3 970SQDMLSLT_zzxw_s 01000100 10 1 ..... 0011.1 ..... ..... @rrxr_3a esz=2 971SQDMLSLT_zzxw_d 01000100 11 1 ..... 0011.1 ..... ..... @rrxr_2a esz=3 972 973# SVE2 complex integer dot product (indexed) 974CDOT_zzxw_s 01000100 10 1 index:2 rm:3 0100 rot:2 rn:5 rd:5 \ 975 ra=%reg_movprfx 976CDOT_zzxw_d 01000100 11 1 index:1 rm:4 0100 rot:2 rn:5 rd:5 \ 977 ra=%reg_movprfx 978 979# SVE2 complex integer multiply-add (indexed) 980CMLA_zzxz_h 01000100 10 1 index:2 rm:3 0110 rot:2 rn:5 rd:5 \ 981 ra=%reg_movprfx 982CMLA_zzxz_s 01000100 11 1 index:1 rm:4 0110 rot:2 rn:5 rd:5 \ 983 ra=%reg_movprfx 984 985# SVE2 complex saturating integer multiply-add (indexed) 986SQRDCMLAH_zzxz_h 01000100 10 1 index:2 rm:3 0111 rot:2 rn:5 rd:5 \ 987 ra=%reg_movprfx 988SQRDCMLAH_zzxz_s 01000100 11 1 index:1 rm:4 0111 rot:2 rn:5 rd:5 \ 989 ra=%reg_movprfx 990 991# SVE2 multiply-add long (indexed) 992SMLALB_zzxw_s 01000100 10 1 ..... 1000.0 ..... ..... @rrxr_3a esz=2 993SMLALB_zzxw_d 01000100 11 1 ..... 1000.0 ..... ..... @rrxr_2a esz=3 994SMLALT_zzxw_s 01000100 10 1 ..... 1000.1 ..... ..... @rrxr_3a esz=2 995SMLALT_zzxw_d 01000100 11 1 ..... 1000.1 ..... ..... @rrxr_2a esz=3 996UMLALB_zzxw_s 01000100 10 1 ..... 1001.0 ..... ..... @rrxr_3a esz=2 997UMLALB_zzxw_d 01000100 11 1 ..... 1001.0 ..... ..... @rrxr_2a esz=3 998UMLALT_zzxw_s 01000100 10 1 ..... 1001.1 ..... ..... @rrxr_3a esz=2 999UMLALT_zzxw_d 01000100 11 1 ..... 1001.1 ..... ..... @rrxr_2a esz=3 1000SMLSLB_zzxw_s 01000100 10 1 ..... 1010.0 ..... ..... @rrxr_3a esz=2 1001SMLSLB_zzxw_d 01000100 11 1 ..... 1010.0 ..... ..... @rrxr_2a esz=3 1002SMLSLT_zzxw_s 01000100 10 1 ..... 1010.1 ..... ..... @rrxr_3a esz=2 1003SMLSLT_zzxw_d 01000100 11 1 ..... 1010.1 ..... ..... @rrxr_2a esz=3 1004UMLSLB_zzxw_s 01000100 10 1 ..... 1011.0 ..... ..... @rrxr_3a esz=2 1005UMLSLB_zzxw_d 01000100 11 1 ..... 1011.0 ..... ..... @rrxr_2a esz=3 1006UMLSLT_zzxw_s 01000100 10 1 ..... 1011.1 ..... ..... @rrxr_3a esz=2 1007UMLSLT_zzxw_d 01000100 11 1 ..... 1011.1 ..... ..... @rrxr_2a esz=3 1008 1009# SVE2 integer multiply long (indexed) 1010SMULLB_zzx_s 01000100 10 1 ..... 1100.0 ..... ..... @rrx_3a esz=2 1011SMULLB_zzx_d 01000100 11 1 ..... 1100.0 ..... ..... @rrx_2a esz=3 1012SMULLT_zzx_s 01000100 10 1 ..... 1100.1 ..... ..... @rrx_3a esz=2 1013SMULLT_zzx_d 01000100 11 1 ..... 1100.1 ..... ..... @rrx_2a esz=3 1014UMULLB_zzx_s 01000100 10 1 ..... 1101.0 ..... ..... @rrx_3a esz=2 1015UMULLB_zzx_d 01000100 11 1 ..... 1101.0 ..... ..... @rrx_2a esz=3 1016UMULLT_zzx_s 01000100 10 1 ..... 1101.1 ..... ..... @rrx_3a esz=2 1017UMULLT_zzx_d 01000100 11 1 ..... 1101.1 ..... ..... @rrx_2a esz=3 1018 1019# SVE2 saturating multiply (indexed) 1020SQDMULLB_zzx_s 01000100 10 1 ..... 1110.0 ..... ..... @rrx_3a esz=2 1021SQDMULLB_zzx_d 01000100 11 1 ..... 1110.0 ..... ..... @rrx_2a esz=3 1022SQDMULLT_zzx_s 01000100 10 1 ..... 1110.1 ..... ..... @rrx_3a esz=2 1023SQDMULLT_zzx_d 01000100 11 1 ..... 1110.1 ..... ..... @rrx_2a esz=3 1024 1025# SVE2 saturating multiply high (indexed) 1026SQDMULH_zzx_h 01000100 0. 1 ..... 111100 ..... ..... @rrx_3 esz=1 1027SQDMULH_zzx_s 01000100 10 1 ..... 111100 ..... ..... @rrx_2 esz=2 1028SQDMULH_zzx_d 01000100 11 1 ..... 111100 ..... ..... @rrx_1 esz=3 1029SQRDMULH_zzx_h 01000100 0. 1 ..... 111101 ..... ..... @rrx_3 esz=1 1030SQRDMULH_zzx_s 01000100 10 1 ..... 111101 ..... ..... @rrx_2 esz=2 1031SQRDMULH_zzx_d 01000100 11 1 ..... 111101 ..... ..... @rrx_1 esz=3 1032 1033# SVE2 integer multiply (indexed) 1034MUL_zzx_h 01000100 0. 1 ..... 111110 ..... ..... @rrx_3 esz=1 1035MUL_zzx_s 01000100 10 1 ..... 111110 ..... ..... @rrx_2 esz=2 1036MUL_zzx_d 01000100 11 1 ..... 111110 ..... ..... @rrx_1 esz=3 1037 1038# SVE floating-point complex add (predicated) 1039FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \ 1040 rn=%reg_movprfx 1041 1042# SVE floating-point complex multiply-add (predicated) 1043FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \ 1044 ra=%reg_movprfx 1045 1046# SVE floating-point complex multiply-add (indexed) 1047FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \ 1048 ra=%reg_movprfx esz=1 1049FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \ 1050 ra=%reg_movprfx esz=2 1051 1052### SVE FP Multiply-Add Indexed Group 1053 1054# SVE floating-point multiply-add (indexed) 1055FMLA_zzxz 01100100 0. 1 ..... 000000 ..... ..... @rrxr_3 esz=1 1056FMLA_zzxz 01100100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 1057FMLA_zzxz 01100100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 1058FMLS_zzxz 01100100 0. 1 ..... 000001 ..... ..... @rrxr_3 esz=1 1059FMLS_zzxz 01100100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 1060FMLS_zzxz 01100100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 1061 1062### SVE FP Multiply Indexed Group 1063 1064# SVE floating-point multiply (indexed) 1065FMUL_zzx 01100100 0. 1 ..... 001000 ..... ..... @rrx_3 esz=1 1066FMUL_zzx 01100100 10 1 ..... 001000 ..... ..... @rrx_2 esz=2 1067FMUL_zzx 01100100 11 1 ..... 001000 ..... ..... @rrx_1 esz=3 1068 1069### SVE FP Fast Reduction Group 1070 1071FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn 1072FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn 1073FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn 1074FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn 1075FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn 1076 1077### SVE FP recursive reduction (quadwords) 1078 1079FADDQV 01100100 .. 010 000 101 ... ..... ..... @rd_pg_rn 1080FMAXNMQV 01100100 .. 010 100 101 ... ..... ..... @rd_pg_rn 1081FMINNMQV 01100100 .. 010 101 101 ... ..... ..... @rd_pg_rn 1082FMAXQV 01100100 .. 010 110 101 ... ..... ..... @rd_pg_rn 1083FMINQV 01100100 .. 010 111 101 ... ..... ..... @rd_pg_rn 1084 1085## SVE Floating Point Unary Operations - Unpredicated Group 1086 1087FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn 1088FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn 1089 1090### SVE FP Compare with Zero Group 1091 1092FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn 1093FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn 1094FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn 1095FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn 1096FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn 1097FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn 1098 1099### SVE FP Accumulating Reduction Group 1100 1101# SVE floating-point serial reduction (predicated) 1102FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm 1103 1104### SVE Floating Point Arithmetic - Unpredicated Group 1105 1106# SVE floating-point arithmetic (unpredicated) 1107FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm 1108FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm 1109FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm 1110FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm 1111FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm 1112FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm 1113 1114### SVE FP Arithmetic Predicated Group 1115 1116# SVE floating-point arithmetic (predicated) 1117FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm 1118FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm 1119FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm 1120FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR 1121FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm 1122FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm 1123FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm 1124FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm 1125FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm 1126FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm 1127FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm 1128FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR 1129FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm 1130 1131# SVE floating-point arithmetic with immediate (predicated) 1132FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1 1133FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1 1134FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1 1135FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1 1136FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1 1137FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1 1138FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1 1139FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1 1140 1141# SVE floating-point trig multiply-add coefficient 1142FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx 1143 1144### SVE FP Multiply-Add Group 1145 1146# SVE floating-point multiply-accumulate writing addend 1147FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm 1148FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm 1149FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm 1150FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm 1151 1152# SVE floating-point multiply-accumulate writing multiplicand 1153# Alter the operand extraction order and reuse the helpers from above. 1154# FMAD, FMSB, FNMAD, FNMS 1155FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra 1156FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra 1157FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra 1158FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra 1159 1160### SVE FP Unary Operations Predicated Group 1161 1162# SVE floating-point convert precision 1163FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 1164FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 1165BFCVT 01100101 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1166FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0 1167FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0 1168FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1169FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 1170 1171# SVE floating-point convert to integer 1172FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0 1173FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0 1174FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 1175FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 1176FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 1177FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 1178FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 1179FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 1180FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0 1181FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0 1182FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 1183FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 1184FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 1185FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 1186 1187# SVE floating-point round to integral value 1188FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn 1189FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn 1190FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn 1191FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn 1192FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn 1193FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn 1194FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn 1195 1196# SVE floating-point unary operations 1197FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn 1198FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn 1199 1200# SVE integer convert to floating-point 1201SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 1202SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 1203SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 1204SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 1205SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0 1206SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 1207SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 1208 1209UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0 1210UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 1211UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 1212UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 1213UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0 1214UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 1215UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 1216 1217### SVE Memory - 32-bit Gather and Unsized Contiguous Group 1218 1219# SVE load predicate register 1220LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 1221 1222# SVE load vector register 1223LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 1224 1225# SVE load and broadcast element 1226LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \ 1227 &rpri_load dtype=%dtype_23_13 nreg=0 1228 1229# SVE 32-bit gather load (scalar plus 32-bit unscaled offsets) 1230# SVE 32-bit gather load (scalar plus 32-bit scaled offsets) 1231LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \ 1232 @rprr_g_load_xs_u esz=2 msz=0 scale=0 1233LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \ 1234 @rprr_g_load_xs_u_sc esz=2 msz=1 1235LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \ 1236 @rprr_g_load_xs_sc esz=2 msz=2 u=1 1237 1238# SVE 32-bit gather load (vector plus immediate) 1239LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \ 1240 @rpri_g_load esz=2 1241 1242### SVE Memory Contiguous Load Group 1243 1244# SVE contiguous load (scalar plus scalar) 1245LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0 1246# LD1W (128-bit element) 1247LD_zprr 1010010 1000 rm:5 100 pg:3 rn:5 rd:5 \ 1248 &rprr_load dtype=16 nreg=0 1249# LD1D (128-bit element) 1250LD_zprr 1010010 1100 rm:5 100 pg:3 rn:5 rd:5 \ 1251 &rprr_load dtype=17 nreg=0 1252 1253# SVE contiguous first-fault load (scalar plus scalar) 1254LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0 1255 1256# SVE contiguous load (scalar plus immediate) 1257LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0 1258# LD1W (128-bit element) 1259LD_zpri 1010010 1000 1 imm:s4 001 pg:3 rn:5 rd:5 \ 1260 &rpri_load dtype=16 nreg=0 1261# LD1D (128-bit element) 1262LD_zpri 1010010 1100 1 imm:s4 001 pg:3 rn:5 rd:5 \ 1263 &rpri_load dtype=17 nreg=0 1264 1265# SVE contiguous non-fault load (scalar plus immediate) 1266LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0 1267 1268# SVE contiguous non-temporal load (scalar plus scalar) 1269# LDNT1B, LDNT1H, LDNT1W, LDNT1D 1270# SVE load multiple structures (scalar plus scalar) 1271# LD2B, LD2H, LD2W, LD2D; etc. 1272LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz 1273# LD[234]Q 1274LD_zprr 1010010 01 01 ..... 100 ... ..... ..... \ 1275 @rprr_load dtype=18 nreg=1 1276LD_zprr 1010010 10 01 ..... 100 ... ..... ..... \ 1277 @rprr_load dtype=18 nreg=2 1278LD_zprr 1010010 11 01 ..... 100 ... ..... ..... \ 1279 @rprr_load dtype=18 nreg=3 1280 1281# SVE contiguous non-temporal load (scalar plus immediate) 1282# LDNT1B, LDNT1H, LDNT1W, LDNT1D 1283# SVE load multiple structures (scalar plus immediate) 1284# LD2B, LD2H, LD2W, LD2D; etc. 1285LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz 1286# LD[234]Q 1287LD_zpri 1010010 01 001 .... 111 ... ..... ..... \ 1288 @rpri_load dtype=18 nreg=1 1289LD_zpri 1010010 10 001 .... 111 ... ..... ..... \ 1290 @rpri_load dtype=18 nreg=2 1291LD_zpri 1010010 11 001 .... 111 ... ..... ..... \ 1292 @rpri_load dtype=18 nreg=3 1293 1294# SVE load and broadcast quadword (scalar plus scalar) 1295LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ 1296 @rprr_load_msz nreg=0 1297LD1RO_zprr 1010010 .. 01 ..... 000 ... ..... ..... \ 1298 @rprr_load_msz nreg=0 1299 1300# SVE load and broadcast quadword (scalar plus immediate) 1301# LD1RQB, LD1RQH, LD1RQS, LD1RQD 1302LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ 1303 @rpri_load_msz nreg=0 1304LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... ..... \ 1305 @rpri_load_msz nreg=0 1306 1307# SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) 1308PRF_ns 1000010 00 -1 ----- 0-- --- ----- 0 ---- 1309 1310# SVE 32-bit gather prefetch (vector plus immediate) 1311PRF_ns 1000010 -- 00 ----- 111 --- ----- 0 ---- 1312 1313# SVE contiguous prefetch (scalar plus immediate) 1314PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- 1315 1316# SVE contiguous prefetch (scalar plus scalar) 1317PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ---- 1318 1319### SVE Memory 64-bit Gather Group 1320 1321# SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets) 1322# SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets) 1323LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \ 1324 @rprr_g_load_xs_u esz=3 msz=0 scale=0 1325LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \ 1326 @rprr_g_load_xs_u_sc esz=3 msz=1 1327LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \ 1328 @rprr_g_load_xs_u_sc esz=3 msz=2 1329LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \ 1330 @rprr_g_load_xs_sc esz=3 msz=3 u=1 1331 1332# SVE 64-bit gather load (scalar plus 64-bit unscaled offsets) 1333# SVE 64-bit gather load (scalar plus 64-bit scaled offsets) 1334LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \ 1335 @rprr_g_load_u esz=3 msz=0 scale=0 1336LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \ 1337 @rprr_g_load_u_sc esz=3 msz=1 1338LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \ 1339 @rprr_g_load_u_sc esz=3 msz=2 1340LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \ 1341 @rprr_g_load_sc esz=3 msz=3 u=1 1342 1343# LD1Q 1344LD1_zprz 1100 0100 000 rm:5 101 pg:3 rn:5 rd:5 \ 1345 &rprr_gather_load u=0 ff=0 xs=2 esz=4 msz=4 scale=0 1346 1347# SVE 64-bit gather load (vector plus immediate) 1348LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \ 1349 @rpri_g_load esz=3 1350 1351# SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) 1352PRF_ns 1100010 00 11 ----- 1-- --- ----- 0 ---- 1353 1354# SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) 1355PRF_ns 1100010 00 -1 ----- 0-- --- ----- 0 ---- 1356 1357# SVE 64-bit gather prefetch (vector plus immediate) 1358PRF_ns 1100010 -- 00 ----- 111 --- ----- 0 ---- 1359 1360### SVE Memory Store Group 1361 1362# SVE store predicate register 1363STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9 1364 1365# SVE store vector register 1366STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9 1367 1368# SVE contiguous store (scalar plus immediate) 1369# ST1B, ST1H, ST1W, ST1D; require msz <= esz 1370ST_zpri 1110010 00 esz:2 0.... 111 ... ..... ..... \ 1371 @rpri_store msz=0 nreg=0 1372ST_zpri 1110010 01 esz:2 0.... 111 ... ..... ..... \ 1373 @rpri_store msz=1 nreg=0 1374ST_zpri 1110010 10 10 0.... 111 ... ..... ..... \ 1375 @rpri_store msz=2 esz=2 nreg=0 1376ST_zpri 1110010 10 11 0.... 111 ... ..... ..... \ 1377 @rpri_store msz=2 esz=3 nreg=0 1378ST_zpri 1110010 11 11 0.... 111 ... ..... ..... \ 1379 @rpri_store msz=3 esz=3 nreg=0 1380ST_zpri 1110010 10 00 0.... 111 ... ..... ..... \ 1381 @rpri_store msz=2 esz=4 nreg=0 1382ST_zpri 1110010 11 10 0.... 111 ... ..... ..... \ 1383 @rpri_store msz=3 esz=4 nreg=0 1384 1385# SVE contiguous store (scalar plus scalar) 1386# ST1B, ST1H, ST1W, ST1D; require msz <= esz 1387# Enumerate msz lest we conflict with STR_zri. 1388ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \ 1389 @rprr_store_esz_n0 msz=0 1390ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \ 1391 @rprr_store_esz_n0 msz=1 1392ST_zprr 1110010 10 10 ..... 010 ... ..... ..... \ 1393 @rprr_store msz=2 esz=2 nreg=0 1394ST_zprr 1110010 10 11 ..... 010 ... ..... ..... \ 1395 @rprr_store msz=2 esz=3 nreg=0 1396ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \ 1397 @rprr_store msz=3 esz=3 nreg=0 1398ST_zprr 1110010 10 00 ..... 010 ... ..... ..... \ 1399 @rprr_store msz=2 esz=4 nreg=0 1400ST_zprr 1110010 11 10 ..... 010 ... ..... ..... \ 1401 @rprr_store msz=3 esz=4 nreg=0 1402 1403# SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0) 1404# SVE store multiple structures (scalar plus immediate) (nreg != 0) 1405ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \ 1406 @rpri_store msz=%size_23 esz=%size_23 1407# ST[234]Q 1408ST_zpri 11100100 01 00 .... 000 ... ..... ..... \ 1409 @rpri_store msz=4 esz=4 nreg=1 1410ST_zpri 11100100 10 00 .... 000 ... ..... ..... \ 1411 @rpri_store msz=4 esz=4 nreg=2 1412ST_zpri 11100100 11 00 .... 000 ... ..... ..... \ 1413 @rpri_store msz=4 esz=4 nreg=3 1414 1415# SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0) 1416# SVE store multiple structures (scalar plus scalar) (nreg != 0) 1417ST_zprr 1110010 .. nreg:2 ..... 011 ... ..... ..... \ 1418 @rprr_store msz=%size_23 esz=%size_23 1419# ST[234]Q 1420ST_zprr 11100100 01 1 ..... 000 ... ..... ..... \ 1421 @rprr_store msz=4 esz=4 nreg=1 1422ST_zprr 11100100 10 1 ..... 000 ... ..... ..... \ 1423 @rprr_store msz=4 esz=4 nreg=2 1424ST_zprr 11100100 11 1 ..... 000 ... ..... ..... \ 1425 @rprr_store msz=4 esz=4 nreg=3 1426 1427# SVE 32-bit scatter store (scalar plus 32-bit scaled offsets) 1428# Require msz > 0 && msz <= esz. 1429ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \ 1430 @rprr_scatter_store xs=0 esz=2 scale=1 1431ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \ 1432 @rprr_scatter_store xs=1 esz=2 scale=1 1433 1434# SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets) 1435# Require msz <= esz. 1436ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \ 1437 @rprr_scatter_store xs=0 esz=2 scale=0 1438ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \ 1439 @rprr_scatter_store xs=1 esz=2 scale=0 1440 1441# SVE 64-bit scatter store (scalar plus 64-bit scaled offset) 1442# Require msz > 0 1443ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \ 1444 @rprr_scatter_store xs=2 esz=3 scale=1 1445 1446# SVE 64-bit scatter store (scalar plus 64-bit unscaled offset) 1447ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \ 1448 @rprr_scatter_store xs=2 esz=3 scale=0 1449 1450# ST1Q 1451ST1_zprz 1110 0100 001 rm:5 001 pg:3 rn:5 rd:5 \ 1452 &rprr_scatter_store xs=2 msz=4 esz=4 scale=0 1453 1454# SVE 64-bit scatter store (vector plus immediate) 1455ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \ 1456 @rpri_scatter_store esz=3 1457 1458# SVE 32-bit scatter store (vector plus immediate) 1459ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \ 1460 @rpri_scatter_store esz=2 1461 1462# SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset) 1463# Require msz > 0 1464ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \ 1465 @rprr_scatter_store xs=0 esz=3 scale=1 1466ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \ 1467 @rprr_scatter_store xs=1 esz=3 scale=1 1468 1469# SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset) 1470ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \ 1471 @rprr_scatter_store xs=0 esz=3 scale=0 1472ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \ 1473 @rprr_scatter_store xs=1 esz=3 scale=0 1474 1475#### SVE2 Support 1476 1477### SVE2 Integer Multiply - Unpredicated 1478 1479# SVE2 integer multiply vectors (unpredicated) 1480MUL_zzz 00000100 .. 1 ..... 0110 00 ..... ..... @rd_rn_rm 1481SMULH_zzz 00000100 .. 1 ..... 0110 10 ..... ..... @rd_rn_rm 1482UMULH_zzz 00000100 .. 1 ..... 0110 11 ..... ..... @rd_rn_rm 1483PMUL_zzz 00000100 00 1 ..... 0110 01 ..... ..... @rd_rn_rm_e0 1484 1485# SVE2 signed saturating doubling multiply high (unpredicated) 1486SQDMULH_zzz 00000100 .. 1 ..... 0111 00 ..... ..... @rd_rn_rm 1487SQRDMULH_zzz 00000100 .. 1 ..... 0111 01 ..... ..... @rd_rn_rm 1488 1489### SVE2 Integer - Predicated 1490 1491SADALP_zpzz 01000100 .. 000 100 101 ... ..... ..... @rdm_pg_rn 1492UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn 1493 1494### SVE2 integer unary operations (predicated) 1495 1496URECPE 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn 1497URSQRTE 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn 1498SQABS 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn 1499SQNEG 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn 1500 1501### SVE2 saturating/rounding bitwise shift left (predicated) 1502 1503SRSHL 01000100 .. 000 010 100 ... ..... ..... @rdn_pg_rm 1504URSHL 01000100 .. 000 011 100 ... ..... ..... @rdn_pg_rm 1505SRSHL 01000100 .. 000 110 100 ... ..... ..... @rdm_pg_rn # SRSHLR 1506URSHL 01000100 .. 000 111 100 ... ..... ..... @rdm_pg_rn # URSHLR 1507 1508SQSHL 01000100 .. 001 000 100 ... ..... ..... @rdn_pg_rm 1509UQSHL 01000100 .. 001 001 100 ... ..... ..... @rdn_pg_rm 1510SQSHL 01000100 .. 001 100 100 ... ..... ..... @rdm_pg_rn # SQSHLR 1511UQSHL 01000100 .. 001 101 100 ... ..... ..... @rdm_pg_rn # UQSHLR 1512 1513SQRSHL 01000100 .. 001 010 100 ... ..... ..... @rdn_pg_rm 1514UQRSHL 01000100 .. 001 011 100 ... ..... ..... @rdn_pg_rm 1515SQRSHL 01000100 .. 001 110 100 ... ..... ..... @rdm_pg_rn # SQRSHLR 1516UQRSHL 01000100 .. 001 111 100 ... ..... ..... @rdm_pg_rn # UQRSHLR 1517 1518### SVE2 integer halving add/subtract (predicated) 1519 1520SHADD 01000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm 1521UHADD 01000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm 1522SHSUB 01000100 .. 010 010 100 ... ..... ..... @rdn_pg_rm 1523UHSUB 01000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm 1524SRHADD 01000100 .. 010 100 100 ... ..... ..... @rdn_pg_rm 1525URHADD 01000100 .. 010 101 100 ... ..... ..... @rdn_pg_rm 1526SHSUB 01000100 .. 010 110 100 ... ..... ..... @rdm_pg_rn # SHSUBR 1527UHSUB 01000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # UHSUBR 1528 1529### SVE2 integer pairwise arithmetic 1530 1531ADDP 01000100 .. 010 001 101 ... ..... ..... @rdn_pg_rm 1532SMAXP 01000100 .. 010 100 101 ... ..... ..... @rdn_pg_rm 1533UMAXP 01000100 .. 010 101 101 ... ..... ..... @rdn_pg_rm 1534SMINP 01000100 .. 010 110 101 ... ..... ..... @rdn_pg_rm 1535UMINP 01000100 .. 010 111 101 ... ..... ..... @rdn_pg_rm 1536 1537### SVE2 saturating add/subtract (predicated) 1538 1539SQADD_zpzz 01000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm 1540UQADD_zpzz 01000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm 1541SQSUB_zpzz 01000100 .. 011 010 100 ... ..... ..... @rdn_pg_rm 1542UQSUB_zpzz 01000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm 1543SUQADD 01000100 .. 011 100 100 ... ..... ..... @rdn_pg_rm 1544USQADD 01000100 .. 011 101 100 ... ..... ..... @rdn_pg_rm 1545SQSUB_zpzz 01000100 .. 011 110 100 ... ..... ..... @rdm_pg_rn # SQSUBR 1546UQSUB_zpzz 01000100 .. 011 111 100 ... ..... ..... @rdm_pg_rn # UQSUBR 1547 1548#### SVE2 Widening Integer Arithmetic 1549 1550## SVE2 integer add/subtract long 1551 1552SADDLB 01000101 .. 0 ..... 00 0000 ..... ..... @rd_rn_rm 1553SADDLT 01000101 .. 0 ..... 00 0001 ..... ..... @rd_rn_rm 1554UADDLB 01000101 .. 0 ..... 00 0010 ..... ..... @rd_rn_rm 1555UADDLT 01000101 .. 0 ..... 00 0011 ..... ..... @rd_rn_rm 1556 1557SSUBLB 01000101 .. 0 ..... 00 0100 ..... ..... @rd_rn_rm 1558SSUBLT 01000101 .. 0 ..... 00 0101 ..... ..... @rd_rn_rm 1559USUBLB 01000101 .. 0 ..... 00 0110 ..... ..... @rd_rn_rm 1560USUBLT 01000101 .. 0 ..... 00 0111 ..... ..... @rd_rn_rm 1561 1562SABDLB 01000101 .. 0 ..... 00 1100 ..... ..... @rd_rn_rm 1563SABDLT 01000101 .. 0 ..... 00 1101 ..... ..... @rd_rn_rm 1564UABDLB 01000101 .. 0 ..... 00 1110 ..... ..... @rd_rn_rm 1565UABDLT 01000101 .. 0 ..... 00 1111 ..... ..... @rd_rn_rm 1566 1567## SVE2 integer add/subtract interleaved long 1568 1569SADDLBT 01000101 .. 0 ..... 1000 00 ..... ..... @rd_rn_rm 1570SSUBLBT 01000101 .. 0 ..... 1000 10 ..... ..... @rd_rn_rm 1571SSUBLTB 01000101 .. 0 ..... 1000 11 ..... ..... @rd_rn_rm 1572 1573## SVE2 integer add/subtract wide 1574 1575SADDWB 01000101 .. 0 ..... 010 000 ..... ..... @rd_rn_rm 1576SADDWT 01000101 .. 0 ..... 010 001 ..... ..... @rd_rn_rm 1577UADDWB 01000101 .. 0 ..... 010 010 ..... ..... @rd_rn_rm 1578UADDWT 01000101 .. 0 ..... 010 011 ..... ..... @rd_rn_rm 1579 1580SSUBWB 01000101 .. 0 ..... 010 100 ..... ..... @rd_rn_rm 1581SSUBWT 01000101 .. 0 ..... 010 101 ..... ..... @rd_rn_rm 1582USUBWB 01000101 .. 0 ..... 010 110 ..... ..... @rd_rn_rm 1583USUBWT 01000101 .. 0 ..... 010 111 ..... ..... @rd_rn_rm 1584 1585## SVE2 integer multiply long 1586 1587SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm 1588SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm 1589PMULLB 01000101 .. 0 ..... 011 010 ..... ..... @rd_rn_rm 1590PMULLT 01000101 .. 0 ..... 011 011 ..... ..... @rd_rn_rm 1591SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm 1592SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm 1593UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm 1594UMULLT_zzz 01000101 .. 0 ..... 011 111 ..... ..... @rd_rn_rm 1595 1596## SVE2 bitwise shift left long 1597 1598# Note bit23 == 0 is handled by esz > 0 in do_sve2_shll_tb. 1599SSHLLB 01000101 .. 0 ..... 1010 00 ..... ..... @rd_rn_tszimm_shl 1600SSHLLT 01000101 .. 0 ..... 1010 01 ..... ..... @rd_rn_tszimm_shl 1601USHLLB 01000101 .. 0 ..... 1010 10 ..... ..... @rd_rn_tszimm_shl 1602USHLLT 01000101 .. 0 ..... 1010 11 ..... ..... @rd_rn_tszimm_shl 1603 1604## SVE2 bitwise exclusive-or interleaved 1605 1606EORBT 01000101 .. 0 ..... 10010 0 ..... ..... @rd_rn_rm 1607EORTB 01000101 .. 0 ..... 10010 1 ..... ..... @rd_rn_rm 1608 1609## SVE integer matrix multiply accumulate 1610 1611SMMLA 01000101 00 0 ..... 10011 0 ..... ..... @rda_rn_rm_ex esz=2 1612USMMLA 01000101 10 0 ..... 10011 0 ..... ..... @rda_rn_rm_ex esz=2 1613UMMLA 01000101 11 0 ..... 10011 0 ..... ..... @rda_rn_rm_ex esz=2 1614 1615## SVE2 bitwise permute 1616 1617BEXT 01000101 .. 0 ..... 1011 00 ..... ..... @rd_rn_rm 1618BDEP 01000101 .. 0 ..... 1011 01 ..... ..... @rd_rn_rm 1619BGRP 01000101 .. 0 ..... 1011 10 ..... ..... @rd_rn_rm 1620 1621#### SVE2 Accumulate 1622 1623## SVE2 complex integer add 1624 1625CADD_rot90 01000101 .. 00000 0 11011 0 ..... ..... @rdn_rm 1626CADD_rot270 01000101 .. 00000 0 11011 1 ..... ..... @rdn_rm 1627SQCADD_rot90 01000101 .. 00000 1 11011 0 ..... ..... @rdn_rm 1628SQCADD_rot270 01000101 .. 00000 1 11011 1 ..... ..... @rdn_rm 1629 1630## SVE2 integer absolute difference and accumulate long 1631 1632SABALB 01000101 .. 0 ..... 1100 00 ..... ..... @rda_rn_rm 1633SABALT 01000101 .. 0 ..... 1100 01 ..... ..... @rda_rn_rm 1634UABALB 01000101 .. 0 ..... 1100 10 ..... ..... @rda_rn_rm 1635UABALT 01000101 .. 0 ..... 1100 11 ..... ..... @rda_rn_rm 1636 1637## SVE2 integer add/subtract long with carry 1638 1639# ADC and SBC decoded via size in helper dispatch. 1640ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm 1641ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm 1642 1643## SVE2 bitwise shift right and accumulate 1644 1645# TODO: Use @rda and %reg_movprfx here. 1646SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr 1647USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr 1648SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr 1649URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr 1650 1651## SVE2 bitwise shift and insert 1652 1653SRI 01000101 .. 0 ..... 11110 0 ..... ..... @rd_rn_tszimm_shr 1654SLI 01000101 .. 0 ..... 11110 1 ..... ..... @rd_rn_tszimm_shl 1655 1656## SVE2 integer absolute difference and accumulate 1657 1658# TODO: Use @rda and %reg_movprfx here. 1659SABA 01000101 .. 0 ..... 11111 0 ..... ..... @rd_rn_rm 1660UABA 01000101 .. 0 ..... 11111 1 ..... ..... @rd_rn_rm 1661 1662#### SVE2 Narrowing 1663 1664## SVE2 saturating extract narrow 1665# Bits 23, 18-16 are zero, limited in the translator via esz < 3 & imm == 0. 1666 1667{ 1668 SQCVTN_sh 01000101 00 1 10001 010 000 ....0 ..... @rd_rnx2 esz=1 1669 SQXTNB 01000101 .. 1 ..... 010 000 ..... ..... @rd_rn_tszimm_shl 1670} 1671SQXTNT 01000101 .. 1 ..... 010 001 ..... ..... @rd_rn_tszimm_shl 1672{ 1673 UQCVTN_sh 01000101 00 1 10001 010 010 ....0 ..... @rd_rnx2 esz=1 1674 UQXTNB 01000101 .. 1 ..... 010 010 ..... ..... @rd_rn_tszimm_shl 1675} 1676UQXTNT 01000101 .. 1 ..... 010 011 ..... ..... @rd_rn_tszimm_shl 1677{ 1678 SQCVTUN_sh 01000101 00 1 10001 010 100 ....0 ..... @rd_rnx2 esz=1 1679 SQXTUNB 01000101 .. 1 ..... 010 100 ..... ..... @rd_rn_tszimm_shl 1680} 1681SQXTUNT 01000101 .. 1 ..... 010 101 ..... ..... @rd_rn_tszimm_shl 1682 1683## SVE2 bitwise shift right narrow 1684 1685# Bit 23 == 0 is handled by esz > 0 in the translator. 1686SQSHRUNB 01000101 .. 1 ..... 00 0000 ..... ..... @rd_rn_tszimm_shr 1687SQSHRUNT 01000101 .. 1 ..... 00 0001 ..... ..... @rd_rn_tszimm_shr 1688SQRSHRUNB 01000101 .. 1 ..... 00 0010 ..... ..... @rd_rn_tszimm_shr 1689SQRSHRUNT 01000101 .. 1 ..... 00 0011 ..... ..... @rd_rn_tszimm_shr 1690SHRNB 01000101 .. 1 ..... 00 0100 ..... ..... @rd_rn_tszimm_shr 1691SHRNT 01000101 .. 1 ..... 00 0101 ..... ..... @rd_rn_tszimm_shr 1692RSHRNB 01000101 .. 1 ..... 00 0110 ..... ..... @rd_rn_tszimm_shr 1693RSHRNT 01000101 .. 1 ..... 00 0111 ..... ..... @rd_rn_tszimm_shr 1694SQSHRNB 01000101 .. 1 ..... 00 1000 ..... ..... @rd_rn_tszimm_shr 1695SQSHRNT 01000101 .. 1 ..... 00 1001 ..... ..... @rd_rn_tszimm_shr 1696SQRSHRNB 01000101 .. 1 ..... 00 1010 ..... ..... @rd_rn_tszimm_shr 1697SQRSHRNT 01000101 .. 1 ..... 00 1011 ..... ..... @rd_rn_tszimm_shr 1698UQSHRNB 01000101 .. 1 ..... 00 1100 ..... ..... @rd_rn_tszimm_shr 1699UQSHRNT 01000101 .. 1 ..... 00 1101 ..... ..... @rd_rn_tszimm_shr 1700UQRSHRNB 01000101 .. 1 ..... 00 1110 ..... ..... @rd_rn_tszimm_shr 1701UQRSHRNT 01000101 .. 1 ..... 00 1111 ..... ..... @rd_rn_tszimm_shr 1702 1703## SVE2 integer add/subtract narrow high part 1704 1705ADDHNB 01000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm 1706ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm 1707RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm 1708RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm 1709SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm 1710SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm 1711RSUBHNB 01000101 .. 1 ..... 011 110 ..... ..... @rd_rn_rm 1712RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..... @rd_rn_rm 1713 1714### SVE2 Character Match 1715 1716MATCH 01000101 .. 1 ..... 100 ... ..... 0 .... @pd_pg_rn_rm 1717NMATCH 01000101 .. 1 ..... 100 ... ..... 1 .... @pd_pg_rn_rm 1718 1719### SVE2 Histogram Computation 1720 1721HISTCNT 01000101 .. 1 ..... 110 ... ..... ..... @rd_pg_rn_rm 1722HISTSEG 01000101 .. 1 ..... 101 000 ..... ..... @rd_rn_rm 1723 1724## SVE2 floating-point pairwise operations 1725 1726FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm 1727FMAXNMP 01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm 1728FMINNMP 01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm 1729FMAXP 01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm 1730FMINP 01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm 1731 1732#### SVE Integer Multiply-Add (unpredicated) 1733 1734## SVE2 saturating multiply-add long 1735 1736SQDMLALB_zzzw 01000100 .. 0 ..... 0110 00 ..... ..... @rda_rn_rm 1737SQDMLALT_zzzw 01000100 .. 0 ..... 0110 01 ..... ..... @rda_rn_rm 1738SQDMLSLB_zzzw 01000100 .. 0 ..... 0110 10 ..... ..... @rda_rn_rm 1739SQDMLSLT_zzzw 01000100 .. 0 ..... 0110 11 ..... ..... @rda_rn_rm 1740 1741## SVE2 saturating multiply-add interleaved long 1742 1743SQDMLALBT 01000100 .. 0 ..... 00001 0 ..... ..... @rda_rn_rm 1744SQDMLSLBT 01000100 .. 0 ..... 00001 1 ..... ..... @rda_rn_rm 1745 1746## SVE2 saturating multiply-add high 1747 1748SQRDMLAH_zzzz 01000100 .. 0 ..... 01110 0 ..... ..... @rda_rn_rm 1749SQRDMLSH_zzzz 01000100 .. 0 ..... 01110 1 ..... ..... @rda_rn_rm 1750 1751## SVE2 integer multiply-add long 1752 1753SMLALB_zzzw 01000100 .. 0 ..... 010 000 ..... ..... @rda_rn_rm 1754SMLALT_zzzw 01000100 .. 0 ..... 010 001 ..... ..... @rda_rn_rm 1755UMLALB_zzzw 01000100 .. 0 ..... 010 010 ..... ..... @rda_rn_rm 1756UMLALT_zzzw 01000100 .. 0 ..... 010 011 ..... ..... @rda_rn_rm 1757SMLSLB_zzzw 01000100 .. 0 ..... 010 100 ..... ..... @rda_rn_rm 1758SMLSLT_zzzw 01000100 .. 0 ..... 010 101 ..... ..... @rda_rn_rm 1759UMLSLB_zzzw 01000100 .. 0 ..... 010 110 ..... ..... @rda_rn_rm 1760UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm 1761 1762## SVE2 complex integer multiply-add 1763 1764CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx 1765SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx 1766 1767## SVE dot product 1768 1769SDOT_zzzz_2s 01000100 00 0 ..... 110 010 ..... ..... @rda_rn_rm_ex esz=2 1770UDOT_zzzz_2s 01000100 00 0 ..... 110 011 ..... ..... @rda_rn_rm_ex esz=2 1771 1772USDOT_zzzz_4s 01000100 10 0 ..... 011 110 ..... ..... @rda_rn_rm_ex esz=2 1773 1774### SVE2 floating point matrix multiply accumulate 1775BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=1 1776FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=2 1777FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=3 1778 1779### SVE2 Memory Gather Load Group 1780 1781# SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets) 1782LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \ 1783 &rprr_gather_load xs=2 esz=3 scale=0 ff=0 1784 1785# SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets) 1786LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \ 1787 &rprr_gather_load xs=0 esz=2 scale=0 ff=0 1788 1789### SVE2 Memory Store Group 1790 1791# SVE2 64-bit scatter non-temporal store (vector plus scalar) 1792STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \ 1793 @rprr_scatter_store xs=2 esz=3 scale=0 1794 1795# SVE2 32-bit scatter non-temporal store (vector plus scalar) 1796STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \ 1797 @rprr_scatter_store xs=0 esz=2 scale=0 1798 1799### SVE2 Crypto Extensions 1800 1801# SVE2 crypto unary operations 1802AESMC 01000101 00 10000011100 0 00000 rd:5 1803AESIMC 01000101 00 10000011100 1 00000 rd:5 1804 1805# SVE2 crypto destructive binary operations 1806AESE 01000101 00 10001 0 11100 0 ..... ..... @rdn_rm_e0 1807AESD 01000101 00 10001 0 11100 1 ..... ..... @rdn_rm_e0 1808SM4E 01000101 00 10001 1 11100 0 ..... ..... @rdn_rm_e0 1809 1810# SVE2 crypto constructive binary operations 1811SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0 1812RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0 1813 1814### SVE2 floating-point convert precision odd elements 1815FCVTXNT_ds 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1816FCVTX_ds 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1817FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 1818BFCVTNT 01100100 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1819FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 1820FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1821FCVTLT_sd 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 1822 1823### SVE2 floating-point convert to integer 1824FLOGB 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz 1825 1826### SVE2 floating-point multiply-add long (vectors) 1827FMLALB_zzzw 01100100 10 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2 1828FMLALT_zzzw 01100100 10 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2 1829FMLSLB_zzzw 01100100 10 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_ex esz=2 1830FMLSLT_zzzw 01100100 10 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_ex esz=2 1831 1832BFMLALB_zzzw 01100100 11 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2 1833BFMLALT_zzzw 01100100 11 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2 1834BFMLSLB_zzzw 01100100 11 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_ex esz=2 1835BFMLSLT_zzzw 01100100 11 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_ex esz=2 1836 1837### SVE2 floating-point dot-product 1838FDOT_zzzz 01100100 00 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2 1839BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2 1840 1841### SVE2 floating-point multiply-add long (indexed) 1842 1843FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2 1844FMLALT_zzxw 01100100 10 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 1845FMLSLB_zzxw 01100100 10 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2 1846FMLSLT_zzxw 01100100 10 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2 1847 1848BFMLALB_zzxw 01100100 11 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2 1849BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 1850BFMLSLB_zzxw 01100100 11 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2 1851BFMLSLT_zzxw 01100100 11 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2 1852 1853### SVE2 floating-point dot-product (indexed) 1854 1855FDOT_zzxz 01100100 00 1 ..... 010000 ..... ..... @rrxr_2 esz=2 1856BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2 1857 1858### SVE broadcast predicate element 1859 1860&psel esz pd pn pm rv imm 1861%psel_rv 16:2 !function=plus_12 1862%psel_imm_b 22:2 19:2 1863%psel_imm_h 22:2 20:1 1864%psel_imm_s 22:2 1865%psel_imm_d 23:1 1866@psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \ 1867 &psel rv=%psel_rv 1868 1869PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \ 1870 @psel esz=0 imm=%psel_imm_b 1871PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \ 1872 @psel esz=1 imm=%psel_imm_h 1873PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ 1874 @psel esz=2 imm=%psel_imm_s 1875PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ 1876 @psel esz=3 imm=%psel_imm_d 1877 1878### SVE clamp 1879 1880SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm 1881UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm 1882 1883FCLAMP 01100100 .. 1 ..... 001001 ..... ..... @rda_rn_rm 1884 1885### SVE2p1 multi-vec contiguous load 1886 1887&zcrr_ldst rd png rn rm esz nreg 1888&zcri_ldst rd png rn imm esz nreg 1889%png 10:3 !function=plus_8 1890%zd_ax2 1:4 !function=times_2 1891%zd_ax4 2:3 !function=times_4 1892 1893LD1_zcrr 10100000000 rm:5 0 esz:2 ... rn:5 .... - \ 1894 &zcrr_ldst %png rd=%zd_ax2 nreg=2 1895LD1_zcrr 10100000000 rm:5 1 esz:2 ... rn:5 ... 0- \ 1896 &zcrr_ldst %png rd=%zd_ax4 nreg=4 1897 1898ST1_zcrr 10100000001 rm:5 0 esz:2 ... rn:5 .... - \ 1899 &zcrr_ldst %png rd=%zd_ax2 nreg=2 1900ST1_zcrr 10100000001 rm:5 1 esz:2 ... rn:5 ... 0- \ 1901 &zcrr_ldst %png rd=%zd_ax4 nreg=4 1902 1903LD1_zcri 101000000100 imm:s4 0 esz:2 ... rn:5 .... - \ 1904 &zcri_ldst %png rd=%zd_ax2 nreg=2 1905LD1_zcri 101000000100 imm:s4 1 esz:2 ... rn:5 ... 0- \ 1906 &zcri_ldst %png rd=%zd_ax4 nreg=4 1907 1908ST1_zcri 101000000110 imm:s4 0 esz:2 ... rn:5 .... - \ 1909 &zcri_ldst %png rd=%zd_ax2 nreg=2 1910ST1_zcri 101000000110 imm:s4 1 esz:2 ... rn:5 ... 0- \ 1911 &zcri_ldst %png rd=%zd_ax4 nreg=4 1912 1913# Note: N bit and 0 bit (for nreg4) still mashed in rd. 1914# This is handled within gen_ldst_c(). 1915LD1_zcrr_stride 10100001000 rm:5 0 esz:2 ... rn:5 rd:5 \ 1916 &zcrr_ldst %png nreg=2 1917LD1_zcrr_stride 10100001000 rm:5 1 esz:2 ... rn:5 rd:5 \ 1918 &zcrr_ldst %png nreg=4 1919 1920ST1_zcrr_stride 10100001001 rm:5 0 esz:2 ... rn:5 rd:5 \ 1921 &zcrr_ldst %png nreg=2 1922ST1_zcrr_stride 10100001001 rm:5 1 esz:2 ... rn:5 rd:5 \ 1923 &zcrr_ldst %png nreg=4 1924 1925LD1_zcri_stride 101000010100 imm:s4 0 esz:2 ... rn:5 rd:5 \ 1926 &zcri_ldst %png nreg=2 1927LD1_zcri_stride 101000010100 imm:s4 1 esz:2 ... rn:5 rd:5 \ 1928 &zcri_ldst %png nreg=4 1929 1930ST1_zcri_stride 101000010110 imm:s4 0 esz:2 ... rn:5 rd:5 \ 1931 &zcri_ldst %png nreg=2 1932ST1_zcri_stride 101000010110 imm:s4 1 esz:2 ... rn:5 rd:5 \ 1933 &zcri_ldst %png nreg=4 1934