1 /* 2 * ARM helper routines 3 * 4 * Copyright (c) 2005-2007 CodeSourcery, LLC 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu/main-loop.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "internals.h" 24 #include "cpu-features.h" 25 #include "exec/exec-all.h" 26 #include "exec/cpu_ldst.h" 27 #include "cpregs.h" 28 29 #define SIGNBIT (uint32_t)0x80000000 30 #define SIGNBIT64 ((uint64_t)1 << 63) 31 32 int exception_target_el(CPUARMState *env) 33 { 34 int target_el = MAX(1, arm_current_el(env)); 35 36 /* 37 * No such thing as secure EL1 if EL3 is aarch32, 38 * so update the target EL to EL3 in this case. 39 */ 40 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { 41 target_el = 3; 42 } 43 44 return target_el; 45 } 46 47 void raise_exception(CPUARMState *env, uint32_t excp, 48 uint32_t syndrome, uint32_t target_el) 49 { 50 CPUState *cs = env_cpu(env); 51 52 if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { 53 /* 54 * Redirect NS EL1 exceptions to NS EL2. These are reported with 55 * their original syndrome register value, with the exception of 56 * SIMD/FP access traps, which are reported as uncategorized 57 * (see DDI0478C.a D1.10.4) 58 */ 59 target_el = 2; 60 if (syn_get_ec(syndrome) == EC_ADVSIMDFPACCESSTRAP) { 61 syndrome = syn_uncategorized(); 62 } 63 } 64 65 assert(!excp_is_internal(excp)); 66 cs->exception_index = excp; 67 env->exception.syndrome = syndrome; 68 env->exception.target_el = target_el; 69 cpu_loop_exit(cs); 70 } 71 72 void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, 73 uint32_t target_el, uintptr_t ra) 74 { 75 CPUState *cs = env_cpu(env); 76 77 /* 78 * restore_state_to_opc() will set env->exception.syndrome, so 79 * we must restore CPU state here before setting the syndrome 80 * the caller passed us, and cannot use cpu_loop_exit_restore(). 81 */ 82 cpu_restore_state(cs, ra); 83 raise_exception(env, excp, syndrome, target_el); 84 } 85 86 uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, 87 uint64_t ireg, uint64_t def) 88 { 89 uint64_t tmp, val = 0; 90 uint32_t maxindex = ((desc & 3) + 1) * 8; 91 uint32_t base_reg = desc >> 2; 92 uint32_t shift, index, reg; 93 94 for (shift = 0; shift < 64; shift += 8) { 95 index = (ireg >> shift) & 0xff; 96 if (index < maxindex) { 97 reg = base_reg + (index >> 3); 98 tmp = *aa32_vfp_dreg(env, reg); 99 tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift; 100 } else { 101 tmp = def & (0xffull << shift); 102 } 103 val |= tmp; 104 } 105 return val; 106 } 107 108 void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) 109 { 110 /* 111 * Perform the v8M stack limit check for SP updates from translated code, 112 * raising an exception if the limit is breached. 113 */ 114 if (newvalue < v7m_sp_limit(env)) { 115 /* 116 * Stack limit exceptions are a rare case, so rather than syncing 117 * PC/condbits before the call, we use raise_exception_ra() so 118 * that cpu_restore_state() will sort them out. 119 */ 120 raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC()); 121 } 122 } 123 124 /* Sign/zero extend */ 125 uint32_t HELPER(sxtb16)(uint32_t x) 126 { 127 uint32_t res; 128 res = (uint16_t)(int8_t)x; 129 res |= (uint32_t)(int8_t)(x >> 16) << 16; 130 return res; 131 } 132 133 static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) 134 { 135 /* 136 * Take a division-by-zero exception if necessary; otherwise return 137 * to get the usual non-trapping division behaviour (result of 0) 138 */ 139 if (arm_feature(env, ARM_FEATURE_M) 140 && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { 141 raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); 142 } 143 } 144 145 uint32_t HELPER(uxtb16)(uint32_t x) 146 { 147 uint32_t res; 148 res = (uint16_t)(uint8_t)x; 149 res |= (uint32_t)(uint8_t)(x >> 16) << 16; 150 return res; 151 } 152 153 int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) 154 { 155 if (den == 0) { 156 handle_possible_div0_trap(env, GETPC()); 157 return 0; 158 } 159 if (num == INT_MIN && den == -1) { 160 return INT_MIN; 161 } 162 return num / den; 163 } 164 165 uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) 166 { 167 if (den == 0) { 168 handle_possible_div0_trap(env, GETPC()); 169 return 0; 170 } 171 return num / den; 172 } 173 174 uint32_t HELPER(rbit)(uint32_t x) 175 { 176 return revbit32(x); 177 } 178 179 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) 180 { 181 uint32_t res = a + b; 182 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) 183 env->QF = 1; 184 return res; 185 } 186 187 uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b) 188 { 189 uint32_t res = a + b; 190 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) { 191 env->QF = 1; 192 res = ~(((int32_t)a >> 31) ^ SIGNBIT); 193 } 194 return res; 195 } 196 197 uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b) 198 { 199 uint32_t res = a - b; 200 if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) { 201 env->QF = 1; 202 res = ~(((int32_t)a >> 31) ^ SIGNBIT); 203 } 204 return res; 205 } 206 207 uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) 208 { 209 uint32_t res = a + b; 210 if (res < a) { 211 env->QF = 1; 212 res = ~0; 213 } 214 return res; 215 } 216 217 uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) 218 { 219 uint32_t res = a - b; 220 if (res > a) { 221 env->QF = 1; 222 res = 0; 223 } 224 return res; 225 } 226 227 /* Signed saturation. */ 228 static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift) 229 { 230 int32_t top; 231 uint32_t mask; 232 233 top = val >> shift; 234 mask = (1u << shift) - 1; 235 if (top > 0) { 236 env->QF = 1; 237 return mask; 238 } else if (top < -1) { 239 env->QF = 1; 240 return ~mask; 241 } 242 return val; 243 } 244 245 /* Unsigned saturation. */ 246 static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift) 247 { 248 uint32_t max; 249 250 max = (1u << shift) - 1; 251 if (val < 0) { 252 env->QF = 1; 253 return 0; 254 } else if (val > max) { 255 env->QF = 1; 256 return max; 257 } 258 return val; 259 } 260 261 /* Signed saturate. */ 262 uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift) 263 { 264 return do_ssat(env, x, shift); 265 } 266 267 /* Dual halfword signed saturate. */ 268 uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift) 269 { 270 uint32_t res; 271 272 res = (uint16_t)do_ssat(env, (int16_t)x, shift); 273 res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16; 274 return res; 275 } 276 277 /* Unsigned saturate. */ 278 uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift) 279 { 280 return do_usat(env, x, shift); 281 } 282 283 /* Dual halfword unsigned saturate. */ 284 uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift) 285 { 286 uint32_t res; 287 288 res = (uint16_t)do_usat(env, (int16_t)x, shift); 289 res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16; 290 return res; 291 } 292 293 void HELPER(setend)(CPUARMState *env) 294 { 295 env->uncached_cpsr ^= CPSR_E; 296 arm_rebuild_hflags(env); 297 } 298 299 void HELPER(check_bxj_trap)(CPUARMState *env, uint32_t rm) 300 { 301 /* 302 * Only called if in NS EL0 or EL1 for a BXJ for a v7A CPU; 303 * check if HSTR.TJDBX means we need to trap to EL2. 304 */ 305 if (env->cp15.hstr_el2 & HSTR_TJDBX) { 306 /* 307 * We know the condition code check passed, so take the IMPDEF 308 * choice to always report CV=1 COND 0xe 309 */ 310 uint32_t syn = syn_bxjtrap(1, 0xe, rm); 311 raise_exception_ra(env, EXCP_HYP_TRAP, syn, 2, GETPC()); 312 } 313 } 314 315 #ifndef CONFIG_USER_ONLY 316 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped. 317 * The function returns the target EL (1-3) if the instruction is to be trapped; 318 * otherwise it returns 0 indicating it is not trapped. 319 */ 320 static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) 321 { 322 int cur_el = arm_current_el(env); 323 uint64_t mask; 324 325 if (arm_feature(env, ARM_FEATURE_M)) { 326 /* M profile cores can never trap WFI/WFE. */ 327 return 0; 328 } 329 330 /* If we are currently in EL0 then we need to check if SCTLR is set up for 331 * WFx instructions being trapped to EL1. These trap bits don't exist in v7. 332 */ 333 if (cur_el < 1 && arm_feature(env, ARM_FEATURE_V8)) { 334 int target_el; 335 336 mask = is_wfe ? SCTLR_nTWE : SCTLR_nTWI; 337 if (arm_is_secure_below_el3(env) && !arm_el_is_aa64(env, 3)) { 338 /* Secure EL0 and Secure PL1 is at EL3 */ 339 target_el = 3; 340 } else { 341 target_el = 1; 342 } 343 344 if (!(env->cp15.sctlr_el[target_el] & mask)) { 345 return target_el; 346 } 347 } 348 349 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it 350 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the 351 * bits will be zero indicating no trap. 352 */ 353 if (cur_el < 2) { 354 mask = is_wfe ? HCR_TWE : HCR_TWI; 355 if (arm_hcr_el2_eff(env) & mask) { 356 return 2; 357 } 358 } 359 360 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */ 361 if (cur_el < 3) { 362 mask = (is_wfe) ? SCR_TWE : SCR_TWI; 363 if (env->cp15.scr_el3 & mask) { 364 return 3; 365 } 366 } 367 368 return 0; 369 } 370 #endif 371 372 void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) 373 { 374 #ifdef CONFIG_USER_ONLY 375 /* 376 * WFI in the user-mode emulator is technically permitted but not 377 * something any real-world code would do. AArch64 Linux kernels 378 * trap it via SCTRL_EL1.nTWI and make it an (expensive) NOP; 379 * AArch32 kernels don't trap it so it will delay a bit. 380 * For QEMU, make it NOP here, because trying to raise EXCP_HLT 381 * would trigger an abort. 382 */ 383 return; 384 #else 385 CPUState *cs = env_cpu(env); 386 int target_el = check_wfx_trap(env, false); 387 388 if (cpu_has_work(cs)) { 389 /* Don't bother to go into our "low power state" if 390 * we would just wake up immediately. 391 */ 392 return; 393 } 394 395 if (target_el) { 396 if (env->aarch64) { 397 env->pc -= insn_len; 398 } else { 399 env->regs[15] -= insn_len; 400 } 401 402 raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len == 2), 403 target_el); 404 } 405 406 cs->exception_index = EXCP_HLT; 407 cs->halted = 1; 408 cpu_loop_exit(cs); 409 #endif 410 } 411 412 void HELPER(wfe)(CPUARMState *env) 413 { 414 /* This is a hint instruction that is semantically different 415 * from YIELD even though we currently implement it identically. 416 * Don't actually halt the CPU, just yield back to top 417 * level loop. This is not going into a "low power state" 418 * (ie halting until some event occurs), so we never take 419 * a configurable trap to a different exception level. 420 */ 421 HELPER(yield)(env); 422 } 423 424 void HELPER(yield)(CPUARMState *env) 425 { 426 CPUState *cs = env_cpu(env); 427 428 /* This is a non-trappable hint instruction that generally indicates 429 * that the guest is currently busy-looping. Yield control back to the 430 * top level loop so that a more deserving VCPU has a chance to run. 431 */ 432 cs->exception_index = EXCP_YIELD; 433 cpu_loop_exit(cs); 434 } 435 436 /* Raise an internal-to-QEMU exception. This is limited to only 437 * those EXCP values which are special cases for QEMU to interrupt 438 * execution and not to be used for exceptions which are passed to 439 * the guest (those must all have syndrome information and thus should 440 * use exception_with_syndrome*). 441 */ 442 void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) 443 { 444 CPUState *cs = env_cpu(env); 445 446 assert(excp_is_internal(excp)); 447 cs->exception_index = excp; 448 cpu_loop_exit(cs); 449 } 450 451 /* Raise an exception with the specified syndrome register value */ 452 void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp, 453 uint32_t syndrome, uint32_t target_el) 454 { 455 raise_exception(env, excp, syndrome, target_el); 456 } 457 458 /* 459 * Raise an exception with the specified syndrome register value 460 * to the default target el. 461 */ 462 void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, 463 uint32_t syndrome) 464 { 465 raise_exception(env, excp, syndrome, exception_target_el(env)); 466 } 467 468 uint32_t HELPER(cpsr_read)(CPUARMState *env) 469 { 470 return cpsr_read(env) & ~CPSR_EXEC; 471 } 472 473 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) 474 { 475 cpsr_write(env, val, mask, CPSRWriteByInstr); 476 /* TODO: Not all cpsr bits are relevant to hflags. */ 477 arm_rebuild_hflags(env); 478 } 479 480 /* Write the CPSR for a 32-bit exception return */ 481 void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) 482 { 483 uint32_t mask; 484 485 bql_lock(); 486 arm_call_pre_el_change_hook(env_archcpu(env)); 487 bql_unlock(); 488 489 mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar); 490 cpsr_write(env, val, mask, CPSRWriteExceptionReturn); 491 492 /* Generated code has already stored the new PC value, but 493 * without masking out its low bits, because which bits need 494 * masking depends on whether we're returning to Thumb or ARM 495 * state. Do the masking now. 496 */ 497 env->regs[15] &= (env->thumb ? ~1 : ~3); 498 arm_rebuild_hflags(env); 499 500 bql_lock(); 501 arm_call_el_change_hook(env_archcpu(env)); 502 bql_unlock(); 503 } 504 505 /* Access to user mode registers from privileged modes. */ 506 uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno) 507 { 508 uint32_t val; 509 510 if (regno == 13) { 511 val = env->banked_r13[BANK_USRSYS]; 512 } else if (regno == 14) { 513 val = env->banked_r14[BANK_USRSYS]; 514 } else if (regno >= 8 515 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { 516 val = env->usr_regs[regno - 8]; 517 } else { 518 val = env->regs[regno]; 519 } 520 return val; 521 } 522 523 void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val) 524 { 525 if (regno == 13) { 526 env->banked_r13[BANK_USRSYS] = val; 527 } else if (regno == 14) { 528 env->banked_r14[BANK_USRSYS] = val; 529 } else if (regno >= 8 530 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { 531 env->usr_regs[regno - 8] = val; 532 } else { 533 env->regs[regno] = val; 534 } 535 } 536 537 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) 538 { 539 if ((env->uncached_cpsr & CPSR_M) == mode) { 540 env->regs[13] = val; 541 } else { 542 env->banked_r13[bank_number(mode)] = val; 543 } 544 } 545 546 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) 547 { 548 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { 549 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF. 550 * Other UNPREDICTABLE and UNDEF cases were caught at translate time. 551 */ 552 raise_exception(env, EXCP_UDEF, syn_uncategorized(), 553 exception_target_el(env)); 554 } 555 556 if ((env->uncached_cpsr & CPSR_M) == mode) { 557 return env->regs[13]; 558 } else { 559 return env->banked_r13[bank_number(mode)]; 560 } 561 } 562 563 static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode, 564 uint32_t regno) 565 { 566 /* Raise an exception if the requested access is one of the UNPREDICTABLE 567 * cases; otherwise return. This broadly corresponds to the pseudocode 568 * BankedRegisterAccessValid() and SPSRAccessValid(), 569 * except that we have already handled some cases at translate time. 570 */ 571 int curmode = env->uncached_cpsr & CPSR_M; 572 573 if (regno == 17) { 574 /* ELR_Hyp: a special case because access from tgtmode is OK */ 575 if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) { 576 goto undef; 577 } 578 return; 579 } 580 581 if (curmode == tgtmode) { 582 goto undef; 583 } 584 585 if (tgtmode == ARM_CPU_MODE_USR) { 586 switch (regno) { 587 case 8 ... 12: 588 if (curmode != ARM_CPU_MODE_FIQ) { 589 goto undef; 590 } 591 break; 592 case 13: 593 if (curmode == ARM_CPU_MODE_SYS) { 594 goto undef; 595 } 596 break; 597 case 14: 598 if (curmode == ARM_CPU_MODE_HYP || curmode == ARM_CPU_MODE_SYS) { 599 goto undef; 600 } 601 break; 602 default: 603 break; 604 } 605 } 606 607 if (tgtmode == ARM_CPU_MODE_HYP) { 608 /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */ 609 if (curmode != ARM_CPU_MODE_MON) { 610 goto undef; 611 } 612 } 613 614 return; 615 616 undef: 617 raise_exception(env, EXCP_UDEF, syn_uncategorized(), 618 exception_target_el(env)); 619 } 620 621 void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode, 622 uint32_t regno) 623 { 624 msr_mrs_banked_exc_checks(env, tgtmode, regno); 625 626 switch (regno) { 627 case 16: /* SPSRs */ 628 env->banked_spsr[bank_number(tgtmode)] = value; 629 break; 630 case 17: /* ELR_Hyp */ 631 env->elr_el[2] = value; 632 break; 633 case 13: 634 env->banked_r13[bank_number(tgtmode)] = value; 635 break; 636 case 14: 637 env->banked_r14[r14_bank_number(tgtmode)] = value; 638 break; 639 case 8 ... 12: 640 switch (tgtmode) { 641 case ARM_CPU_MODE_USR: 642 env->usr_regs[regno - 8] = value; 643 break; 644 case ARM_CPU_MODE_FIQ: 645 env->fiq_regs[regno - 8] = value; 646 break; 647 default: 648 g_assert_not_reached(); 649 } 650 break; 651 default: 652 g_assert_not_reached(); 653 } 654 } 655 656 uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno) 657 { 658 msr_mrs_banked_exc_checks(env, tgtmode, regno); 659 660 switch (regno) { 661 case 16: /* SPSRs */ 662 return env->banked_spsr[bank_number(tgtmode)]; 663 case 17: /* ELR_Hyp */ 664 return env->elr_el[2]; 665 case 13: 666 return env->banked_r13[bank_number(tgtmode)]; 667 case 14: 668 return env->banked_r14[r14_bank_number(tgtmode)]; 669 case 8 ... 12: 670 switch (tgtmode) { 671 case ARM_CPU_MODE_USR: 672 return env->usr_regs[regno - 8]; 673 case ARM_CPU_MODE_FIQ: 674 return env->fiq_regs[regno - 8]; 675 default: 676 g_assert_not_reached(); 677 } 678 default: 679 g_assert_not_reached(); 680 } 681 } 682 683 const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, 684 uint32_t syndrome, uint32_t isread) 685 { 686 ARMCPU *cpu = env_archcpu(env); 687 const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, key); 688 CPAccessResult res = CP_ACCESS_OK; 689 int target_el; 690 691 assert(ri != NULL); 692 693 if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 694 && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) { 695 res = CP_ACCESS_TRAP; 696 goto fail; 697 } 698 699 if (ri->accessfn) { 700 res = ri->accessfn(env, ri, isread); 701 } 702 703 /* 704 * If the access function indicates a trap from EL0 to EL1 then 705 * that always takes priority over the HSTR_EL2 trap. (If it indicates 706 * a trap to EL3, then the HSTR_EL2 trap takes priority; if it indicates 707 * a trap to EL2, then the syndrome is the same either way so we don't 708 * care whether technically the architecture says that HSTR_EL2 trap or 709 * the other trap takes priority. So we take the "check HSTR_EL2" path 710 * for all of those cases.) 711 */ 712 if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) == 0) && 713 arm_current_el(env) == 0) { 714 goto fail; 715 } 716 717 /* 718 * HSTR_EL2 traps from EL1 are checked earlier, in generated code; 719 * we only need to check here for traps from EL0. 720 */ 721 if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 && 722 arm_is_el2_enabled(env) && 723 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 724 uint32_t mask = 1 << ri->crn; 725 726 if (ri->type & ARM_CP_64BIT) { 727 mask = 1 << ri->crm; 728 } 729 730 /* T4 and T14 are RES0 */ 731 mask &= ~((1 << 4) | (1 << 14)); 732 733 if (env->cp15.hstr_el2 & mask) { 734 res = CP_ACCESS_TRAP_EL2; 735 goto fail; 736 } 737 } 738 739 /* 740 * Fine-grained traps also are lower priority than undef-to-EL1, 741 * higher priority than trap-to-EL3, and we don't care about priority 742 * order with other EL2 traps because the syndrome value is the same. 743 */ 744 if (arm_fgt_active(env, arm_current_el(env))) { 745 uint64_t trapword = 0; 746 unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX); 747 unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS); 748 bool rev = FIELD_EX32(ri->fgt, FGT, REV); 749 bool trapbit; 750 751 if (ri->fgt & FGT_EXEC) { 752 assert(idx < ARRAY_SIZE(env->cp15.fgt_exec)); 753 trapword = env->cp15.fgt_exec[idx]; 754 } else if (isread && (ri->fgt & FGT_R)) { 755 assert(idx < ARRAY_SIZE(env->cp15.fgt_read)); 756 trapword = env->cp15.fgt_read[idx]; 757 } else if (!isread && (ri->fgt & FGT_W)) { 758 assert(idx < ARRAY_SIZE(env->cp15.fgt_write)); 759 trapword = env->cp15.fgt_write[idx]; 760 } 761 762 trapbit = extract64(trapword, bitpos, 1); 763 if (trapbit != rev) { 764 res = CP_ACCESS_TRAP_EL2; 765 goto fail; 766 } 767 } 768 769 if (likely(res == CP_ACCESS_OK)) { 770 return ri; 771 } 772 773 fail: 774 switch (res & ~CP_ACCESS_EL_MASK) { 775 case CP_ACCESS_TRAP: 776 break; 777 case CP_ACCESS_TRAP_UNCATEGORIZED: 778 /* Only CP_ACCESS_TRAP traps are direct to a specified EL */ 779 assert((res & CP_ACCESS_EL_MASK) == 0); 780 if (cpu_isar_feature(aa64_ids, cpu) && isread && 781 arm_cpreg_in_idspace(ri)) { 782 /* 783 * FEAT_IDST says this should be reported as EC_SYSTEMREGISTERTRAP, 784 * not EC_UNCATEGORIZED 785 */ 786 break; 787 } 788 syndrome = syn_uncategorized(); 789 break; 790 default: 791 g_assert_not_reached(); 792 } 793 794 target_el = res & CP_ACCESS_EL_MASK; 795 switch (target_el) { 796 case 0: 797 target_el = exception_target_el(env); 798 break; 799 case 2: 800 assert(arm_current_el(env) != 3); 801 assert(arm_is_el2_enabled(env)); 802 break; 803 case 3: 804 assert(arm_feature(env, ARM_FEATURE_EL3)); 805 break; 806 default: 807 /* No "direct" traps to EL1 */ 808 g_assert_not_reached(); 809 } 810 811 raise_exception(env, EXCP_UDEF, syndrome, target_el); 812 } 813 814 const void *HELPER(lookup_cp_reg)(CPUARMState *env, uint32_t key) 815 { 816 ARMCPU *cpu = env_archcpu(env); 817 const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, key); 818 819 assert(ri != NULL); 820 return ri; 821 } 822 823 /* 824 * Test for HCR_EL2.TIDCP at EL1. 825 * Since implementation defined registers are rare, and within QEMU 826 * most of them are no-op, do not waste HFLAGS space for this and 827 * always use a helper. 828 */ 829 void HELPER(tidcp_el1)(CPUARMState *env, uint32_t syndrome) 830 { 831 if (arm_hcr_el2_eff(env) & HCR_TIDCP) { 832 raise_exception_ra(env, EXCP_UDEF, syndrome, 2, GETPC()); 833 } 834 } 835 836 /* 837 * Similarly, for FEAT_TIDCP1 at EL0. 838 * We have already checked for the presence of the feature. 839 */ 840 void HELPER(tidcp_el0)(CPUARMState *env, uint32_t syndrome) 841 { 842 /* See arm_sctlr(), but we also need the sctlr el. */ 843 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); 844 int target_el = mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1; 845 846 /* 847 * The bit is not valid unless the target el is aa64, but since the 848 * bit test is simpler perform that first and check validity after. 849 */ 850 if ((env->cp15.sctlr_el[target_el] & SCTLR_TIDCP) 851 && arm_el_is_aa64(env, target_el)) { 852 raise_exception_ra(env, EXCP_UDEF, syndrome, target_el, GETPC()); 853 } 854 } 855 856 void HELPER(set_cp_reg)(CPUARMState *env, const void *rip, uint32_t value) 857 { 858 const ARMCPRegInfo *ri = rip; 859 860 if (ri->type & ARM_CP_IO) { 861 bql_lock(); 862 ri->writefn(env, ri, value); 863 bql_unlock(); 864 } else { 865 ri->writefn(env, ri, value); 866 } 867 } 868 869 uint32_t HELPER(get_cp_reg)(CPUARMState *env, const void *rip) 870 { 871 const ARMCPRegInfo *ri = rip; 872 uint32_t res; 873 874 if (ri->type & ARM_CP_IO) { 875 bql_lock(); 876 res = ri->readfn(env, ri); 877 bql_unlock(); 878 } else { 879 res = ri->readfn(env, ri); 880 } 881 882 return res; 883 } 884 885 void HELPER(set_cp_reg64)(CPUARMState *env, const void *rip, uint64_t value) 886 { 887 const ARMCPRegInfo *ri = rip; 888 889 if (ri->type & ARM_CP_IO) { 890 bql_lock(); 891 ri->writefn(env, ri, value); 892 bql_unlock(); 893 } else { 894 ri->writefn(env, ri, value); 895 } 896 } 897 898 uint64_t HELPER(get_cp_reg64)(CPUARMState *env, const void *rip) 899 { 900 const ARMCPRegInfo *ri = rip; 901 uint64_t res; 902 903 if (ri->type & ARM_CP_IO) { 904 bql_lock(); 905 res = ri->readfn(env, ri); 906 bql_unlock(); 907 } else { 908 res = ri->readfn(env, ri); 909 } 910 911 return res; 912 } 913 914 void HELPER(pre_hvc)(CPUARMState *env) 915 { 916 ARMCPU *cpu = env_archcpu(env); 917 int cur_el = arm_current_el(env); 918 /* FIXME: Use actual secure state. */ 919 bool secure = false; 920 bool undef; 921 922 if (arm_is_psci_call(cpu, EXCP_HVC)) { 923 /* If PSCI is enabled and this looks like a valid PSCI call then 924 * that overrides the architecturally mandated HVC behaviour. 925 */ 926 return; 927 } 928 929 if (!arm_feature(env, ARM_FEATURE_EL2)) { 930 /* If EL2 doesn't exist, HVC always UNDEFs */ 931 undef = true; 932 } else if (arm_feature(env, ARM_FEATURE_EL3)) { 933 /* EL3.HCE has priority over EL2.HCD. */ 934 undef = !(env->cp15.scr_el3 & SCR_HCE); 935 } else { 936 undef = env->cp15.hcr_el2 & HCR_HCD; 937 } 938 939 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state. 940 * For ARMv8/AArch64, HVC is allowed in EL3. 941 * Note that we've already trapped HVC from EL0 at translation 942 * time. 943 */ 944 if (secure && (!is_a64(env) || cur_el == 1)) { 945 undef = true; 946 } 947 948 if (undef) { 949 raise_exception(env, EXCP_UDEF, syn_uncategorized(), 950 exception_target_el(env)); 951 } 952 } 953 954 void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) 955 { 956 ARMCPU *cpu = env_archcpu(env); 957 int cur_el = arm_current_el(env); 958 bool secure = arm_is_secure(env); 959 bool smd_flag = env->cp15.scr_el3 & SCR_SMD; 960 961 /* 962 * SMC behaviour is summarized in the following table. 963 * This helper handles the "Trap to EL2" and "Undef insn" cases. 964 * The "Trap to EL3" and "PSCI call" cases are handled in the exception 965 * helper. 966 * 967 * -> ARM_FEATURE_EL3 and !SMD 968 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 969 * 970 * Conduit SMC, valid call Trap to EL2 PSCI Call 971 * Conduit SMC, inval call Trap to EL2 Trap to EL3 972 * Conduit not SMC Trap to EL2 Trap to EL3 973 * 974 * 975 * -> ARM_FEATURE_EL3 and SMD 976 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 977 * 978 * Conduit SMC, valid call Trap to EL2 PSCI Call 979 * Conduit SMC, inval call Trap to EL2 Undef insn 980 * Conduit not SMC Trap to EL2 Undef insn 981 * 982 * 983 * -> !ARM_FEATURE_EL3 984 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 985 * 986 * Conduit SMC, valid call Trap to EL2 PSCI Call 987 * Conduit SMC, inval call Trap to EL2 Undef insn 988 * Conduit not SMC Undef or trap[1] Undef insn 989 * 990 * [1] In this case: 991 * - if HCR_EL2.NV == 1 we must trap to EL2 992 * - if HCR_EL2.NV == 0 then newer architecture revisions permit 993 * AArch64 (but not AArch32) to trap to EL2 as an IMPDEF choice 994 * - otherwise we must UNDEF 995 * We take the IMPDEF choice to always UNDEF if HCR_EL2.NV == 0. 996 */ 997 998 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state. 999 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization 1000 * extensions, SMD only applies to NS state. 1001 * On ARMv7 without the Virtualization extensions, the SMD bit 1002 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(), 1003 * so we need not special case this here. 1004 */ 1005 bool smd = arm_feature(env, ARM_FEATURE_AARCH64) ? smd_flag 1006 : smd_flag && !secure; 1007 1008 if (!arm_feature(env, ARM_FEATURE_EL3) && 1009 !(arm_hcr_el2_eff(env) & HCR_NV) && 1010 cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { 1011 /* 1012 * If we have no EL3 then traditionally SMC always UNDEFs and can't be 1013 * trapped to EL2. For nested virtualization, SMC can be trapped to 1014 * the outer hypervisor. PSCI-via-SMC is a sort of ersatz EL3 1015 * firmware within QEMU, and we want an EL2 guest to be able 1016 * to forbid its EL1 from making PSCI calls into QEMU's 1017 * "firmware" via HCR.TSC, so for these purposes treat 1018 * PSCI-via-SMC as implying an EL3. 1019 * This handles the very last line of the previous table. 1020 */ 1021 raise_exception(env, EXCP_UDEF, syn_uncategorized(), 1022 exception_target_el(env)); 1023 } 1024 1025 if (cur_el == 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) { 1026 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. 1027 * We also want an EL2 guest to be able to forbid its EL1 from 1028 * making PSCI calls into QEMU's "firmware" via HCR.TSC. 1029 * This handles all the "Trap to EL2" cases of the previous table. 1030 */ 1031 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); 1032 } 1033 1034 /* Catch the two remaining "Undef insn" cases of the previous table: 1035 * - PSCI conduit is SMC but we don't have a valid PCSI call, 1036 * - We don't have EL3 or SMD is set. 1037 */ 1038 if (!arm_is_psci_call(cpu, EXCP_SMC) && 1039 (smd || !arm_feature(env, ARM_FEATURE_EL3))) { 1040 raise_exception(env, EXCP_UDEF, syn_uncategorized(), 1041 exception_target_el(env)); 1042 } 1043 } 1044 1045 /* ??? Flag setting arithmetic is awkward because we need to do comparisons. 1046 The only way to do that in TCG is a conditional branch, which clobbers 1047 all our temporaries. For now implement these as helper functions. */ 1048 1049 /* Similarly for variable shift instructions. */ 1050 1051 uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i) 1052 { 1053 int shift = i & 0xff; 1054 if (shift >= 32) { 1055 if (shift == 32) 1056 env->CF = x & 1; 1057 else 1058 env->CF = 0; 1059 return 0; 1060 } else if (shift != 0) { 1061 env->CF = (x >> (32 - shift)) & 1; 1062 return x << shift; 1063 } 1064 return x; 1065 } 1066 1067 uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i) 1068 { 1069 int shift = i & 0xff; 1070 if (shift >= 32) { 1071 if (shift == 32) 1072 env->CF = (x >> 31) & 1; 1073 else 1074 env->CF = 0; 1075 return 0; 1076 } else if (shift != 0) { 1077 env->CF = (x >> (shift - 1)) & 1; 1078 return x >> shift; 1079 } 1080 return x; 1081 } 1082 1083 uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i) 1084 { 1085 int shift = i & 0xff; 1086 if (shift >= 32) { 1087 env->CF = (x >> 31) & 1; 1088 return (int32_t)x >> 31; 1089 } else if (shift != 0) { 1090 env->CF = (x >> (shift - 1)) & 1; 1091 return (int32_t)x >> shift; 1092 } 1093 return x; 1094 } 1095 1096 uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i) 1097 { 1098 int shift1, shift; 1099 shift1 = i & 0xff; 1100 shift = shift1 & 0x1f; 1101 if (shift == 0) { 1102 if (shift1 != 0) 1103 env->CF = (x >> 31) & 1; 1104 return x; 1105 } else { 1106 env->CF = (x >> (shift - 1)) & 1; 1107 return ((uint32_t)x >> shift) | (x << (32 - shift)); 1108 } 1109 } 1110 1111 void HELPER(probe_access)(CPUARMState *env, target_ulong ptr, 1112 uint32_t access_type, uint32_t mmu_idx, 1113 uint32_t size) 1114 { 1115 uint32_t in_page = -((uint32_t)ptr | TARGET_PAGE_SIZE); 1116 uintptr_t ra = GETPC(); 1117 1118 if (likely(size <= in_page)) { 1119 probe_access(env, ptr, size, access_type, mmu_idx, ra); 1120 } else { 1121 probe_access(env, ptr, in_page, access_type, mmu_idx, ra); 1122 probe_access(env, ptr + in_page, size - in_page, 1123 access_type, mmu_idx, ra); 1124 } 1125 } 1126 1127 /* 1128 * This function corresponds to AArch64.vESBOperation(). 1129 * Note that the AArch32 version is not functionally different. 1130 */ 1131 void HELPER(vesb)(CPUARMState *env) 1132 { 1133 /* 1134 * The EL2Enabled() check is done inside arm_hcr_el2_eff, 1135 * and will return HCR_EL2.VSE == 0, so nothing happens. 1136 */ 1137 uint64_t hcr = arm_hcr_el2_eff(env); 1138 bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO); 1139 bool pending = enabled && (hcr & HCR_VSE); 1140 bool masked = (env->daif & PSTATE_A); 1141 1142 /* If VSE pending and masked, defer the exception. */ 1143 if (pending && masked) { 1144 uint32_t syndrome; 1145 1146 if (arm_el_is_aa64(env, 1)) { 1147 /* Copy across IDS and ISS from VSESR. */ 1148 syndrome = env->cp15.vsesr_el2 & 0x1ffffff; 1149 } else { 1150 ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal }; 1151 1152 if (extended_addresses_enabled(env)) { 1153 syndrome = arm_fi_to_lfsc(&fi); 1154 } else { 1155 syndrome = arm_fi_to_sfsc(&fi); 1156 } 1157 /* Copy across AET and ExT from VSESR. */ 1158 syndrome |= env->cp15.vsesr_el2 & 0xd000; 1159 } 1160 1161 /* Set VDISR_EL2.A along with the syndrome. */ 1162 env->cp15.vdisr_el2 = syndrome | (1u << 31); 1163 1164 /* Clear pending virtual SError */ 1165 env->cp15.hcr_el2 &= ~HCR_VSE; 1166 cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); 1167 } 1168 } 1169