xref: /openbmc/qemu/target/arm/tcg/neon-dp.decode (revision 1b063fe2) 
1# AArch32 Neon data-processing instruction descriptions
2#
3#  Copyright (c) 2020 Linaro, Ltd
4#
5# This library is free software; you can redistribute it and/or
6# modify it under the terms of the GNU Lesser General Public
7# License as published by the Free Software Foundation; either
8# version 2.1 of the License, or (at your option) any later version.
9#
10# This library is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13# Lesser General Public License for more details.
14#
15# You should have received a copy of the GNU Lesser General Public
16# License along with this library; if not, see <http://www.gnu.org/licenses/>.
17
18#
19# This file is processed by scripts/decodetree.py
20#
21# VFP/Neon register fields; same as vfp.decode
22%vm_dp  5:1 0:4
23%vn_dp  7:1 16:4
24%vd_dp  22:1 12:4
25
26# Encodings for Neon data processing instructions where the T32 encoding
27# is a simple transformation of the A32 encoding.
28# More specifically, this file covers instructions where the A32 encoding is
29#   0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
30# and the T32 encoding is
31#   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
32# This file works on the A32 encoding only; calling code for T32 has to
33# transform the insn into the A32 version first.
34
35######################################################################
36# 3-reg-same grouping:
37# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
38######################################################################
39
40&3same vm vn vd q size
41
42@3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
43                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
44
45@3same_q0        .... ... . . . size:2 .... .... .... . 0 . . .... \
46                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
47
48# For FP insns the high bit of 'size' is used as part of opcode decode,
49# and the 'size' bit is 0 for 32-bit float and 1 for 16-bit float.
50# This converts this encoding to the same MO_8/16/32/64 values that the
51# integer neon insns use.
52%3same_fp_size   20:1 !function=neon_3same_fp_size
53
54@3same_fp        .... ... . . . . . .... .... .... . q:1 . . .... \
55                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%3same_fp_size
56@3same_fp_q0     .... ... . . . . . .... .... .... . 0 . . .... \
57                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0 size=%3same_fp_size
58
59VHADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
60VHADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
61VQADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
62VQADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
63
64VRHADD_S_3s      1111 001 0 0 . .. .... .... 0001 . . . 0 .... @3same
65VRHADD_U_3s      1111 001 1 0 . .. .... .... 0001 . . . 0 .... @3same
66
67@3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
68                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
69
70VAND_3s          1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
71VBIC_3s          1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
72VORR_3s          1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
73VORN_3s          1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
74VEOR_3s          1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
75VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
76VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
77VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
78
79VHSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 0 .... @3same
80VHSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 0 .... @3same
81
82VQSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
83VQSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
84
85VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
86VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
87VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
88VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
89
90# The _rev suffix indicates that Vn and Vm are reversed. This is
91# the case for shifts. In the Arm ARM these insns are documented
92# with the Vm and Vn fields in their usual places, but in the
93# assembly the operands are listed "backwards", ie in the order
94# Dd, Dm, Dn where other insns use Dd, Dn, Dm. For QEMU we choose
95# to consider Vm and Vn as being in different fields in the insn,
96# which allows us to avoid special-casing shifts in the trans_
97# function code. We would otherwise need to manually swap the operands
98# over to call Neon helper functions that are shared with AArch64,
99# which does not have this odd reversed-operand situation.
100@3same_rev       .... ... . . . size:2 .... .... .... . q:1 . . .... \
101                 &3same vn=%vm_dp vm=%vn_dp vd=%vd_dp
102
103VSHL_S_3s        1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev
104VSHL_U_3s        1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev
105VQSHL_S_3s       1111 001 0 0 . .. .... .... 0100 . . . 1 .... @3same_rev
106VQSHL_U_3s       1111 001 1 0 . .. .... .... 0100 . . . 1 .... @3same_rev
107VRSHL_S_3s       1111 001 0 0 . .. .... .... 0101 . . . 0 .... @3same_rev
108VRSHL_U_3s       1111 001 1 0 . .. .... .... 0101 . . . 0 .... @3same_rev
109VQRSHL_S_3s      1111 001 0 0 . .. .... .... 0101 . . . 1 .... @3same_rev
110VQRSHL_U_3s      1111 001 1 0 . .. .... .... 0101 . . . 1 .... @3same_rev
111
112VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
113VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
114VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
115VMIN_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
116
117VABD_S_3s        1111 001 0 0 . .. .... .... 0111 . . . 0 .... @3same
118VABD_U_3s        1111 001 1 0 . .. .... .... 0111 . . . 0 .... @3same
119
120VABA_S_3s        1111 001 0 0 . .. .... .... 0111 . . . 1 .... @3same
121VABA_U_3s        1111 001 1 0 . .. .... .... 0111 . . . 1 .... @3same
122
123VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
124VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
125
126VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
127VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
128
129VMLA_3s          1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
130VMLS_3s          1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
131
132VMUL_3s          1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
133VMUL_p_3s        1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
134
135VPMAX_S_3s       1111 001 0 0 . .. .... .... 1010 . . . 0 .... @3same_q0
136VPMAX_U_3s       1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0
137
138VPMIN_S_3s       1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
139VPMIN_U_3s       1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0
140
141VQDMULH_3s       1111 001 0 0 . .. .... .... 1011 . . . 0 .... @3same
142VQRDMULH_3s      1111 001 1 0 . .. .... .... 1011 . . . 0 .... @3same
143
144VPADD_3s         1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
145
146VQRDMLAH_3s      1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
147
148@3same_crypto    .... .... .... .... .... .... .... .... \
149                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1
150
151SHA1C_3s         1111 001 0 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
152SHA1P_3s         1111 001 0 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
153SHA1M_3s         1111 001 0 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
154SHA1SU0_3s       1111 001 0 0 . 11 .... .... 1100 . 1 . 0 .... @3same_crypto
155SHA256H_3s       1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto
156SHA256H2_3s      1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto
157SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto
158
159VFMA_fp_3s       1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp
160VFMS_fp_3s       1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp
161
162VQRDMLSH_3s      1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same
163
164VADD_fp_3s       1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp
165VSUB_fp_3s       1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
166VPADD_fp_3s      1111 001 1 0 . 0 . .... .... 1101 ... 0 .... @3same_fp_q0
167VABD_fp_3s       1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
168VMLA_fp_3s       1111 001 0 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
169VMLS_fp_3s       1111 001 0 0 . 1 . .... .... 1101 ... 1 .... @3same_fp
170VMUL_fp_3s       1111 001 1 0 . 0 . .... .... 1101 ... 1 .... @3same_fp
171VCEQ_fp_3s       1111 001 0 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
172VCGE_fp_3s       1111 001 1 0 . 0 . .... .... 1110 ... 0 .... @3same_fp
173VACGE_fp_3s      1111 001 1 0 . 0 . .... .... 1110 ... 1 .... @3same_fp
174VCGT_fp_3s       1111 001 1 0 . 1 . .... .... 1110 ... 0 .... @3same_fp
175VACGT_fp_3s      1111 001 1 0 . 1 . .... .... 1110 ... 1 .... @3same_fp
176VMAX_fp_3s       1111 001 0 0 . 0 . .... .... 1111 ... 0 .... @3same_fp
177VMIN_fp_3s       1111 001 0 0 . 1 . .... .... 1111 ... 0 .... @3same_fp
178VPMAX_fp_3s      1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0
179VPMIN_fp_3s      1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0
180VRECPS_fp_3s     1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
181VRSQRTS_fp_3s    1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
182VMAXNM_fp_3s     1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
183VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
184
185######################################################################
186# 2-reg-and-shift grouping:
187# 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4
188######################################################################
189&2reg_shift vm vd q shift size
190
191# Right shifts are encoded as N - shift, where N is the element size in bits.
192%neon_rshift_i6  16:6 !function=rsub_64
193%neon_rshift_i5  16:5 !function=rsub_32
194%neon_rshift_i4  16:4 !function=rsub_16
195%neon_rshift_i3  16:3 !function=rsub_8
196
197@2reg_shr_d      .... ... . . . ......  .... .... 1 q:1 . . .... \
198                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
199@2reg_shr_s      .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
200                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
201@2reg_shr_h      .... ... . . . 01 .... .... .... 0 q:1 . . .... \
202                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
203@2reg_shr_b      .... ... . . . 001 ... .... .... 0 q:1 . . .... \
204                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
205
206@2reg_shl_d      .... ... . . . shift:6      .... .... 1 q:1 . . .... \
207                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3
208@2reg_shl_s      .... ... . . . 1 shift:5    .... .... 0 q:1 . . .... \
209                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2
210@2reg_shl_h      .... ... . . . 01 shift:4   .... .... 0 q:1 . . .... \
211                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1
212@2reg_shl_b      .... ... . . . 001 shift:3  .... .... 0 q:1 . . .... \
213                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0
214
215# Narrowing right shifts: here the Q bit is part of the opcode decode
216@2reg_shrn_d     .... ... . . . 1 ..... .... .... 0 . . . .... \
217                 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
218                 shift=%neon_rshift_i5
219@2reg_shrn_s     .... ... . . . 01 .... .... .... 0 . . . .... \
220                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \
221                 shift=%neon_rshift_i4
222@2reg_shrn_h     .... ... . . . 001 ... .... .... 0 . . . .... \
223                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \
224                 shift=%neon_rshift_i3
225
226# Long left shifts: again Q is part of opcode decode
227@2reg_shll_s     .... ... . . . 1 shift:5    .... .... 0 . . . .... \
228                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0
229@2reg_shll_h     .... ... . . . 01 shift:4   .... .... 0 . . . .... \
230                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0
231@2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
232                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
233
234@2reg_vcvt       .... ... . . . 1 ..... .... .... . q:1 . . .... \
235                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
236@2reg_vcvt_f16   .... ... . . . 11 .... .... .... . q:1 . . .... \
237                 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
238
239VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
240VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
241VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
242VSHR_S_2sh       1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
243
244VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d
245VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s
246VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h
247VSHR_U_2sh       1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b
248
249VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
250VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
251VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
252VSRA_S_2sh       1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
253
254VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d
255VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s
256VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h
257VSRA_U_2sh       1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b
258
259VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
260VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
261VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
262VRSHR_S_2sh      1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
263
264VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d
265VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s
266VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h
267VRSHR_U_2sh      1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b
268
269VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
270VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
271VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
272VRSRA_S_2sh      1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
273
274VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d
275VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s
276VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h
277VRSRA_U_2sh      1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b
278
279VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d
280VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s
281VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h
282VSRI_2sh         1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b
283
284VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
285VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
286VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
287VSHL_2sh         1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
288
289VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
290VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
291VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
292VSLI_2sh         1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
293
294VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d
295VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s
296VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h
297VQSHLU_2sh       1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b
298
299VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
300VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
301VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
302VQSHL_S_2sh      1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
303
304VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
305VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
306VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
307VQSHL_U_2sh      1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b
308
309VSHRN_64_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
310VSHRN_32_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
311VSHRN_16_2sh     1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
312
313VRSHRN_64_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
314VRSHRN_32_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
315VRSHRN_16_2sh    1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
316
317VQSHRUN_64_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d
318VQSHRUN_32_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s
319VQSHRUN_16_2sh   1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h
320
321VQRSHRUN_64_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d
322VQRSHRUN_32_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s
323VQRSHRUN_16_2sh  1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h
324
325# VQSHRN with signed input
326VQSHRN_S64_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
327VQSHRN_S32_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
328VQSHRN_S16_2sh   1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
329
330# VQRSHRN with signed input
331VQRSHRN_S64_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
332VQRSHRN_S32_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
333VQRSHRN_S16_2sh  1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
334
335# VQSHRN with unsigned input
336VQSHRN_U64_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d
337VQSHRN_U32_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s
338VQSHRN_U16_2sh   1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h
339
340# VQRSHRN with unsigned input
341VQRSHRN_U64_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d
342VQRSHRN_U32_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s
343VQRSHRN_U16_2sh  1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h
344
345VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
346VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
347VSHLL_S_2sh      1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
348
349VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s
350VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h
351VSHLL_U_2sh      1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b
352
353# VCVT fixed<->float conversions
354VCVT_SH_2sh      1111 001 0 1 . ...... .... 1100 0 . . 1 .... @2reg_vcvt_f16
355VCVT_UH_2sh      1111 001 1 1 . ...... .... 1100 0 . . 1 .... @2reg_vcvt_f16
356VCVT_HS_2sh      1111 001 0 1 . ...... .... 1101 0 . . 1 .... @2reg_vcvt_f16
357VCVT_HU_2sh      1111 001 1 1 . ...... .... 1101 0 . . 1 .... @2reg_vcvt_f16
358
359VCVT_SF_2sh      1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
360VCVT_UF_2sh      1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt
361VCVT_FS_2sh      1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
362VCVT_FU_2sh      1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt
363
364######################################################################
365# 1-reg-and-modified-immediate grouping:
366# 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4
367######################################################################
368
369&1reg_imm        vd q imm cmode op
370
371%asimd_imm_value 24:1 16:3 0:4
372
373@1reg_imm        .... ... . . . ... ... .... .... . q:1 . . .... \
374                 &1reg_imm imm=%asimd_imm_value vd=%vd_dp
375
376# The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but
377# not in a way we can conveniently represent in decodetree without
378# a lot of repetition:
379# VORR: op=0, (cmode & 1) && cmode < 12
380# VBIC: op=1, (cmode & 1) && cmode < 12
381# VMOV: everything else
382# So we have a single decode line and check the cmode/op in the
383# trans function.
384Vimm_1r          1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
385
386######################################################################
387# Within the "two registers, or three registers of different lengths"
388# grouping ([23,4]=0b10), bits [21:20] are either part of the opcode
389# decode: 0b11 for VEXT, two-reg-misc, VTBL, and duplicate-scalar;
390# or they are a size field for the three-reg-different-lengths and
391# two-reg-and-scalar insn groups (where size cannot be 0b11). This
392# is slightly awkward for decodetree: we handle it with this
393# non-exclusive group which contains within it two exclusive groups:
394# one for the size=0b11 patterns, and one for the size-not-0b11
395# patterns. This allows us to check that none of the insns within
396# each subgroup accidentally overlap each other. Note that all the
397# trans functions for the size-not-0b11 patterns must check and
398# return false for size==3.
399######################################################################
400{
401  [
402    ##################################################################
403    # Miscellaneous size=0b11 insns
404    ##################################################################
405    VEXT         1111 001 0 1 . 11 .... .... imm:4 . q:1 . 0 .... \
406                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
407
408    VTBL         1111 001 1 1 . 11 .... .... 10 len:2 . op:1 . 0 .... \
409                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
410
411    VDUP_scalar  1111 001 1 1 . 11 index:3 1 .... 11 000 q:1 . 0 .... \
412                 vm=%vm_dp vd=%vd_dp size=0
413    VDUP_scalar  1111 001 1 1 . 11 index:2 10 .... 11 000 q:1 . 0 .... \
414                 vm=%vm_dp vd=%vd_dp size=1
415    VDUP_scalar  1111 001 1 1 . 11 index:1 100 .... 11 000 q:1 . 0 .... \
416                 vm=%vm_dp vd=%vd_dp size=2
417
418    ##################################################################
419    # 2-reg-misc grouping:
420    # 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4
421    ##################################################################
422
423    &2misc vd vm q size
424
425    @2misc       .... ... .. . .. size:2 .. .... . .... q:1 . . .... \
426                 &2misc vm=%vm_dp vd=%vd_dp
427    @2misc_q0    .... ... .. . .. size:2 .. .... . .... . . . .... \
428                 &2misc vm=%vm_dp vd=%vd_dp q=0
429    @2misc_q1    .... ... .. . .. size:2 .. .... . .... . . . .... \
430                 &2misc vm=%vm_dp vd=%vd_dp q=1
431
432    VREV64       1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc
433    VREV32       1111 001 11 . 11 .. 00 .... 0 0001 . . 0 .... @2misc
434    VREV16       1111 001 11 . 11 .. 00 .... 0 0010 . . 0 .... @2misc
435
436    VPADDL_S     1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc
437    VPADDL_U     1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc
438
439    AESE         1111 001 11 . 11 .. 00 .... 0 0110 0 . 0 .... @2misc_q1
440    AESD         1111 001 11 . 11 .. 00 .... 0 0110 1 . 0 .... @2misc_q1
441    AESMC        1111 001 11 . 11 .. 00 .... 0 0111 0 . 0 .... @2misc_q1
442    AESIMC       1111 001 11 . 11 .. 00 .... 0 0111 1 . 0 .... @2misc_q1
443
444    VCLS         1111 001 11 . 11 .. 00 .... 0 1000 . . 0 .... @2misc
445    VCLZ         1111 001 11 . 11 .. 00 .... 0 1001 . . 0 .... @2misc
446    VCNT         1111 001 11 . 11 .. 00 .... 0 1010 . . 0 .... @2misc
447
448    VMVN         1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc
449
450    VPADAL_S     1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc
451    VPADAL_U     1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc
452
453    VQABS        1111 001 11 . 11 .. 00 .... 0 1110 . . 0 .... @2misc
454    VQNEG        1111 001 11 . 11 .. 00 .... 0 1111 . . 0 .... @2misc
455
456    VCGT0        1111 001 11 . 11 .. 01 .... 0 0000 . . 0 .... @2misc
457    VCGE0        1111 001 11 . 11 .. 01 .... 0 0001 . . 0 .... @2misc
458    VCEQ0        1111 001 11 . 11 .. 01 .... 0 0010 . . 0 .... @2misc
459    VCLE0        1111 001 11 . 11 .. 01 .... 0 0011 . . 0 .... @2misc
460    VCLT0        1111 001 11 . 11 .. 01 .... 0 0100 . . 0 .... @2misc
461
462    SHA1H        1111 001 11 . 11 .. 01 .... 0 0101 1 . 0 .... @2misc_q1
463
464    VABS         1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
465    VNEG         1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
466
467    VCGT0_F      1111 001 11 . 11 .. 01 .... 0 1000 . . 0 .... @2misc
468    VCGE0_F      1111 001 11 . 11 .. 01 .... 0 1001 . . 0 .... @2misc
469    VCEQ0_F      1111 001 11 . 11 .. 01 .... 0 1010 . . 0 .... @2misc
470    VCLE0_F      1111 001 11 . 11 .. 01 .... 0 1011 . . 0 .... @2misc
471    VCLT0_F      1111 001 11 . 11 .. 01 .... 0 1100 . . 0 .... @2misc
472
473    VABS_F       1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc
474    VNEG_F       1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
475
476    VSWP         1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc
477    VTRN         1111 001 11 . 11 .. 10 .... 0 0001 . . 0 .... @2misc
478    VUZP         1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
479    VZIP         1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
480
481    VMOVN        1111 001 11 . 11 .. 10 .... 0 0100 0 . 0 .... @2misc_q0
482    # VQMOVUN: unsigned result (source is always signed)
483    VQMOVUN      1111 001 11 . 11 .. 10 .... 0 0100 1 . 0 .... @2misc_q0
484    # VQMOVN: signed result, source may be signed (_S) or unsigned (_U)
485    VQMOVN_S     1111 001 11 . 11 .. 10 .... 0 0101 0 . 0 .... @2misc_q0
486    VQMOVN_U     1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0
487
488    VSHLL        1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0
489
490    SHA1SU1      1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1
491    SHA256SU0    1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1
492
493    VRINTN       1111 001 11 . 11 .. 10 .... 0 1000 . . 0 .... @2misc
494    VRINTX       1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc
495    VRINTA       1111 001 11 . 11 .. 10 .... 0 1010 . . 0 .... @2misc
496    VRINTZ       1111 001 11 . 11 .. 10 .... 0 1011 . . 0 .... @2misc
497
498    VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0
499    VCVT_B16_F32 1111 001 11 . 11 .. 10 .... 0 1100 1 . 0 .... @2misc_q0
500
501    VRINTM       1111 001 11 . 11 .. 10 .... 0 1101 . . 0 .... @2misc
502
503    VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0
504
505    VRINTP       1111 001 11 . 11 .. 10 .... 0 1111 . . 0 .... @2misc
506
507    VCVTAS       1111 001 11 . 11 .. 11 .... 0 0000 . . 0 .... @2misc
508    VCVTAU       1111 001 11 . 11 .. 11 .... 0 0001 . . 0 .... @2misc
509    VCVTNS       1111 001 11 . 11 .. 11 .... 0 0010 . . 0 .... @2misc
510    VCVTNU       1111 001 11 . 11 .. 11 .... 0 0011 . . 0 .... @2misc
511    VCVTPS       1111 001 11 . 11 .. 11 .... 0 0100 . . 0 .... @2misc
512    VCVTPU       1111 001 11 . 11 .. 11 .... 0 0101 . . 0 .... @2misc
513    VCVTMS       1111 001 11 . 11 .. 11 .... 0 0110 . . 0 .... @2misc
514    VCVTMU       1111 001 11 . 11 .. 11 .... 0 0111 . . 0 .... @2misc
515
516    VRECPE       1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc
517    VRSQRTE      1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc
518    VRECPE_F     1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc
519    VRSQRTE_F    1111 001 11 . 11 .. 11 .... 0 1011 . . 0 .... @2misc
520    VCVT_FS      1111 001 11 . 11 .. 11 .... 0 1100 . . 0 .... @2misc
521    VCVT_FU      1111 001 11 . 11 .. 11 .... 0 1101 . . 0 .... @2misc
522    VCVT_SF      1111 001 11 . 11 .. 11 .... 0 1110 . . 0 .... @2misc
523    VCVT_UF      1111 001 11 . 11 .. 11 .... 0 1111 . . 0 .... @2misc
524  ]
525
526  # Subgroup for size != 0b11
527  [
528    ##################################################################
529    # 3-reg-different-length grouping:
530    # 1111 001 U 1 D sz!=11 Vn:4 Vd:4 opc:4 N 0 M 0 Vm:4
531    ##################################################################
532
533    &3diff vm vn vd size
534
535    @3diff       .... ... . . . size:2 .... .... .... . . . . .... \
536                 &3diff vm=%vm_dp vn=%vn_dp vd=%vd_dp
537
538    VADDL_S_3d   1111 001 0 1 . .. .... .... 0000 . 0 . 0 .... @3diff
539    VADDL_U_3d   1111 001 1 1 . .. .... .... 0000 . 0 . 0 .... @3diff
540
541    VADDW_S_3d   1111 001 0 1 . .. .... .... 0001 . 0 . 0 .... @3diff
542    VADDW_U_3d   1111 001 1 1 . .. .... .... 0001 . 0 . 0 .... @3diff
543
544    VSUBL_S_3d   1111 001 0 1 . .. .... .... 0010 . 0 . 0 .... @3diff
545    VSUBL_U_3d   1111 001 1 1 . .. .... .... 0010 . 0 . 0 .... @3diff
546
547    VSUBW_S_3d   1111 001 0 1 . .. .... .... 0011 . 0 . 0 .... @3diff
548    VSUBW_U_3d   1111 001 1 1 . .. .... .... 0011 . 0 . 0 .... @3diff
549
550    VADDHN_3d    1111 001 0 1 . .. .... .... 0100 . 0 . 0 .... @3diff
551    VRADDHN_3d   1111 001 1 1 . .. .... .... 0100 . 0 . 0 .... @3diff
552
553    VABAL_S_3d   1111 001 0 1 . .. .... .... 0101 . 0 . 0 .... @3diff
554    VABAL_U_3d   1111 001 1 1 . .. .... .... 0101 . 0 . 0 .... @3diff
555
556    VSUBHN_3d    1111 001 0 1 . .. .... .... 0110 . 0 . 0 .... @3diff
557    VRSUBHN_3d   1111 001 1 1 . .. .... .... 0110 . 0 . 0 .... @3diff
558
559    VABDL_S_3d   1111 001 0 1 . .. .... .... 0111 . 0 . 0 .... @3diff
560    VABDL_U_3d   1111 001 1 1 . .. .... .... 0111 . 0 . 0 .... @3diff
561
562    VMLAL_S_3d   1111 001 0 1 . .. .... .... 1000 . 0 . 0 .... @3diff
563    VMLAL_U_3d   1111 001 1 1 . .. .... .... 1000 . 0 . 0 .... @3diff
564
565    VQDMLAL_3d   1111 001 0 1 . .. .... .... 1001 . 0 . 0 .... @3diff
566
567    VMLSL_S_3d   1111 001 0 1 . .. .... .... 1010 . 0 . 0 .... @3diff
568    VMLSL_U_3d   1111 001 1 1 . .. .... .... 1010 . 0 . 0 .... @3diff
569
570    VQDMLSL_3d   1111 001 0 1 . .. .... .... 1011 . 0 . 0 .... @3diff
571
572    VMULL_S_3d   1111 001 0 1 . .. .... .... 1100 . 0 . 0 .... @3diff
573    VMULL_U_3d   1111 001 1 1 . .. .... .... 1100 . 0 . 0 .... @3diff
574
575    VQDMULL_3d   1111 001 0 1 . .. .... .... 1101 . 0 . 0 .... @3diff
576
577    VMULL_P_3d   1111 001 0 1 . .. .... .... 1110 . 0 . 0 .... @3diff
578
579    ##################################################################
580    # 2-regs-plus-scalar grouping:
581    # 1111 001 Q 1 D sz!=11 Vn:4 Vd:4 opc:4 N 1 M 0 Vm:4
582    ##################################################################
583    &2scalar vm vn vd size q
584
585    @2scalar     .... ... q:1 . . size:2 .... .... .... . . . . .... \
586                 &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp
587    # For the 'long' ops the Q bit is part of insn decode
588    @2scalar_q0  .... ... . . . size:2 .... .... .... . . . . .... \
589                 &2scalar vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
590
591    VMLA_2sc     1111 001 . 1 . .. .... .... 0000 . 1 . 0 .... @2scalar
592    VMLA_F_2sc   1111 001 . 1 . .. .... .... 0001 . 1 . 0 .... @2scalar
593
594    VMLAL_S_2sc  1111 001 0 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0
595    VMLAL_U_2sc  1111 001 1 1 . .. .... .... 0010 . 1 . 0 .... @2scalar_q0
596
597    VQDMLAL_2sc  1111 001 0 1 . .. .... .... 0011 . 1 . 0 .... @2scalar_q0
598
599    VMLS_2sc     1111 001 . 1 . .. .... .... 0100 . 1 . 0 .... @2scalar
600    VMLS_F_2sc   1111 001 . 1 . .. .... .... 0101 . 1 . 0 .... @2scalar
601
602    VMLSL_S_2sc  1111 001 0 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0
603    VMLSL_U_2sc  1111 001 1 1 . .. .... .... 0110 . 1 . 0 .... @2scalar_q0
604
605    VQDMLSL_2sc  1111 001 0 1 . .. .... .... 0111 . 1 . 0 .... @2scalar_q0
606
607    VMUL_2sc     1111 001 . 1 . .. .... .... 1000 . 1 . 0 .... @2scalar
608    VMUL_F_2sc   1111 001 . 1 . .. .... .... 1001 . 1 . 0 .... @2scalar
609
610    VMULL_S_2sc  1111 001 0 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0
611    VMULL_U_2sc  1111 001 1 1 . .. .... .... 1010 . 1 . 0 .... @2scalar_q0
612
613    VQDMULL_2sc  1111 001 0 1 . .. .... .... 1011 . 1 . 0 .... @2scalar_q0
614
615    VQDMULH_2sc  1111 001 . 1 . .. .... .... 1100 . 1 . 0 .... @2scalar
616    VQRDMULH_2sc 1111 001 . 1 . .. .... .... 1101 . 1 . 0 .... @2scalar
617
618    VQRDMLAH_2sc 1111 001 . 1 . .. .... .... 1110 . 1 . 0 .... @2scalar
619    VQRDMLSH_2sc 1111 001 . 1 . .. .... .... 1111 . 1 . 0 .... @2scalar
620  ]
621}
622