1 /* 2 * ARM hflags 3 * 4 * This code is licensed under the GNU GPL v2 or later. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 #include "qemu/osdep.h" 9 #include "cpu.h" 10 #include "internals.h" 11 #include "cpu-features.h" 12 #include "exec/helper-proto.h" 13 #include "cpregs.h" 14 15 static inline bool fgt_svc(CPUARMState *env, int el) 16 { 17 /* 18 * Assuming fine-grained-traps are active, return true if we 19 * should be trapping on SVC instructions. Only AArch64 can 20 * trap on an SVC at EL1, but we don't need to special-case this 21 * because if this is AArch32 EL1 then arm_fgt_active() is false. 22 * We also know el is 0 or 1. 23 */ 24 return el == 0 ? 25 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) : 26 FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); 27 } 28 29 /* Return true if memory alignment should be enforced. */ 30 static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) 31 { 32 #ifdef CONFIG_USER_ONLY 33 return false; 34 #else 35 /* Check the alignment enable bit. */ 36 if (sctlr & SCTLR_A) { 37 return true; 38 } 39 40 /* 41 * If translation is disabled, then the default memory type is 42 * Device(-nGnRnE) instead of Normal, which requires that alignment 43 * be enforced. Since this affects all ram, it is most efficient 44 * to handle this during translation. 45 */ 46 if (sctlr & SCTLR_M) { 47 /* Translation enabled: memory type in PTE via MAIR_ELx. */ 48 return false; 49 } 50 if (el < 2 && (arm_hcr_el2_eff(env) & (HCR_DC | HCR_VM))) { 51 /* Stage 2 translation enabled: memory type in PTE. */ 52 return false; 53 } 54 return true; 55 #endif 56 } 57 58 static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, 59 ARMMMUIdx mmu_idx, 60 CPUARMTBFlags flags) 61 { 62 DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); 63 DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); 64 65 if (arm_singlestep_active(env)) { 66 DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); 67 } 68 69 return flags; 70 } 71 72 static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, 73 ARMMMUIdx mmu_idx, 74 CPUARMTBFlags flags) 75 { 76 bool sctlr_b = arm_sctlr_b(env); 77 78 if (sctlr_b) { 79 DP_TBFLAG_A32(flags, SCTLR__B, 1); 80 } 81 if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { 82 DP_TBFLAG_ANY(flags, BE_DATA, 1); 83 } 84 DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); 85 86 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); 87 } 88 89 static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, 90 ARMMMUIdx mmu_idx) 91 { 92 CPUARMTBFlags flags = {}; 93 uint32_t ccr = env->v7m.ccr[env->v7m.secure]; 94 95 /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ 96 if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { 97 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 98 } 99 100 if (arm_v7m_is_handler_mode(env)) { 101 DP_TBFLAG_M32(flags, HANDLER, 1); 102 } 103 104 /* 105 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN 106 * is suppressing them because the requested execution priority 107 * is less than 0. 108 */ 109 if (arm_feature(env, ARM_FEATURE_V8) && 110 !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && 111 (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { 112 DP_TBFLAG_M32(flags, STACKCHECK, 1); 113 } 114 115 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { 116 DP_TBFLAG_M32(flags, SECURE, 1); 117 } 118 119 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); 120 } 121 122 /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ 123 static bool sme_fa64(CPUARMState *env, int el) 124 { 125 if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { 126 return false; 127 } 128 129 if (el <= 1 && !el_is_in_host(env, el)) { 130 if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { 131 return false; 132 } 133 } 134 if (el <= 2 && arm_is_el2_enabled(env)) { 135 if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { 136 return false; 137 } 138 } 139 if (arm_feature(env, ARM_FEATURE_EL3)) { 140 if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { 141 return false; 142 } 143 } 144 145 return true; 146 } 147 148 static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, 149 ARMMMUIdx mmu_idx) 150 { 151 CPUARMTBFlags flags = {}; 152 int el = arm_current_el(env); 153 uint64_t sctlr = arm_sctlr(env, el); 154 155 if (aprofile_require_alignment(env, el, sctlr)) { 156 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 157 } 158 159 if (arm_el_is_aa64(env, 1)) { 160 DP_TBFLAG_A32(flags, VFPEN, 1); 161 } 162 163 if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && 164 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 165 DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); 166 } 167 168 if (arm_fgt_active(env, el)) { 169 DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); 170 if (fgt_svc(env, el)) { 171 DP_TBFLAG_ANY(flags, FGT_SVC, 1); 172 } 173 } 174 175 if (env->uncached_cpsr & CPSR_IL) { 176 DP_TBFLAG_ANY(flags, PSTATE__IL, 1); 177 } 178 179 /* 180 * The SME exception we are testing for is raised via 181 * AArch64.CheckFPAdvSIMDEnabled(), as called from 182 * AArch32.CheckAdvSIMDOrFPEnabled(). 183 */ 184 if (el == 0 185 && FIELD_EX64(env->svcr, SVCR, SM) 186 && (!arm_is_el2_enabled(env) 187 || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) 188 && arm_el_is_aa64(env, 1) 189 && !sme_fa64(env, el)) { 190 DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); 191 } 192 193 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); 194 } 195 196 static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, 197 ARMMMUIdx mmu_idx) 198 { 199 CPUARMTBFlags flags = {}; 200 ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); 201 uint64_t tcr = regime_tcr(env, mmu_idx); 202 uint64_t hcr = arm_hcr_el2_eff(env); 203 uint64_t sctlr; 204 int tbii, tbid; 205 206 DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); 207 208 /* Get control bits for tagged addresses. */ 209 tbid = aa64_va_parameter_tbi(tcr, mmu_idx); 210 tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); 211 212 DP_TBFLAG_A64(flags, TBII, tbii); 213 DP_TBFLAG_A64(flags, TBID, tbid); 214 215 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { 216 int sve_el = sve_exception_el(env, el); 217 218 /* 219 * If either FP or SVE are disabled, translator does not need len. 220 * If SVE EL > FP EL, FP exception has precedence, and translator 221 * does not need SVE EL. Save potential re-translations by forcing 222 * the unneeded data to zero. 223 */ 224 if (fp_el != 0) { 225 if (sve_el > fp_el) { 226 sve_el = 0; 227 } 228 } else if (sve_el == 0) { 229 DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); 230 } 231 DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); 232 } 233 if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { 234 int sme_el = sme_exception_el(env, el); 235 bool sm = FIELD_EX64(env->svcr, SVCR, SM); 236 237 DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); 238 if (sme_el == 0) { 239 /* Similarly, do not compute SVL if SME is disabled. */ 240 int svl = sve_vqm1_for_el_sm(env, el, true); 241 DP_TBFLAG_A64(flags, SVL, svl); 242 if (sm) { 243 /* If SVE is disabled, we will not have set VL above. */ 244 DP_TBFLAG_A64(flags, VL, svl); 245 } 246 } 247 if (sm) { 248 DP_TBFLAG_A64(flags, PSTATE_SM, 1); 249 DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)); 250 } 251 DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); 252 } 253 254 sctlr = regime_sctlr(env, stage1); 255 256 if (aprofile_require_alignment(env, el, sctlr)) { 257 DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 258 } 259 260 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { 261 DP_TBFLAG_ANY(flags, BE_DATA, 1); 262 } 263 264 if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { 265 /* 266 * In order to save space in flags, we record only whether 267 * pauth is "inactive", meaning all insns are implemented as 268 * a nop, or "active" when some action must be performed. 269 * The decision of which action to take is left to a helper. 270 */ 271 if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { 272 DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); 273 } 274 } 275 276 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { 277 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ 278 if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { 279 DP_TBFLAG_A64(flags, BT, 1); 280 } 281 } 282 283 if (cpu_isar_feature(aa64_lse2, env_archcpu(env))) { 284 if (sctlr & SCTLR_nAA) { 285 DP_TBFLAG_A64(flags, NAA, 1); 286 } 287 } 288 289 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ 290 if (!(env->pstate & PSTATE_UAO)) { 291 switch (mmu_idx) { 292 case ARMMMUIdx_E10_1: 293 case ARMMMUIdx_E10_1_PAN: 294 /* FEAT_NV: NV,NV1 == 1,1 means we don't do UNPRIV accesses */ 295 if ((hcr & (HCR_NV | HCR_NV1)) != (HCR_NV | HCR_NV1)) { 296 DP_TBFLAG_A64(flags, UNPRIV, 1); 297 } 298 break; 299 case ARMMMUIdx_E20_2: 300 case ARMMMUIdx_E20_2_PAN: 301 /* 302 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is 303 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. 304 */ 305 if (env->cp15.hcr_el2 & HCR_TGE) { 306 DP_TBFLAG_A64(flags, UNPRIV, 1); 307 } 308 break; 309 default: 310 break; 311 } 312 } 313 314 if (env->pstate & PSTATE_IL) { 315 DP_TBFLAG_ANY(flags, PSTATE__IL, 1); 316 } 317 318 if (arm_fgt_active(env, el)) { 319 DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); 320 if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { 321 DP_TBFLAG_A64(flags, TRAP_ERET, 1); 322 } 323 if (fgt_svc(env, el)) { 324 DP_TBFLAG_ANY(flags, FGT_SVC, 1); 325 } 326 } 327 328 /* 329 * ERET can also be trapped for FEAT_NV. arm_hcr_el2_eff() takes care 330 * of "is EL2 enabled" and the NV bit can only be set if FEAT_NV is present. 331 */ 332 if (el == 1 && (hcr & HCR_NV)) { 333 DP_TBFLAG_A64(flags, TRAP_ERET, 1); 334 DP_TBFLAG_A64(flags, NV, 1); 335 if (hcr & HCR_NV1) { 336 DP_TBFLAG_A64(flags, NV1, 1); 337 } 338 if (hcr & HCR_NV2) { 339 DP_TBFLAG_A64(flags, NV2, 1); 340 if (hcr & HCR_E2H) { 341 DP_TBFLAG_A64(flags, NV2_MEM_E20, 1); 342 } 343 if (env->cp15.sctlr_el[2] & SCTLR_EE) { 344 DP_TBFLAG_A64(flags, NV2_MEM_BE, 1); 345 } 346 } 347 } 348 349 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { 350 /* 351 * Set MTE_ACTIVE if any access may be Checked, and leave clear 352 * if all accesses must be Unchecked: 353 * 1) If no TBI, then there are no tags in the address to check, 354 * 2) If Tag Check Override, then all accesses are Unchecked, 355 * 3) If Tag Check Fail == 0, then Checked access have no effect, 356 * 4) If no Allocation Tag Access, then all accesses are Unchecked. 357 */ 358 if (allocation_tag_access_enabled(env, el, sctlr)) { 359 DP_TBFLAG_A64(flags, ATA, 1); 360 if (tbid 361 && !(env->pstate & PSTATE_TCO) 362 && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { 363 DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); 364 if (!EX_TBFLAG_A64(flags, UNPRIV)) { 365 /* 366 * In non-unpriv contexts (eg EL0), unpriv load/stores 367 * act like normal ones; duplicate the MTE info to 368 * avoid translate-a64.c having to check UNPRIV to see 369 * whether it is OK to index into MTE_ACTIVE[]. 370 */ 371 DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); 372 } 373 } 374 } 375 /* And again for unprivileged accesses, if required. */ 376 if (EX_TBFLAG_A64(flags, UNPRIV) 377 && tbid 378 && !(env->pstate & PSTATE_TCO) 379 && (sctlr & SCTLR_TCF0) 380 && allocation_tag_access_enabled(env, 0, sctlr)) { 381 DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); 382 } 383 /* 384 * For unpriv tag-setting accesses we also need ATA0. Again, in 385 * contexts where unpriv and normal insns are the same we 386 * duplicate the ATA bit to save effort for translate-a64.c. 387 */ 388 if (EX_TBFLAG_A64(flags, UNPRIV)) { 389 if (allocation_tag_access_enabled(env, 0, sctlr)) { 390 DP_TBFLAG_A64(flags, ATA0, 1); 391 } 392 } else { 393 DP_TBFLAG_A64(flags, ATA0, EX_TBFLAG_A64(flags, ATA)); 394 } 395 /* Cache TCMA as well as TBI. */ 396 DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); 397 } 398 399 return rebuild_hflags_common(env, fp_el, mmu_idx, flags); 400 } 401 402 static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) 403 { 404 int el = arm_current_el(env); 405 int fp_el = fp_exception_el(env, el); 406 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 407 408 if (is_a64(env)) { 409 return rebuild_hflags_a64(env, el, fp_el, mmu_idx); 410 } else if (arm_feature(env, ARM_FEATURE_M)) { 411 return rebuild_hflags_m32(env, fp_el, mmu_idx); 412 } else { 413 return rebuild_hflags_a32(env, fp_el, mmu_idx); 414 } 415 } 416 417 void arm_rebuild_hflags(CPUARMState *env) 418 { 419 env->hflags = rebuild_hflags_internal(env); 420 } 421 422 /* 423 * If we have triggered a EL state change we can't rely on the 424 * translator having passed it to us, we need to recompute. 425 */ 426 void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) 427 { 428 int el = arm_current_el(env); 429 int fp_el = fp_exception_el(env, el); 430 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 431 432 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); 433 } 434 435 void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) 436 { 437 int fp_el = fp_exception_el(env, el); 438 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 439 440 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); 441 } 442 443 /* 444 * If we have triggered a EL state change we can't rely on the 445 * translator having passed it to us, we need to recompute. 446 */ 447 void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) 448 { 449 int el = arm_current_el(env); 450 int fp_el = fp_exception_el(env, el); 451 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 452 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); 453 } 454 455 void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) 456 { 457 int fp_el = fp_exception_el(env, el); 458 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 459 460 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); 461 } 462 463 void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) 464 { 465 int fp_el = fp_exception_el(env, el); 466 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 467 468 env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); 469 } 470 471 void assert_hflags_rebuild_correctly(CPUARMState *env) 472 { 473 #ifdef CONFIG_DEBUG_TCG 474 CPUARMTBFlags c = env->hflags; 475 CPUARMTBFlags r = rebuild_hflags_internal(env); 476 477 if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) { 478 fprintf(stderr, "TCG hflags mismatch " 479 "(current:(0x%08x,0x" TARGET_FMT_lx ")" 480 " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", 481 c.flags, c.flags2, r.flags, r.flags2); 482 abort(); 483 } 484 #endif 485 } 486