1 /* 2 * AArch64 specific helpers 3 * 4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "cpu.h" 23 #include "gdbstub/helpers.h" 24 #include "exec/helper-proto.h" 25 #include "qemu/host-utils.h" 26 #include "qemu/log.h" 27 #include "qemu/main-loop.h" 28 #include "qemu/bitops.h" 29 #include "internals.h" 30 #include "qemu/crc32c.h" 31 #include "exec/exec-all.h" 32 #include "exec/cpu_ldst.h" 33 #include "qemu/int128.h" 34 #include "qemu/atomic128.h" 35 #include "fpu/softfloat.h" 36 #include <zlib.h> /* For crc32 */ 37 38 /* C2.4.7 Multiply and divide */ 39 /* special cases for 0 and LLONG_MIN are mandated by the standard */ 40 uint64_t HELPER(udiv64)(uint64_t num, uint64_t den) 41 { 42 if (den == 0) { 43 return 0; 44 } 45 return num / den; 46 } 47 48 int64_t HELPER(sdiv64)(int64_t num, int64_t den) 49 { 50 if (den == 0) { 51 return 0; 52 } 53 if (num == LLONG_MIN && den == -1) { 54 return LLONG_MIN; 55 } 56 return num / den; 57 } 58 59 uint64_t HELPER(rbit64)(uint64_t x) 60 { 61 return revbit64(x); 62 } 63 64 void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm) 65 { 66 update_spsel(env, imm); 67 } 68 69 static void daif_check(CPUARMState *env, uint32_t op, 70 uint32_t imm, uintptr_t ra) 71 { 72 /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ 73 if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { 74 raise_exception_ra(env, EXCP_UDEF, 75 syn_aa64_sysregtrap(0, extract32(op, 0, 3), 76 extract32(op, 3, 3), 4, 77 imm, 0x1f, 0), 78 exception_target_el(env), ra); 79 } 80 } 81 82 void HELPER(msr_i_daifset)(CPUARMState *env, uint32_t imm) 83 { 84 daif_check(env, 0x1e, imm, GETPC()); 85 env->daif |= (imm << 6) & PSTATE_DAIF; 86 arm_rebuild_hflags(env); 87 } 88 89 void HELPER(msr_i_daifclear)(CPUARMState *env, uint32_t imm) 90 { 91 daif_check(env, 0x1f, imm, GETPC()); 92 env->daif &= ~((imm << 6) & PSTATE_DAIF); 93 arm_rebuild_hflags(env); 94 } 95 96 /* Convert a softfloat float_relation_ (as returned by 97 * the float*_compare functions) to the correct ARM 98 * NZCV flag state. 99 */ 100 static inline uint32_t float_rel_to_flags(int res) 101 { 102 uint64_t flags; 103 switch (res) { 104 case float_relation_equal: 105 flags = PSTATE_Z | PSTATE_C; 106 break; 107 case float_relation_less: 108 flags = PSTATE_N; 109 break; 110 case float_relation_greater: 111 flags = PSTATE_C; 112 break; 113 case float_relation_unordered: 114 default: 115 flags = PSTATE_C | PSTATE_V; 116 break; 117 } 118 return flags; 119 } 120 121 uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status) 122 { 123 return float_rel_to_flags(float16_compare_quiet(x, y, fp_status)); 124 } 125 126 uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status) 127 { 128 return float_rel_to_flags(float16_compare(x, y, fp_status)); 129 } 130 131 uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status) 132 { 133 return float_rel_to_flags(float32_compare_quiet(x, y, fp_status)); 134 } 135 136 uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status) 137 { 138 return float_rel_to_flags(float32_compare(x, y, fp_status)); 139 } 140 141 uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status) 142 { 143 return float_rel_to_flags(float64_compare_quiet(x, y, fp_status)); 144 } 145 146 uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status) 147 { 148 return float_rel_to_flags(float64_compare(x, y, fp_status)); 149 } 150 151 float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp) 152 { 153 float_status *fpst = fpstp; 154 155 a = float32_squash_input_denormal(a, fpst); 156 b = float32_squash_input_denormal(b, fpst); 157 158 if ((float32_is_zero(a) && float32_is_infinity(b)) || 159 (float32_is_infinity(a) && float32_is_zero(b))) { 160 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ 161 return make_float32((1U << 30) | 162 ((float32_val(a) ^ float32_val(b)) & (1U << 31))); 163 } 164 return float32_mul(a, b, fpst); 165 } 166 167 float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp) 168 { 169 float_status *fpst = fpstp; 170 171 a = float64_squash_input_denormal(a, fpst); 172 b = float64_squash_input_denormal(b, fpst); 173 174 if ((float64_is_zero(a) && float64_is_infinity(b)) || 175 (float64_is_infinity(a) && float64_is_zero(b))) { 176 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ 177 return make_float64((1ULL << 62) | 178 ((float64_val(a) ^ float64_val(b)) & (1ULL << 63))); 179 } 180 return float64_mul(a, b, fpst); 181 } 182 183 /* 64bit/double versions of the neon float compare functions */ 184 uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp) 185 { 186 float_status *fpst = fpstp; 187 return -float64_eq_quiet(a, b, fpst); 188 } 189 190 uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp) 191 { 192 float_status *fpst = fpstp; 193 return -float64_le(b, a, fpst); 194 } 195 196 uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp) 197 { 198 float_status *fpst = fpstp; 199 return -float64_lt(b, a, fpst); 200 } 201 202 /* Reciprocal step and sqrt step. Note that unlike the A32/T32 203 * versions, these do a fully fused multiply-add or 204 * multiply-add-and-halve. 205 */ 206 207 uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp) 208 { 209 float_status *fpst = fpstp; 210 211 a = float16_squash_input_denormal(a, fpst); 212 b = float16_squash_input_denormal(b, fpst); 213 214 a = float16_chs(a); 215 if ((float16_is_infinity(a) && float16_is_zero(b)) || 216 (float16_is_infinity(b) && float16_is_zero(a))) { 217 return float16_two; 218 } 219 return float16_muladd(a, b, float16_two, 0, fpst); 220 } 221 222 float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp) 223 { 224 float_status *fpst = fpstp; 225 226 a = float32_squash_input_denormal(a, fpst); 227 b = float32_squash_input_denormal(b, fpst); 228 229 a = float32_chs(a); 230 if ((float32_is_infinity(a) && float32_is_zero(b)) || 231 (float32_is_infinity(b) && float32_is_zero(a))) { 232 return float32_two; 233 } 234 return float32_muladd(a, b, float32_two, 0, fpst); 235 } 236 237 float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp) 238 { 239 float_status *fpst = fpstp; 240 241 a = float64_squash_input_denormal(a, fpst); 242 b = float64_squash_input_denormal(b, fpst); 243 244 a = float64_chs(a); 245 if ((float64_is_infinity(a) && float64_is_zero(b)) || 246 (float64_is_infinity(b) && float64_is_zero(a))) { 247 return float64_two; 248 } 249 return float64_muladd(a, b, float64_two, 0, fpst); 250 } 251 252 uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp) 253 { 254 float_status *fpst = fpstp; 255 256 a = float16_squash_input_denormal(a, fpst); 257 b = float16_squash_input_denormal(b, fpst); 258 259 a = float16_chs(a); 260 if ((float16_is_infinity(a) && float16_is_zero(b)) || 261 (float16_is_infinity(b) && float16_is_zero(a))) { 262 return float16_one_point_five; 263 } 264 return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst); 265 } 266 267 float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp) 268 { 269 float_status *fpst = fpstp; 270 271 a = float32_squash_input_denormal(a, fpst); 272 b = float32_squash_input_denormal(b, fpst); 273 274 a = float32_chs(a); 275 if ((float32_is_infinity(a) && float32_is_zero(b)) || 276 (float32_is_infinity(b) && float32_is_zero(a))) { 277 return float32_one_point_five; 278 } 279 return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst); 280 } 281 282 float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp) 283 { 284 float_status *fpst = fpstp; 285 286 a = float64_squash_input_denormal(a, fpst); 287 b = float64_squash_input_denormal(b, fpst); 288 289 a = float64_chs(a); 290 if ((float64_is_infinity(a) && float64_is_zero(b)) || 291 (float64_is_infinity(b) && float64_is_zero(a))) { 292 return float64_one_point_five; 293 } 294 return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst); 295 } 296 297 /* Pairwise long add: add pairs of adjacent elements into 298 * double-width elements in the result (eg _s8 is an 8x8->16 op) 299 */ 300 uint64_t HELPER(neon_addlp_s8)(uint64_t a) 301 { 302 uint64_t nsignmask = 0x0080008000800080ULL; 303 uint64_t wsignmask = 0x8000800080008000ULL; 304 uint64_t elementmask = 0x00ff00ff00ff00ffULL; 305 uint64_t tmp1, tmp2; 306 uint64_t res, signres; 307 308 /* Extract odd elements, sign extend each to a 16 bit field */ 309 tmp1 = a & elementmask; 310 tmp1 ^= nsignmask; 311 tmp1 |= wsignmask; 312 tmp1 = (tmp1 - nsignmask) ^ wsignmask; 313 /* Ditto for the even elements */ 314 tmp2 = (a >> 8) & elementmask; 315 tmp2 ^= nsignmask; 316 tmp2 |= wsignmask; 317 tmp2 = (tmp2 - nsignmask) ^ wsignmask; 318 319 /* calculate the result by summing bits 0..14, 16..22, etc, 320 * and then adjusting the sign bits 15, 23, etc manually. 321 * This ensures the addition can't overflow the 16 bit field. 322 */ 323 signres = (tmp1 ^ tmp2) & wsignmask; 324 res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask); 325 res ^= signres; 326 327 return res; 328 } 329 330 uint64_t HELPER(neon_addlp_u8)(uint64_t a) 331 { 332 uint64_t tmp; 333 334 tmp = a & 0x00ff00ff00ff00ffULL; 335 tmp += (a >> 8) & 0x00ff00ff00ff00ffULL; 336 return tmp; 337 } 338 339 uint64_t HELPER(neon_addlp_s16)(uint64_t a) 340 { 341 int32_t reslo, reshi; 342 343 reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16); 344 reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48); 345 346 return (uint32_t)reslo | (((uint64_t)reshi) << 32); 347 } 348 349 uint64_t HELPER(neon_addlp_u16)(uint64_t a) 350 { 351 uint64_t tmp; 352 353 tmp = a & 0x0000ffff0000ffffULL; 354 tmp += (a >> 16) & 0x0000ffff0000ffffULL; 355 return tmp; 356 } 357 358 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */ 359 uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp) 360 { 361 float_status *fpst = fpstp; 362 uint16_t val16, sbit; 363 int16_t exp; 364 365 if (float16_is_any_nan(a)) { 366 float16 nan = a; 367 if (float16_is_signaling_nan(a, fpst)) { 368 float_raise(float_flag_invalid, fpst); 369 if (!fpst->default_nan_mode) { 370 nan = float16_silence_nan(a, fpst); 371 } 372 } 373 if (fpst->default_nan_mode) { 374 nan = float16_default_nan(fpst); 375 } 376 return nan; 377 } 378 379 a = float16_squash_input_denormal(a, fpst); 380 381 val16 = float16_val(a); 382 sbit = 0x8000 & val16; 383 exp = extract32(val16, 10, 5); 384 385 if (exp == 0) { 386 return make_float16(deposit32(sbit, 10, 5, 0x1e)); 387 } else { 388 return make_float16(deposit32(sbit, 10, 5, ~exp)); 389 } 390 } 391 392 float32 HELPER(frecpx_f32)(float32 a, void *fpstp) 393 { 394 float_status *fpst = fpstp; 395 uint32_t val32, sbit; 396 int32_t exp; 397 398 if (float32_is_any_nan(a)) { 399 float32 nan = a; 400 if (float32_is_signaling_nan(a, fpst)) { 401 float_raise(float_flag_invalid, fpst); 402 if (!fpst->default_nan_mode) { 403 nan = float32_silence_nan(a, fpst); 404 } 405 } 406 if (fpst->default_nan_mode) { 407 nan = float32_default_nan(fpst); 408 } 409 return nan; 410 } 411 412 a = float32_squash_input_denormal(a, fpst); 413 414 val32 = float32_val(a); 415 sbit = 0x80000000ULL & val32; 416 exp = extract32(val32, 23, 8); 417 418 if (exp == 0) { 419 return make_float32(sbit | (0xfe << 23)); 420 } else { 421 return make_float32(sbit | (~exp & 0xff) << 23); 422 } 423 } 424 425 float64 HELPER(frecpx_f64)(float64 a, void *fpstp) 426 { 427 float_status *fpst = fpstp; 428 uint64_t val64, sbit; 429 int64_t exp; 430 431 if (float64_is_any_nan(a)) { 432 float64 nan = a; 433 if (float64_is_signaling_nan(a, fpst)) { 434 float_raise(float_flag_invalid, fpst); 435 if (!fpst->default_nan_mode) { 436 nan = float64_silence_nan(a, fpst); 437 } 438 } 439 if (fpst->default_nan_mode) { 440 nan = float64_default_nan(fpst); 441 } 442 return nan; 443 } 444 445 a = float64_squash_input_denormal(a, fpst); 446 447 val64 = float64_val(a); 448 sbit = 0x8000000000000000ULL & val64; 449 exp = extract64(float64_val(a), 52, 11); 450 451 if (exp == 0) { 452 return make_float64(sbit | (0x7feULL << 52)); 453 } else { 454 return make_float64(sbit | (~exp & 0x7ffULL) << 52); 455 } 456 } 457 458 float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env) 459 { 460 /* Von Neumann rounding is implemented by using round-to-zero 461 * and then setting the LSB of the result if Inexact was raised. 462 */ 463 float32 r; 464 float_status *fpst = &env->vfp.fp_status; 465 float_status tstat = *fpst; 466 int exflags; 467 468 set_float_rounding_mode(float_round_to_zero, &tstat); 469 set_float_exception_flags(0, &tstat); 470 r = float64_to_float32(a, &tstat); 471 exflags = get_float_exception_flags(&tstat); 472 if (exflags & float_flag_inexact) { 473 r = make_float32(float32_val(r) | 1); 474 } 475 exflags |= get_float_exception_flags(fpst); 476 set_float_exception_flags(exflags, fpst); 477 return r; 478 } 479 480 /* 64-bit versions of the CRC helpers. Note that although the operation 481 * (and the prototypes of crc32c() and crc32() mean that only the bottom 482 * 32 bits of the accumulator and result are used, we pass and return 483 * uint64_t for convenience of the generated code. Unlike the 32-bit 484 * instruction set versions, val may genuinely have 64 bits of data in it. 485 * The upper bytes of val (above the number specified by 'bytes') must have 486 * been zeroed out by the caller. 487 */ 488 uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes) 489 { 490 uint8_t buf[8]; 491 492 stq_le_p(buf, val); 493 494 /* zlib crc32 converts the accumulator and output to one's complement. */ 495 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; 496 } 497 498 uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes) 499 { 500 uint8_t buf[8]; 501 502 stq_le_p(buf, val); 503 504 /* Linux crc32c converts the output to one's complement. */ 505 return crc32c(acc, buf, bytes) ^ 0xffffffff; 506 } 507 508 /* 509 * AdvSIMD half-precision 510 */ 511 512 #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix)) 513 514 #define ADVSIMD_HALFOP(name) \ 515 uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \ 516 { \ 517 float_status *fpst = fpstp; \ 518 return float16_ ## name(a, b, fpst); \ 519 } 520 521 ADVSIMD_HALFOP(add) 522 ADVSIMD_HALFOP(sub) 523 ADVSIMD_HALFOP(mul) 524 ADVSIMD_HALFOP(div) 525 ADVSIMD_HALFOP(min) 526 ADVSIMD_HALFOP(max) 527 ADVSIMD_HALFOP(minnum) 528 ADVSIMD_HALFOP(maxnum) 529 530 #define ADVSIMD_TWOHALFOP(name) \ 531 uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \ 532 { \ 533 float16 a1, a2, b1, b2; \ 534 uint32_t r1, r2; \ 535 float_status *fpst = fpstp; \ 536 a1 = extract32(two_a, 0, 16); \ 537 a2 = extract32(two_a, 16, 16); \ 538 b1 = extract32(two_b, 0, 16); \ 539 b2 = extract32(two_b, 16, 16); \ 540 r1 = float16_ ## name(a1, b1, fpst); \ 541 r2 = float16_ ## name(a2, b2, fpst); \ 542 return deposit32(r1, 16, 16, r2); \ 543 } 544 545 ADVSIMD_TWOHALFOP(add) 546 ADVSIMD_TWOHALFOP(sub) 547 ADVSIMD_TWOHALFOP(mul) 548 ADVSIMD_TWOHALFOP(div) 549 ADVSIMD_TWOHALFOP(min) 550 ADVSIMD_TWOHALFOP(max) 551 ADVSIMD_TWOHALFOP(minnum) 552 ADVSIMD_TWOHALFOP(maxnum) 553 554 /* Data processing - scalar floating-point and advanced SIMD */ 555 static float16 float16_mulx(float16 a, float16 b, void *fpstp) 556 { 557 float_status *fpst = fpstp; 558 559 a = float16_squash_input_denormal(a, fpst); 560 b = float16_squash_input_denormal(b, fpst); 561 562 if ((float16_is_zero(a) && float16_is_infinity(b)) || 563 (float16_is_infinity(a) && float16_is_zero(b))) { 564 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ 565 return make_float16((1U << 14) | 566 ((float16_val(a) ^ float16_val(b)) & (1U << 15))); 567 } 568 return float16_mul(a, b, fpst); 569 } 570 571 ADVSIMD_HALFOP(mulx) 572 ADVSIMD_TWOHALFOP(mulx) 573 574 /* fused multiply-accumulate */ 575 uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c, 576 void *fpstp) 577 { 578 float_status *fpst = fpstp; 579 return float16_muladd(a, b, c, 0, fpst); 580 } 581 582 uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b, 583 uint32_t two_c, void *fpstp) 584 { 585 float_status *fpst = fpstp; 586 float16 a1, a2, b1, b2, c1, c2; 587 uint32_t r1, r2; 588 a1 = extract32(two_a, 0, 16); 589 a2 = extract32(two_a, 16, 16); 590 b1 = extract32(two_b, 0, 16); 591 b2 = extract32(two_b, 16, 16); 592 c1 = extract32(two_c, 0, 16); 593 c2 = extract32(two_c, 16, 16); 594 r1 = float16_muladd(a1, b1, c1, 0, fpst); 595 r2 = float16_muladd(a2, b2, c2, 0, fpst); 596 return deposit32(r1, 16, 16, r2); 597 } 598 599 /* 600 * Floating point comparisons produce an integer result. Softfloat 601 * routines return float_relation types which we convert to the 0/-1 602 * Neon requires. 603 */ 604 605 #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0 606 607 uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp) 608 { 609 float_status *fpst = fpstp; 610 int compare = float16_compare_quiet(a, b, fpst); 611 return ADVSIMD_CMPRES(compare == float_relation_equal); 612 } 613 614 uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp) 615 { 616 float_status *fpst = fpstp; 617 int compare = float16_compare(a, b, fpst); 618 return ADVSIMD_CMPRES(compare == float_relation_greater || 619 compare == float_relation_equal); 620 } 621 622 uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp) 623 { 624 float_status *fpst = fpstp; 625 int compare = float16_compare(a, b, fpst); 626 return ADVSIMD_CMPRES(compare == float_relation_greater); 627 } 628 629 uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp) 630 { 631 float_status *fpst = fpstp; 632 float16 f0 = float16_abs(a); 633 float16 f1 = float16_abs(b); 634 int compare = float16_compare(f0, f1, fpst); 635 return ADVSIMD_CMPRES(compare == float_relation_greater || 636 compare == float_relation_equal); 637 } 638 639 uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp) 640 { 641 float_status *fpst = fpstp; 642 float16 f0 = float16_abs(a); 643 float16 f1 = float16_abs(b); 644 int compare = float16_compare(f0, f1, fpst); 645 return ADVSIMD_CMPRES(compare == float_relation_greater); 646 } 647 648 /* round to integral */ 649 uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status) 650 { 651 return float16_round_to_int(x, fp_status); 652 } 653 654 uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status) 655 { 656 int old_flags = get_float_exception_flags(fp_status), new_flags; 657 float16 ret; 658 659 ret = float16_round_to_int(x, fp_status); 660 661 /* Suppress any inexact exceptions the conversion produced */ 662 if (!(old_flags & float_flag_inexact)) { 663 new_flags = get_float_exception_flags(fp_status); 664 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 665 } 666 667 return ret; 668 } 669 670 /* 671 * Half-precision floating point conversion functions 672 * 673 * There are a multitude of conversion functions with various 674 * different rounding modes. This is dealt with by the calling code 675 * setting the mode appropriately before calling the helper. 676 */ 677 678 uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp) 679 { 680 float_status *fpst = fpstp; 681 682 /* Invalid if we are passed a NaN */ 683 if (float16_is_any_nan(a)) { 684 float_raise(float_flag_invalid, fpst); 685 return 0; 686 } 687 return float16_to_int16(a, fpst); 688 } 689 690 uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp) 691 { 692 float_status *fpst = fpstp; 693 694 /* Invalid if we are passed a NaN */ 695 if (float16_is_any_nan(a)) { 696 float_raise(float_flag_invalid, fpst); 697 return 0; 698 } 699 return float16_to_uint16(a, fpst); 700 } 701 702 static int el_from_spsr(uint32_t spsr) 703 { 704 /* Return the exception level that this SPSR is requesting a return to, 705 * or -1 if it is invalid (an illegal return) 706 */ 707 if (spsr & PSTATE_nRW) { 708 switch (spsr & CPSR_M) { 709 case ARM_CPU_MODE_USR: 710 return 0; 711 case ARM_CPU_MODE_HYP: 712 return 2; 713 case ARM_CPU_MODE_FIQ: 714 case ARM_CPU_MODE_IRQ: 715 case ARM_CPU_MODE_SVC: 716 case ARM_CPU_MODE_ABT: 717 case ARM_CPU_MODE_UND: 718 case ARM_CPU_MODE_SYS: 719 return 1; 720 case ARM_CPU_MODE_MON: 721 /* Returning to Mon from AArch64 is never possible, 722 * so this is an illegal return. 723 */ 724 default: 725 return -1; 726 } 727 } else { 728 if (extract32(spsr, 1, 1)) { 729 /* Return with reserved M[1] bit set */ 730 return -1; 731 } 732 if (extract32(spsr, 0, 4) == 1) { 733 /* return to EL0 with M[0] bit set */ 734 return -1; 735 } 736 return extract32(spsr, 2, 2); 737 } 738 } 739 740 static void cpsr_write_from_spsr_elx(CPUARMState *env, 741 uint32_t val) 742 { 743 uint32_t mask; 744 745 /* Save SPSR_ELx.SS into PSTATE. */ 746 env->pstate = (env->pstate & ~PSTATE_SS) | (val & PSTATE_SS); 747 val &= ~PSTATE_SS; 748 749 /* Move DIT to the correct location for CPSR */ 750 if (val & PSTATE_DIT) { 751 val &= ~PSTATE_DIT; 752 val |= CPSR_DIT; 753 } 754 755 mask = aarch32_cpsr_valid_mask(env->features, \ 756 &env_archcpu(env)->isar); 757 cpsr_write(env, val, mask, CPSRWriteRaw); 758 } 759 760 void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) 761 { 762 int cur_el = arm_current_el(env); 763 unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); 764 uint32_t spsr = env->banked_spsr[spsr_idx]; 765 int new_el; 766 bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; 767 768 aarch64_save_sp(env, cur_el); 769 770 arm_clear_exclusive(env); 771 772 /* We must squash the PSTATE.SS bit to zero unless both of the 773 * following hold: 774 * 1. debug exceptions are currently disabled 775 * 2. singlestep will be active in the EL we return to 776 * We check 1 here and 2 after we've done the pstate/cpsr write() to 777 * transition to the EL we're going to. 778 */ 779 if (arm_generate_debug_exceptions(env)) { 780 spsr &= ~PSTATE_SS; 781 } 782 783 /* 784 * FEAT_RME forbids return from EL3 with an invalid security state. 785 * We don't need an explicit check for FEAT_RME here because we enforce 786 * in scr_write() that you can't set the NSE bit without it. 787 */ 788 if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) { 789 goto illegal_return; 790 } 791 792 new_el = el_from_spsr(spsr); 793 if (new_el == -1) { 794 goto illegal_return; 795 } 796 if (new_el > cur_el || (new_el == 2 && !arm_is_el2_enabled(env))) { 797 /* Disallow return to an EL which is unimplemented or higher 798 * than the current one. 799 */ 800 goto illegal_return; 801 } 802 803 if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) { 804 /* Return to an EL which is configured for a different register width */ 805 goto illegal_return; 806 } 807 808 if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { 809 goto illegal_return; 810 } 811 812 qemu_mutex_lock_iothread(); 813 arm_call_pre_el_change_hook(env_archcpu(env)); 814 qemu_mutex_unlock_iothread(); 815 816 if (!return_to_aa64) { 817 env->aarch64 = false; 818 /* We do a raw CPSR write because aarch64_sync_64_to_32() 819 * will sort the register banks out for us, and we've already 820 * caught all the bad-mode cases in el_from_spsr(). 821 */ 822 cpsr_write_from_spsr_elx(env, spsr); 823 if (!arm_singlestep_active(env)) { 824 env->pstate &= ~PSTATE_SS; 825 } 826 aarch64_sync_64_to_32(env); 827 828 if (spsr & CPSR_T) { 829 env->regs[15] = new_pc & ~0x1; 830 } else { 831 env->regs[15] = new_pc & ~0x3; 832 } 833 helper_rebuild_hflags_a32(env, new_el); 834 qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " 835 "AArch32 EL%d PC 0x%" PRIx32 "\n", 836 cur_el, new_el, env->regs[15]); 837 } else { 838 int tbii; 839 840 env->aarch64 = true; 841 spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar); 842 pstate_write(env, spsr); 843 if (!arm_singlestep_active(env)) { 844 env->pstate &= ~PSTATE_SS; 845 } 846 aarch64_restore_sp(env, new_el); 847 helper_rebuild_hflags_a64(env, new_el); 848 849 /* 850 * Apply TBI to the exception return address. We had to delay this 851 * until after we selected the new EL, so that we could select the 852 * correct TBI+TBID bits. This is made easier by waiting until after 853 * the hflags rebuild, since we can pull the composite TBII field 854 * from there. 855 */ 856 tbii = EX_TBFLAG_A64(env->hflags, TBII); 857 if ((tbii >> extract64(new_pc, 55, 1)) & 1) { 858 /* TBI is enabled. */ 859 int core_mmu_idx = cpu_mmu_index(env, false); 860 if (regime_has_2_ranges(core_to_aa64_mmu_idx(core_mmu_idx))) { 861 new_pc = sextract64(new_pc, 0, 56); 862 } else { 863 new_pc = extract64(new_pc, 0, 56); 864 } 865 } 866 env->pc = new_pc; 867 868 qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " 869 "AArch64 EL%d PC 0x%" PRIx64 "\n", 870 cur_el, new_el, env->pc); 871 } 872 873 /* 874 * Note that cur_el can never be 0. If new_el is 0, then 875 * el0_a64 is return_to_aa64, else el0_a64 is ignored. 876 */ 877 aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); 878 879 qemu_mutex_lock_iothread(); 880 arm_call_el_change_hook(env_archcpu(env)); 881 qemu_mutex_unlock_iothread(); 882 883 return; 884 885 illegal_return: 886 /* Illegal return events of various kinds have architecturally 887 * mandated behaviour: 888 * restore NZCV and DAIF from SPSR_ELx 889 * set PSTATE.IL 890 * restore PC from ELR_ELx 891 * no change to exception level, execution state or stack pointer 892 */ 893 env->pstate |= PSTATE_IL; 894 env->pc = new_pc; 895 spsr &= PSTATE_NZCV | PSTATE_DAIF; 896 spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF); 897 pstate_write(env, spsr); 898 if (!arm_singlestep_active(env)) { 899 env->pstate &= ~PSTATE_SS; 900 } 901 helper_rebuild_hflags_a64(env, cur_el); 902 qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: " 903 "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc); 904 } 905 906 /* 907 * Square Root and Reciprocal square root 908 */ 909 910 uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp) 911 { 912 float_status *s = fpstp; 913 914 return float16_sqrt(a, s); 915 } 916 917 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) 918 { 919 /* 920 * Implement DC ZVA, which zeroes a fixed-length block of memory. 921 * Note that we do not implement the (architecturally mandated) 922 * alignment fault for attempts to use this on Device memory 923 * (which matches the usual QEMU behaviour of not implementing either 924 * alignment faults or any memory attribute handling). 925 */ 926 int blocklen = 4 << env_archcpu(env)->dcz_blocksize; 927 uint64_t vaddr = vaddr_in & ~(blocklen - 1); 928 int mmu_idx = cpu_mmu_index(env, false); 929 void *mem; 930 931 /* 932 * Trapless lookup. In addition to actual invalid page, may 933 * return NULL for I/O, watchpoints, clean pages, etc. 934 */ 935 mem = tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx); 936 937 #ifndef CONFIG_USER_ONLY 938 if (unlikely(!mem)) { 939 uintptr_t ra = GETPC(); 940 941 /* 942 * Trap if accessing an invalid page. DC_ZVA requires that we supply 943 * the original pointer for an invalid page. But watchpoints require 944 * that we probe the actual space. So do both. 945 */ 946 (void) probe_write(env, vaddr_in, 1, mmu_idx, ra); 947 mem = probe_write(env, vaddr, blocklen, mmu_idx, ra); 948 949 if (unlikely(!mem)) { 950 /* 951 * The only remaining reason for mem == NULL is I/O. 952 * Just do a series of byte writes as the architecture demands. 953 */ 954 for (int i = 0; i < blocklen; i++) { 955 cpu_stb_mmuidx_ra(env, vaddr + i, 0, mmu_idx, ra); 956 } 957 return; 958 } 959 } 960 #endif 961 962 memset(mem, 0, blocklen); 963 } 964 965 void HELPER(unaligned_access)(CPUARMState *env, uint64_t addr, 966 uint32_t access_type, uint32_t mmu_idx) 967 { 968 arm_cpu_do_unaligned_access(env_cpu(env), addr, access_type, 969 mmu_idx, GETPC()); 970 } 971