xref: /openbmc/qemu/target/arm/tcg/cpu64.c (revision 27047bd2)
1 /*
2  * QEMU AArch64 TCG CPUs
3  *
4  * Copyright (c) 2013 Linaro Ltd
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version 2
9  * of the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, see
18  * <http://www.gnu.org/licenses/gpl-2.0.html>
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "cpu.h"
24 #include "qemu/module.h"
25 #include "qapi/visitor.h"
26 #include "hw/qdev-properties.h"
27 #include "internals.h"
28 #include "cpregs.h"
29 
30 static void aarch64_a35_initfn(Object *obj)
31 {
32     ARMCPU *cpu = ARM_CPU(obj);
33 
34     cpu->dtb_compatible = "arm,cortex-a35";
35     set_feature(&cpu->env, ARM_FEATURE_V8);
36     set_feature(&cpu->env, ARM_FEATURE_NEON);
37     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
38     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
39     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
40     set_feature(&cpu->env, ARM_FEATURE_EL2);
41     set_feature(&cpu->env, ARM_FEATURE_EL3);
42     set_feature(&cpu->env, ARM_FEATURE_PMU);
43 
44     /* From B2.2 AArch64 identification registers. */
45     cpu->midr = 0x411fd040;
46     cpu->revidr = 0;
47     cpu->ctr = 0x84448004;
48     cpu->isar.id_pfr0 = 0x00000131;
49     cpu->isar.id_pfr1 = 0x00011011;
50     cpu->isar.id_dfr0 = 0x03010066;
51     cpu->id_afr0 = 0;
52     cpu->isar.id_mmfr0 = 0x10201105;
53     cpu->isar.id_mmfr1 = 0x40000000;
54     cpu->isar.id_mmfr2 = 0x01260000;
55     cpu->isar.id_mmfr3 = 0x02102211;
56     cpu->isar.id_isar0 = 0x02101110;
57     cpu->isar.id_isar1 = 0x13112111;
58     cpu->isar.id_isar2 = 0x21232042;
59     cpu->isar.id_isar3 = 0x01112131;
60     cpu->isar.id_isar4 = 0x00011142;
61     cpu->isar.id_isar5 = 0x00011121;
62     cpu->isar.id_aa64pfr0 = 0x00002222;
63     cpu->isar.id_aa64pfr1 = 0;
64     cpu->isar.id_aa64dfr0 = 0x10305106;
65     cpu->isar.id_aa64dfr1 = 0;
66     cpu->isar.id_aa64isar0 = 0x00011120;
67     cpu->isar.id_aa64isar1 = 0;
68     cpu->isar.id_aa64mmfr0 = 0x00101122;
69     cpu->isar.id_aa64mmfr1 = 0;
70     cpu->clidr = 0x0a200023;
71     cpu->dcz_blocksize = 4;
72 
73     /* From B2.4 AArch64 Virtual Memory control registers */
74     cpu->reset_sctlr = 0x00c50838;
75 
76     /* From B2.10 AArch64 performance monitor registers */
77     cpu->isar.reset_pmcr_el0 = 0x410a3000;
78 
79     /* From B2.29 Cache ID registers */
80     cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
81     cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
82     cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
83 
84     /* From B3.5 VGIC Type register */
85     cpu->gic_num_lrs = 4;
86     cpu->gic_vpribits = 5;
87     cpu->gic_vprebits = 5;
88     cpu->gic_pribits = 5;
89 
90     /* From C6.4 Debug ID Register */
91     cpu->isar.dbgdidr = 0x3516d000;
92     /* From C6.5 Debug Device ID Register */
93     cpu->isar.dbgdevid = 0x00110f13;
94     /* From C6.6 Debug Device ID Register 1 */
95     cpu->isar.dbgdevid1 = 0x2;
96 
97     /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
98     /* From 3.2 AArch32 register summary */
99     cpu->reset_fpsid = 0x41034043;
100 
101     /* From 2.2 AArch64 register summary */
102     cpu->isar.mvfr0 = 0x10110222;
103     cpu->isar.mvfr1 = 0x12111111;
104     cpu->isar.mvfr2 = 0x00000043;
105 
106     /* These values are the same with A53/A57/A72. */
107     define_cortex_a72_a57_a53_cp_reginfo(cpu);
108 }
109 
110 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
111                                    void *opaque, Error **errp)
112 {
113     ARMCPU *cpu = ARM_CPU(obj);
114     uint32_t value;
115 
116     /* All vector lengths are disabled when SVE is off. */
117     if (!cpu_isar_feature(aa64_sve, cpu)) {
118         value = 0;
119     } else {
120         value = cpu->sve_max_vq;
121     }
122     visit_type_uint32(v, name, &value, errp);
123 }
124 
125 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
126                                    void *opaque, Error **errp)
127 {
128     ARMCPU *cpu = ARM_CPU(obj);
129     uint32_t max_vq;
130 
131     if (!visit_type_uint32(v, name, &max_vq, errp)) {
132         return;
133     }
134 
135     if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
136         error_setg(errp, "unsupported SVE vector length");
137         error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
138                           ARM_MAX_VQ);
139         return;
140     }
141 
142     cpu->sve_max_vq = max_vq;
143 }
144 
145 static Property arm_cpu_lpa2_property =
146     DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
147 
148 static void aarch64_a55_initfn(Object *obj)
149 {
150     ARMCPU *cpu = ARM_CPU(obj);
151 
152     cpu->dtb_compatible = "arm,cortex-a55";
153     set_feature(&cpu->env, ARM_FEATURE_V8);
154     set_feature(&cpu->env, ARM_FEATURE_NEON);
155     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
156     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
157     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
158     set_feature(&cpu->env, ARM_FEATURE_EL2);
159     set_feature(&cpu->env, ARM_FEATURE_EL3);
160     set_feature(&cpu->env, ARM_FEATURE_PMU);
161 
162     /* Ordered by B2.4 AArch64 registers by functional group */
163     cpu->clidr = 0x82000023;
164     cpu->ctr = 0x84448004; /* L1Ip = VIPT */
165     cpu->dcz_blocksize = 4; /* 64 bytes */
166     cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
167     cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
168     cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
169     cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
170     cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
171     cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
172     cpu->isar.id_aa64pfr0  = 0x0000000010112222ull;
173     cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
174     cpu->id_afr0       = 0x00000000;
175     cpu->isar.id_dfr0  = 0x04010088;
176     cpu->isar.id_isar0 = 0x02101110;
177     cpu->isar.id_isar1 = 0x13112111;
178     cpu->isar.id_isar2 = 0x21232042;
179     cpu->isar.id_isar3 = 0x01112131;
180     cpu->isar.id_isar4 = 0x00011142;
181     cpu->isar.id_isar5 = 0x01011121;
182     cpu->isar.id_isar6 = 0x00000010;
183     cpu->isar.id_mmfr0 = 0x10201105;
184     cpu->isar.id_mmfr1 = 0x40000000;
185     cpu->isar.id_mmfr2 = 0x01260000;
186     cpu->isar.id_mmfr3 = 0x02122211;
187     cpu->isar.id_mmfr4 = 0x00021110;
188     cpu->isar.id_pfr0  = 0x10010131;
189     cpu->isar.id_pfr1  = 0x00011011;
190     cpu->isar.id_pfr2  = 0x00000011;
191     cpu->midr = 0x412FD050;          /* r2p0 */
192     cpu->revidr = 0;
193 
194     /* From B2.23 CCSIDR_EL1 */
195     cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
196     cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
197     cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
198 
199     /* From B2.96 SCTLR_EL3 */
200     cpu->reset_sctlr = 0x30c50838;
201 
202     /* From B4.45 ICH_VTR_EL2 */
203     cpu->gic_num_lrs = 4;
204     cpu->gic_vpribits = 5;
205     cpu->gic_vprebits = 5;
206     cpu->gic_pribits = 5;
207 
208     cpu->isar.mvfr0 = 0x10110222;
209     cpu->isar.mvfr1 = 0x13211111;
210     cpu->isar.mvfr2 = 0x00000043;
211 
212     /* From D5.4 AArch64 PMU register summary */
213     cpu->isar.reset_pmcr_el0 = 0x410b3000;
214 }
215 
216 static void aarch64_a72_initfn(Object *obj)
217 {
218     ARMCPU *cpu = ARM_CPU(obj);
219 
220     cpu->dtb_compatible = "arm,cortex-a72";
221     set_feature(&cpu->env, ARM_FEATURE_V8);
222     set_feature(&cpu->env, ARM_FEATURE_NEON);
223     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
224     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
225     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
226     set_feature(&cpu->env, ARM_FEATURE_EL2);
227     set_feature(&cpu->env, ARM_FEATURE_EL3);
228     set_feature(&cpu->env, ARM_FEATURE_PMU);
229     cpu->midr = 0x410fd083;
230     cpu->revidr = 0x00000000;
231     cpu->reset_fpsid = 0x41034080;
232     cpu->isar.mvfr0 = 0x10110222;
233     cpu->isar.mvfr1 = 0x12111111;
234     cpu->isar.mvfr2 = 0x00000043;
235     cpu->ctr = 0x8444c004;
236     cpu->reset_sctlr = 0x00c50838;
237     cpu->isar.id_pfr0 = 0x00000131;
238     cpu->isar.id_pfr1 = 0x00011011;
239     cpu->isar.id_dfr0 = 0x03010066;
240     cpu->id_afr0 = 0x00000000;
241     cpu->isar.id_mmfr0 = 0x10201105;
242     cpu->isar.id_mmfr1 = 0x40000000;
243     cpu->isar.id_mmfr2 = 0x01260000;
244     cpu->isar.id_mmfr3 = 0x02102211;
245     cpu->isar.id_isar0 = 0x02101110;
246     cpu->isar.id_isar1 = 0x13112111;
247     cpu->isar.id_isar2 = 0x21232042;
248     cpu->isar.id_isar3 = 0x01112131;
249     cpu->isar.id_isar4 = 0x00011142;
250     cpu->isar.id_isar5 = 0x00011121;
251     cpu->isar.id_aa64pfr0 = 0x00002222;
252     cpu->isar.id_aa64dfr0 = 0x10305106;
253     cpu->isar.id_aa64isar0 = 0x00011120;
254     cpu->isar.id_aa64mmfr0 = 0x00001124;
255     cpu->isar.dbgdidr = 0x3516d000;
256     cpu->isar.dbgdevid = 0x01110f13;
257     cpu->isar.dbgdevid1 = 0x2;
258     cpu->isar.reset_pmcr_el0 = 0x41023000;
259     cpu->clidr = 0x0a200023;
260     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
261     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
262     cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
263     cpu->dcz_blocksize = 4; /* 64 bytes */
264     cpu->gic_num_lrs = 4;
265     cpu->gic_vpribits = 5;
266     cpu->gic_vprebits = 5;
267     cpu->gic_pribits = 5;
268     define_cortex_a72_a57_a53_cp_reginfo(cpu);
269 }
270 
271 static void aarch64_a76_initfn(Object *obj)
272 {
273     ARMCPU *cpu = ARM_CPU(obj);
274 
275     cpu->dtb_compatible = "arm,cortex-a76";
276     set_feature(&cpu->env, ARM_FEATURE_V8);
277     set_feature(&cpu->env, ARM_FEATURE_NEON);
278     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
279     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
280     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
281     set_feature(&cpu->env, ARM_FEATURE_EL2);
282     set_feature(&cpu->env, ARM_FEATURE_EL3);
283     set_feature(&cpu->env, ARM_FEATURE_PMU);
284 
285     /* Ordered by B2.4 AArch64 registers by functional group */
286     cpu->clidr = 0x82000023;
287     cpu->ctr = 0x8444C004;
288     cpu->dcz_blocksize = 4;
289     cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
290     cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
291     cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
292     cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
293     cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
294     cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
295     cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
296     cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
297     cpu->id_afr0       = 0x00000000;
298     cpu->isar.id_dfr0  = 0x04010088;
299     cpu->isar.id_isar0 = 0x02101110;
300     cpu->isar.id_isar1 = 0x13112111;
301     cpu->isar.id_isar2 = 0x21232042;
302     cpu->isar.id_isar3 = 0x01112131;
303     cpu->isar.id_isar4 = 0x00010142;
304     cpu->isar.id_isar5 = 0x01011121;
305     cpu->isar.id_isar6 = 0x00000010;
306     cpu->isar.id_mmfr0 = 0x10201105;
307     cpu->isar.id_mmfr1 = 0x40000000;
308     cpu->isar.id_mmfr2 = 0x01260000;
309     cpu->isar.id_mmfr3 = 0x02122211;
310     cpu->isar.id_mmfr4 = 0x00021110;
311     cpu->isar.id_pfr0  = 0x10010131;
312     cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
313     cpu->isar.id_pfr2  = 0x00000011;
314     cpu->midr = 0x414fd0b1;          /* r4p1 */
315     cpu->revidr = 0;
316 
317     /* From B2.18 CCSIDR_EL1 */
318     cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
319     cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
320     cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
321 
322     /* From B2.93 SCTLR_EL3 */
323     cpu->reset_sctlr = 0x30c50838;
324 
325     /* From B4.23 ICH_VTR_EL2 */
326     cpu->gic_num_lrs = 4;
327     cpu->gic_vpribits = 5;
328     cpu->gic_vprebits = 5;
329     cpu->gic_pribits = 5;
330 
331     /* From B5.1 AdvSIMD AArch64 register summary */
332     cpu->isar.mvfr0 = 0x10110222;
333     cpu->isar.mvfr1 = 0x13211111;
334     cpu->isar.mvfr2 = 0x00000043;
335 
336     /* From D5.1 AArch64 PMU register summary */
337     cpu->isar.reset_pmcr_el0 = 0x410b3000;
338 }
339 
340 static void aarch64_a64fx_initfn(Object *obj)
341 {
342     ARMCPU *cpu = ARM_CPU(obj);
343 
344     cpu->dtb_compatible = "arm,a64fx";
345     set_feature(&cpu->env, ARM_FEATURE_V8);
346     set_feature(&cpu->env, ARM_FEATURE_NEON);
347     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
348     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
349     set_feature(&cpu->env, ARM_FEATURE_EL2);
350     set_feature(&cpu->env, ARM_FEATURE_EL3);
351     set_feature(&cpu->env, ARM_FEATURE_PMU);
352     cpu->midr = 0x461f0010;
353     cpu->revidr = 0x00000000;
354     cpu->ctr = 0x86668006;
355     cpu->reset_sctlr = 0x30000180;
356     cpu->isar.id_aa64pfr0 =   0x0000000101111111; /* No RAS Extensions */
357     cpu->isar.id_aa64pfr1 = 0x0000000000000000;
358     cpu->isar.id_aa64dfr0 = 0x0000000010305408;
359     cpu->isar.id_aa64dfr1 = 0x0000000000000000;
360     cpu->id_aa64afr0 = 0x0000000000000000;
361     cpu->id_aa64afr1 = 0x0000000000000000;
362     cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
363     cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
364     cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
365     cpu->isar.id_aa64isar0 = 0x0000000010211120;
366     cpu->isar.id_aa64isar1 = 0x0000000000010001;
367     cpu->isar.id_aa64zfr0 = 0x0000000000000000;
368     cpu->clidr = 0x0000000080000023;
369     cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
370     cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
371     cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
372     cpu->dcz_blocksize = 6; /* 256 bytes */
373     cpu->gic_num_lrs = 4;
374     cpu->gic_vpribits = 5;
375     cpu->gic_vprebits = 5;
376     cpu->gic_pribits = 5;
377 
378     /* The A64FX supports only 128, 256 and 512 bit vector lengths */
379     aarch64_add_sve_properties(obj);
380     cpu->sve_vq.supported = (1 << 0)  /* 128bit */
381                           | (1 << 1)  /* 256bit */
382                           | (1 << 3); /* 512bit */
383 
384     cpu->isar.reset_pmcr_el0 = 0x46014040;
385 
386     /* TODO:  Add A64FX specific HPC extension registers */
387 }
388 
389 static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
390     { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
391       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
392       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
393     { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
394       .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
395       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
396     { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
397       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
398       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
399     { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64,
400       .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
401       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
402     { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
403       .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
404       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
405     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
406       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
407       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
408     { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
409       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
410       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
411     { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
412       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
413       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
414     /*
415      * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
416      * (and in particular its system registers).
417      */
418     { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
419       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
420       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
421     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
422       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
423       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
424     { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
425       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
426       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
427     { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64,
428       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3,
429       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
430     { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64,
431       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2,
432       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
433     { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64,
434       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
435       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
436     { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
437       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
438       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
439     { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
440       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
441       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
442     { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
443       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
444       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
445     { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
446       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
447       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
448 };
449 
450 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
451 {
452     define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo);
453 }
454 
455 static void aarch64_neoverse_n1_initfn(Object *obj)
456 {
457     ARMCPU *cpu = ARM_CPU(obj);
458 
459     cpu->dtb_compatible = "arm,neoverse-n1";
460     set_feature(&cpu->env, ARM_FEATURE_V8);
461     set_feature(&cpu->env, ARM_FEATURE_NEON);
462     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
463     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
464     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
465     set_feature(&cpu->env, ARM_FEATURE_EL2);
466     set_feature(&cpu->env, ARM_FEATURE_EL3);
467     set_feature(&cpu->env, ARM_FEATURE_PMU);
468 
469     /* Ordered by B2.4 AArch64 registers by functional group */
470     cpu->clidr = 0x82000023;
471     cpu->ctr = 0x8444c004;
472     cpu->dcz_blocksize = 4;
473     cpu->isar.id_aa64dfr0  = 0x0000000110305408ull;
474     cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
475     cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
476     cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
477     cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
478     cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
479     cpu->isar.id_aa64pfr0  = 0x1100000010111112ull; /* GIC filled in later */
480     cpu->isar.id_aa64pfr1  = 0x0000000000000020ull;
481     cpu->id_afr0       = 0x00000000;
482     cpu->isar.id_dfr0  = 0x04010088;
483     cpu->isar.id_isar0 = 0x02101110;
484     cpu->isar.id_isar1 = 0x13112111;
485     cpu->isar.id_isar2 = 0x21232042;
486     cpu->isar.id_isar3 = 0x01112131;
487     cpu->isar.id_isar4 = 0x00010142;
488     cpu->isar.id_isar5 = 0x01011121;
489     cpu->isar.id_isar6 = 0x00000010;
490     cpu->isar.id_mmfr0 = 0x10201105;
491     cpu->isar.id_mmfr1 = 0x40000000;
492     cpu->isar.id_mmfr2 = 0x01260000;
493     cpu->isar.id_mmfr3 = 0x02122211;
494     cpu->isar.id_mmfr4 = 0x00021110;
495     cpu->isar.id_pfr0  = 0x10010131;
496     cpu->isar.id_pfr1  = 0x00010000; /* GIC filled in later */
497     cpu->isar.id_pfr2  = 0x00000011;
498     cpu->midr = 0x414fd0c1;          /* r4p1 */
499     cpu->revidr = 0;
500 
501     /* From B2.23 CCSIDR_EL1 */
502     cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
503     cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
504     cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
505 
506     /* From B2.98 SCTLR_EL3 */
507     cpu->reset_sctlr = 0x30c50838;
508 
509     /* From B4.23 ICH_VTR_EL2 */
510     cpu->gic_num_lrs = 4;
511     cpu->gic_vpribits = 5;
512     cpu->gic_vprebits = 5;
513     cpu->gic_pribits = 5;
514 
515     /* From B5.1 AdvSIMD AArch64 register summary */
516     cpu->isar.mvfr0 = 0x10110222;
517     cpu->isar.mvfr1 = 0x13211111;
518     cpu->isar.mvfr2 = 0x00000043;
519 
520     /* From D5.1 AArch64 PMU register summary */
521     cpu->isar.reset_pmcr_el0 = 0x410c3000;
522 
523     define_neoverse_n1_cp_reginfo(cpu);
524 }
525 
526 /*
527  * -cpu max: a CPU with as many features enabled as our emulation supports.
528  * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c;
529  * this only needs to handle 64 bits.
530  */
531 void aarch64_max_tcg_initfn(Object *obj)
532 {
533     ARMCPU *cpu = ARM_CPU(obj);
534     uint64_t t;
535     uint32_t u;
536 
537     /*
538      * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
539      * one and try to apply errata workarounds or use impdef features we
540      * don't provide.
541      * An IMPLEMENTER field of 0 means "reserved for software use";
542      * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
543      * to see which features are present";
544      * the VARIANT, PARTNUM and REVISION fields are all implementation
545      * defined and we choose to define PARTNUM just in case guest
546      * code needs to distinguish this QEMU CPU from other software
547      * implementations, though this shouldn't be needed.
548      */
549     t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
550     t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
551     t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
552     t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
553     t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
554     cpu->midr = t;
555 
556     /*
557      * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
558      * are zero.
559      */
560     u = cpu->clidr;
561     u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
562     u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
563     cpu->clidr = u;
564 
565     t = cpu->isar.id_aa64isar0;
566     t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
567     t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
568     t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
569     t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
570     t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
571     t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
572     t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
573     t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);      /* FEAT_SM3 */
574     t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);      /* FEAT_SM4 */
575     t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);       /* FEAT_DotProd */
576     t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);      /* FEAT_FHM */
577     t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2);       /* FEAT_FlagM2 */
578     t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2);      /* FEAT_TLBIRANGE */
579     t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);     /* FEAT_RNG */
580     cpu->isar.id_aa64isar0 = t;
581 
582     t = cpu->isar.id_aa64isar1;
583     t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);      /* FEAT_DPB2 */
584     t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);    /* FEAT_JSCVT */
585     t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);     /* FEAT_FCMA */
586     t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2);    /* FEAT_LRCPC2 */
587     t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);  /* FEAT_FRINTTS */
588     t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);       /* FEAT_SB */
589     t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);  /* FEAT_SPECRES */
590     t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);     /* FEAT_BF16 */
591     t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1);      /* FEAT_DGH */
592     t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);     /* FEAT_I8MM */
593     cpu->isar.id_aa64isar1 = t;
594 
595     t = cpu->isar.id_aa64pfr0;
596     t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);        /* FEAT_FP16 */
597     t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);   /* FEAT_FP16 */
598     t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2);       /* FEAT_RASv1p1 + FEAT_DoubleFault */
599     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
600     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
601     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
602     t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
603     t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1);      /* FEAT_CSV3 */
604     cpu->isar.id_aa64pfr0 = t;
605 
606     t = cpu->isar.id_aa64pfr1;
607     t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);        /* FEAT_BTI */
608     t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);      /* FEAT_SSBS2 */
609     /*
610      * Begin with full support for MTE. This will be downgraded to MTE=0
611      * during realize if the board provides no tag memory, much like
612      * we do for EL2 with the virtualization=on property.
613      */
614     t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
615     t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0);  /* FEAT_RASv1p1 + FEAT_DoubleFault */
616     t = FIELD_DP64(t, ID_AA64PFR1, SME, 1);       /* FEAT_SME */
617     t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
618     cpu->isar.id_aa64pfr1 = t;
619 
620     t = cpu->isar.id_aa64mmfr0;
621     t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
622     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1);   /* 16k pages supported */
623     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
624     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
625     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2);  /*  4k stage2 supported */
626     t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1);       /* FEAT_FGT */
627     cpu->isar.id_aa64mmfr0 = t;
628 
629     t = cpu->isar.id_aa64mmfr1;
630     t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2);   /* FEAT_HAFDBS */
631     t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
632     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
633     t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
634     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
635     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
636     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
637     t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1);      /* FEAT_ETS */
638     t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1);      /* FEAT_HCX */
639     cpu->isar.id_aa64mmfr1 = t;
640 
641     t = cpu->isar.id_aa64mmfr2;
642     t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1);      /* FEAT_TTCNP */
643     t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);      /* FEAT_UAO */
644     t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1);     /* FEAT_IESB */
645     t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1);  /* FEAT_LVA */
646     t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1);       /* FEAT_TTST */
647     t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1);       /* FEAT_LSE2 */
648     t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1);      /* FEAT_IDST */
649     t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1);      /* FEAT_S2FWB */
650     t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
651     t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
652     t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2);      /* FEAT_EVT */
653     t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1);     /* FEAT_E0PD */
654     cpu->isar.id_aa64mmfr2 = t;
655 
656     t = cpu->isar.id_aa64zfr0;
657     t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
658     t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
659     t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);   /* FEAT_SVE_BitPerm */
660     t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);  /* FEAT_BF16 */
661     t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);      /* FEAT_SVE_SHA3 */
662     t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);       /* FEAT_SVE_SM4 */
663     t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);      /* FEAT_I8MM */
664     t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);     /* FEAT_F32MM */
665     t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);     /* FEAT_F64MM */
666     cpu->isar.id_aa64zfr0 = t;
667 
668     t = cpu->isar.id_aa64dfr0;
669     t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9);  /* FEAT_Debugv8p4 */
670     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6);    /* FEAT_PMUv3p5 */
671     cpu->isar.id_aa64dfr0 = t;
672 
673     t = cpu->isar.id_aa64smfr0;
674     t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1);   /* FEAT_SME */
675     t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1);   /* FEAT_SME */
676     t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1);   /* FEAT_SME */
677     t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf);  /* FEAT_SME */
678     t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1);   /* FEAT_SME_F64F64 */
679     t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
680     t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1);     /* FEAT_SME_FA64 */
681     cpu->isar.id_aa64smfr0 = t;
682 
683     /* Replicate the same data to the 32-bit id registers.  */
684     aa32_max_features(cpu);
685 
686 #ifdef CONFIG_USER_ONLY
687     /*
688      * For usermode -cpu max we can use a larger and more efficient DCZ
689      * blocksize since we don't have to follow what the hardware does.
690      */
691     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
692     cpu->dcz_blocksize = 7; /*  512 bytes */
693 #endif
694 
695     cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
696     cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
697 
698     aarch64_add_pauth_properties(obj);
699     aarch64_add_sve_properties(obj);
700     aarch64_add_sme_properties(obj);
701     object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
702                         cpu_max_set_sve_max_vq, NULL, NULL);
703     qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
704 }
705 
706 static const ARMCPUInfo aarch64_cpus[] = {
707     { .name = "cortex-a35",         .initfn = aarch64_a35_initfn },
708     { .name = "cortex-a55",         .initfn = aarch64_a55_initfn },
709     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
710     { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
711     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
712     { .name = "neoverse-n1",        .initfn = aarch64_neoverse_n1_initfn },
713 };
714 
715 static void aarch64_cpu_register_types(void)
716 {
717     size_t i;
718 
719     for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
720         aarch64_cpu_register(&aarch64_cpus[i]);
721     }
722 }
723 
724 type_init(aarch64_cpu_register_types)
725