1 /* 2 * QEMU AArch64 TCG CPUs 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu/module.h" 25 #include "qapi/visitor.h" 26 #include "hw/qdev-properties.h" 27 #include "qemu/units.h" 28 #include "internals.h" 29 #include "cpu-features.h" 30 #include "cpregs.h" 31 32 static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize, 33 unsigned cachesize) 34 { 35 unsigned lg_linesize = ctz32(linesize); 36 unsigned sets; 37 38 /* 39 * The 64-bit CCSIDR_EL1 format is: 40 * [55:32] number of sets - 1 41 * [23:3] associativity - 1 42 * [2:0] log2(linesize) - 4 43 * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc 44 */ 45 assert(assoc != 0); 46 assert(is_power_of_2(linesize)); 47 assert(lg_linesize >= 4 && lg_linesize <= 7 + 4); 48 49 /* sets * associativity * linesize == cachesize. */ 50 sets = cachesize / (assoc * linesize); 51 assert(cachesize % (assoc * linesize) == 0); 52 53 return ((uint64_t)(sets - 1) << 32) 54 | ((assoc - 1) << 3) 55 | (lg_linesize - 4); 56 } 57 58 static void aarch64_a35_initfn(Object *obj) 59 { 60 ARMCPU *cpu = ARM_CPU(obj); 61 62 cpu->dtb_compatible = "arm,cortex-a35"; 63 set_feature(&cpu->env, ARM_FEATURE_V8); 64 set_feature(&cpu->env, ARM_FEATURE_NEON); 65 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 66 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 67 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 68 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 69 set_feature(&cpu->env, ARM_FEATURE_EL2); 70 set_feature(&cpu->env, ARM_FEATURE_EL3); 71 set_feature(&cpu->env, ARM_FEATURE_PMU); 72 73 /* From B2.2 AArch64 identification registers. */ 74 cpu->midr = 0x411fd040; 75 cpu->revidr = 0; 76 cpu->ctr = 0x84448004; 77 cpu->isar.id_pfr0 = 0x00000131; 78 cpu->isar.id_pfr1 = 0x00011011; 79 cpu->isar.id_dfr0 = 0x03010066; 80 cpu->id_afr0 = 0; 81 cpu->isar.id_mmfr0 = 0x10201105; 82 cpu->isar.id_mmfr1 = 0x40000000; 83 cpu->isar.id_mmfr2 = 0x01260000; 84 cpu->isar.id_mmfr3 = 0x02102211; 85 cpu->isar.id_isar0 = 0x02101110; 86 cpu->isar.id_isar1 = 0x13112111; 87 cpu->isar.id_isar2 = 0x21232042; 88 cpu->isar.id_isar3 = 0x01112131; 89 cpu->isar.id_isar4 = 0x00011142; 90 cpu->isar.id_isar5 = 0x00011121; 91 cpu->isar.id_aa64pfr0 = 0x00002222; 92 cpu->isar.id_aa64pfr1 = 0; 93 cpu->isar.id_aa64dfr0 = 0x10305106; 94 cpu->isar.id_aa64dfr1 = 0; 95 cpu->isar.id_aa64isar0 = 0x00011120; 96 cpu->isar.id_aa64isar1 = 0; 97 cpu->isar.id_aa64mmfr0 = 0x00101122; 98 cpu->isar.id_aa64mmfr1 = 0; 99 cpu->clidr = 0x0a200023; 100 cpu->dcz_blocksize = 4; 101 102 /* From B2.4 AArch64 Virtual Memory control registers */ 103 cpu->reset_sctlr = 0x00c50838; 104 105 /* From B2.10 AArch64 performance monitor registers */ 106 cpu->isar.reset_pmcr_el0 = 0x410a3000; 107 108 /* From B2.29 Cache ID registers */ 109 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 110 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 111 cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */ 112 113 /* From B3.5 VGIC Type register */ 114 cpu->gic_num_lrs = 4; 115 cpu->gic_vpribits = 5; 116 cpu->gic_vprebits = 5; 117 cpu->gic_pribits = 5; 118 119 /* From C6.4 Debug ID Register */ 120 cpu->isar.dbgdidr = 0x3516d000; 121 /* From C6.5 Debug Device ID Register */ 122 cpu->isar.dbgdevid = 0x00110f13; 123 /* From C6.6 Debug Device ID Register 1 */ 124 cpu->isar.dbgdevid1 = 0x2; 125 126 /* From Cortex-A35 SIMD and Floating-point Support r1p0 */ 127 /* From 3.2 AArch32 register summary */ 128 cpu->reset_fpsid = 0x41034043; 129 130 /* From 2.2 AArch64 register summary */ 131 cpu->isar.mvfr0 = 0x10110222; 132 cpu->isar.mvfr1 = 0x12111111; 133 cpu->isar.mvfr2 = 0x00000043; 134 135 /* These values are the same with A53/A57/A72. */ 136 define_cortex_a72_a57_a53_cp_reginfo(cpu); 137 } 138 139 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, 140 void *opaque, Error **errp) 141 { 142 ARMCPU *cpu = ARM_CPU(obj); 143 uint32_t value; 144 145 /* All vector lengths are disabled when SVE is off. */ 146 if (!cpu_isar_feature(aa64_sve, cpu)) { 147 value = 0; 148 } else { 149 value = cpu->sve_max_vq; 150 } 151 visit_type_uint32(v, name, &value, errp); 152 } 153 154 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, 155 void *opaque, Error **errp) 156 { 157 ARMCPU *cpu = ARM_CPU(obj); 158 uint32_t max_vq; 159 160 if (!visit_type_uint32(v, name, &max_vq, errp)) { 161 return; 162 } 163 164 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { 165 error_setg(errp, "unsupported SVE vector length"); 166 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", 167 ARM_MAX_VQ); 168 return; 169 } 170 171 cpu->sve_max_vq = max_vq; 172 } 173 174 static bool cpu_arm_get_rme(Object *obj, Error **errp) 175 { 176 ARMCPU *cpu = ARM_CPU(obj); 177 return cpu_isar_feature(aa64_rme, cpu); 178 } 179 180 static void cpu_arm_set_rme(Object *obj, bool value, Error **errp) 181 { 182 ARMCPU *cpu = ARM_CPU(obj); 183 uint64_t t; 184 185 t = cpu->isar.id_aa64pfr0; 186 t = FIELD_DP64(t, ID_AA64PFR0, RME, value); 187 cpu->isar.id_aa64pfr0 = t; 188 } 189 190 static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, 191 void *opaque, Error **errp) 192 { 193 ARMCPU *cpu = ARM_CPU(obj); 194 uint32_t value; 195 196 if (!visit_type_uint32(v, name, &value, errp)) { 197 return; 198 } 199 200 /* Encode the value for the GPCCR_EL3 field. */ 201 switch (value) { 202 case 30: 203 case 34: 204 case 36: 205 case 39: 206 cpu->reset_l0gptsz = value - 30; 207 break; 208 default: 209 error_setg(errp, "invalid value for l0gptsz"); 210 error_append_hint(errp, "valid values are 30, 34, 36, 39\n"); 211 break; 212 } 213 } 214 215 static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name, 216 void *opaque, Error **errp) 217 { 218 ARMCPU *cpu = ARM_CPU(obj); 219 uint32_t value = cpu->reset_l0gptsz + 30; 220 221 visit_type_uint32(v, name, &value, errp); 222 } 223 224 static Property arm_cpu_lpa2_property = 225 DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); 226 227 static void aarch64_a55_initfn(Object *obj) 228 { 229 ARMCPU *cpu = ARM_CPU(obj); 230 231 cpu->dtb_compatible = "arm,cortex-a55"; 232 set_feature(&cpu->env, ARM_FEATURE_V8); 233 set_feature(&cpu->env, ARM_FEATURE_NEON); 234 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 235 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 236 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 237 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 238 set_feature(&cpu->env, ARM_FEATURE_EL2); 239 set_feature(&cpu->env, ARM_FEATURE_EL3); 240 set_feature(&cpu->env, ARM_FEATURE_PMU); 241 242 /* Ordered by B2.4 AArch64 registers by functional group */ 243 cpu->clidr = 0x82000023; 244 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 245 cpu->dcz_blocksize = 4; /* 64 bytes */ 246 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; 247 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 248 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 249 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; 250 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 251 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 252 cpu->isar.id_aa64pfr0 = 0x0000000010112222ull; 253 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; 254 cpu->id_afr0 = 0x00000000; 255 cpu->isar.id_dfr0 = 0x04010088; 256 cpu->isar.id_isar0 = 0x02101110; 257 cpu->isar.id_isar1 = 0x13112111; 258 cpu->isar.id_isar2 = 0x21232042; 259 cpu->isar.id_isar3 = 0x01112131; 260 cpu->isar.id_isar4 = 0x00011142; 261 cpu->isar.id_isar5 = 0x01011121; 262 cpu->isar.id_isar6 = 0x00000010; 263 cpu->isar.id_mmfr0 = 0x10201105; 264 cpu->isar.id_mmfr1 = 0x40000000; 265 cpu->isar.id_mmfr2 = 0x01260000; 266 cpu->isar.id_mmfr3 = 0x02122211; 267 cpu->isar.id_mmfr4 = 0x00021110; 268 cpu->isar.id_pfr0 = 0x10010131; 269 cpu->isar.id_pfr1 = 0x00011011; 270 cpu->isar.id_pfr2 = 0x00000011; 271 cpu->midr = 0x412FD050; /* r2p0 */ 272 cpu->revidr = 0; 273 274 /* From B2.23 CCSIDR_EL1 */ 275 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 276 cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */ 277 cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */ 278 279 /* From B2.96 SCTLR_EL3 */ 280 cpu->reset_sctlr = 0x30c50838; 281 282 /* From B4.45 ICH_VTR_EL2 */ 283 cpu->gic_num_lrs = 4; 284 cpu->gic_vpribits = 5; 285 cpu->gic_vprebits = 5; 286 cpu->gic_pribits = 5; 287 288 cpu->isar.mvfr0 = 0x10110222; 289 cpu->isar.mvfr1 = 0x13211111; 290 cpu->isar.mvfr2 = 0x00000043; 291 292 /* From D5.4 AArch64 PMU register summary */ 293 cpu->isar.reset_pmcr_el0 = 0x410b3000; 294 } 295 296 static void aarch64_a72_initfn(Object *obj) 297 { 298 ARMCPU *cpu = ARM_CPU(obj); 299 300 cpu->dtb_compatible = "arm,cortex-a72"; 301 set_feature(&cpu->env, ARM_FEATURE_V8); 302 set_feature(&cpu->env, ARM_FEATURE_NEON); 303 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 304 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 305 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 306 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 307 set_feature(&cpu->env, ARM_FEATURE_EL2); 308 set_feature(&cpu->env, ARM_FEATURE_EL3); 309 set_feature(&cpu->env, ARM_FEATURE_PMU); 310 cpu->midr = 0x410fd083; 311 cpu->revidr = 0x00000000; 312 cpu->reset_fpsid = 0x41034080; 313 cpu->isar.mvfr0 = 0x10110222; 314 cpu->isar.mvfr1 = 0x12111111; 315 cpu->isar.mvfr2 = 0x00000043; 316 cpu->ctr = 0x8444c004; 317 cpu->reset_sctlr = 0x00c50838; 318 cpu->isar.id_pfr0 = 0x00000131; 319 cpu->isar.id_pfr1 = 0x00011011; 320 cpu->isar.id_dfr0 = 0x03010066; 321 cpu->id_afr0 = 0x00000000; 322 cpu->isar.id_mmfr0 = 0x10201105; 323 cpu->isar.id_mmfr1 = 0x40000000; 324 cpu->isar.id_mmfr2 = 0x01260000; 325 cpu->isar.id_mmfr3 = 0x02102211; 326 cpu->isar.id_isar0 = 0x02101110; 327 cpu->isar.id_isar1 = 0x13112111; 328 cpu->isar.id_isar2 = 0x21232042; 329 cpu->isar.id_isar3 = 0x01112131; 330 cpu->isar.id_isar4 = 0x00011142; 331 cpu->isar.id_isar5 = 0x00011121; 332 cpu->isar.id_aa64pfr0 = 0x00002222; 333 cpu->isar.id_aa64dfr0 = 0x10305106; 334 cpu->isar.id_aa64isar0 = 0x00011120; 335 cpu->isar.id_aa64mmfr0 = 0x00001124; 336 cpu->isar.dbgdidr = 0x3516d000; 337 cpu->isar.dbgdevid = 0x01110f13; 338 cpu->isar.dbgdevid1 = 0x2; 339 cpu->isar.reset_pmcr_el0 = 0x41023000; 340 cpu->clidr = 0x0a200023; 341 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 342 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 343 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 344 cpu->dcz_blocksize = 4; /* 64 bytes */ 345 cpu->gic_num_lrs = 4; 346 cpu->gic_vpribits = 5; 347 cpu->gic_vprebits = 5; 348 cpu->gic_pribits = 5; 349 define_cortex_a72_a57_a53_cp_reginfo(cpu); 350 } 351 352 static void aarch64_a76_initfn(Object *obj) 353 { 354 ARMCPU *cpu = ARM_CPU(obj); 355 356 cpu->dtb_compatible = "arm,cortex-a76"; 357 set_feature(&cpu->env, ARM_FEATURE_V8); 358 set_feature(&cpu->env, ARM_FEATURE_NEON); 359 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 360 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 361 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 362 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 363 set_feature(&cpu->env, ARM_FEATURE_EL2); 364 set_feature(&cpu->env, ARM_FEATURE_EL3); 365 set_feature(&cpu->env, ARM_FEATURE_PMU); 366 367 /* Ordered by B2.4 AArch64 registers by functional group */ 368 cpu->clidr = 0x82000023; 369 cpu->ctr = 0x8444C004; 370 cpu->dcz_blocksize = 4; 371 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; 372 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 373 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 374 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; 375 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 376 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 377 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 378 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; 379 cpu->id_afr0 = 0x00000000; 380 cpu->isar.id_dfr0 = 0x04010088; 381 cpu->isar.id_isar0 = 0x02101110; 382 cpu->isar.id_isar1 = 0x13112111; 383 cpu->isar.id_isar2 = 0x21232042; 384 cpu->isar.id_isar3 = 0x01112131; 385 cpu->isar.id_isar4 = 0x00010142; 386 cpu->isar.id_isar5 = 0x01011121; 387 cpu->isar.id_isar6 = 0x00000010; 388 cpu->isar.id_mmfr0 = 0x10201105; 389 cpu->isar.id_mmfr1 = 0x40000000; 390 cpu->isar.id_mmfr2 = 0x01260000; 391 cpu->isar.id_mmfr3 = 0x02122211; 392 cpu->isar.id_mmfr4 = 0x00021110; 393 cpu->isar.id_pfr0 = 0x10010131; 394 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 395 cpu->isar.id_pfr2 = 0x00000011; 396 cpu->midr = 0x414fd0b1; /* r4p1 */ 397 cpu->revidr = 0; 398 399 /* From B2.18 CCSIDR_EL1 */ 400 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 401 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 402 cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ 403 404 /* From B2.93 SCTLR_EL3 */ 405 cpu->reset_sctlr = 0x30c50838; 406 407 /* From B4.23 ICH_VTR_EL2 */ 408 cpu->gic_num_lrs = 4; 409 cpu->gic_vpribits = 5; 410 cpu->gic_vprebits = 5; 411 cpu->gic_pribits = 5; 412 413 /* From B5.1 AdvSIMD AArch64 register summary */ 414 cpu->isar.mvfr0 = 0x10110222; 415 cpu->isar.mvfr1 = 0x13211111; 416 cpu->isar.mvfr2 = 0x00000043; 417 418 /* From D5.1 AArch64 PMU register summary */ 419 cpu->isar.reset_pmcr_el0 = 0x410b3000; 420 } 421 422 static void aarch64_a64fx_initfn(Object *obj) 423 { 424 ARMCPU *cpu = ARM_CPU(obj); 425 426 cpu->dtb_compatible = "arm,a64fx"; 427 set_feature(&cpu->env, ARM_FEATURE_V8); 428 set_feature(&cpu->env, ARM_FEATURE_NEON); 429 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 430 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 431 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 432 set_feature(&cpu->env, ARM_FEATURE_EL2); 433 set_feature(&cpu->env, ARM_FEATURE_EL3); 434 set_feature(&cpu->env, ARM_FEATURE_PMU); 435 cpu->midr = 0x461f0010; 436 cpu->revidr = 0x00000000; 437 cpu->ctr = 0x86668006; 438 cpu->reset_sctlr = 0x30000180; 439 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ 440 cpu->isar.id_aa64pfr1 = 0x0000000000000000; 441 cpu->isar.id_aa64dfr0 = 0x0000000010305408; 442 cpu->isar.id_aa64dfr1 = 0x0000000000000000; 443 cpu->id_aa64afr0 = 0x0000000000000000; 444 cpu->id_aa64afr1 = 0x0000000000000000; 445 cpu->isar.id_aa64mmfr0 = 0x0000000000001122; 446 cpu->isar.id_aa64mmfr1 = 0x0000000011212100; 447 cpu->isar.id_aa64mmfr2 = 0x0000000000001011; 448 cpu->isar.id_aa64isar0 = 0x0000000010211120; 449 cpu->isar.id_aa64isar1 = 0x0000000000010001; 450 cpu->isar.id_aa64zfr0 = 0x0000000000000000; 451 cpu->clidr = 0x0000000080000023; 452 cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ 453 cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ 454 cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ 455 cpu->dcz_blocksize = 6; /* 256 bytes */ 456 cpu->gic_num_lrs = 4; 457 cpu->gic_vpribits = 5; 458 cpu->gic_vprebits = 5; 459 cpu->gic_pribits = 5; 460 461 /* The A64FX supports only 128, 256 and 512 bit vector lengths */ 462 aarch64_add_sve_properties(obj); 463 cpu->sve_vq.supported = (1 << 0) /* 128bit */ 464 | (1 << 1) /* 256bit */ 465 | (1 << 3); /* 512bit */ 466 467 cpu->isar.reset_pmcr_el0 = 0x46014040; 468 469 /* TODO: Add A64FX specific HPC extension registers */ 470 } 471 472 static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r, 473 bool read) 474 { 475 if (!read) { 476 int el = arm_current_el(env); 477 478 /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */ 479 if (el < 2 && arm_is_el2_enabled(env)) { 480 return CP_ACCESS_TRAP_EL2; 481 } 482 /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */ 483 if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { 484 return CP_ACCESS_TRAP_EL3; 485 } 486 } 487 return CP_ACCESS_OK; 488 } 489 490 static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { 491 { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, 492 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, 493 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 494 /* Traps and enables are the same as for TCR_EL1. */ 495 .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, }, 496 { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, 497 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, 498 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 499 { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64, 500 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0, 501 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 502 { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64, 503 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0, 504 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 505 { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64, 506 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1, 507 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 508 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 509 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, 510 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 511 .accessfn = access_actlr_w }, 512 { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, 513 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, 514 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 515 .accessfn = access_actlr_w }, 516 { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, 517 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, 518 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 519 .accessfn = access_actlr_w }, 520 /* 521 * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU 522 * (and in particular its system registers). 523 */ 524 { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64, 525 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, 526 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, 527 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 528 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, 529 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010, 530 .accessfn = access_actlr_w }, 531 { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, 532 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, 533 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 534 { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64, 535 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3, 536 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 537 { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64, 538 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2, 539 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 540 { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64, 541 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0, 542 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 543 { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, 544 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, 545 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 546 .accessfn = access_actlr_w }, 547 { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64, 548 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2, 549 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 550 .accessfn = access_actlr_w }, 551 { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64, 552 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1, 553 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 554 .accessfn = access_actlr_w }, 555 { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64, 556 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, 557 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 558 .accessfn = access_actlr_w }, 559 }; 560 561 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) 562 { 563 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); 564 } 565 566 static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { 567 { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, 568 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, 569 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 570 .accessfn = access_actlr_w }, 571 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, 572 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, 573 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 574 { .name = "CPUPPMCR2_EL3", .state = ARM_CP_STATE_AA64, 575 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 1, 576 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 577 { .name = "CPUPPMCR3_EL3", .state = ARM_CP_STATE_AA64, 578 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6, 579 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 580 }; 581 582 static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) 583 { 584 /* 585 * The Neoverse V1 has all of the Neoverse N1's IMPDEF 586 * registers and a few more of its own. 587 */ 588 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); 589 define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo); 590 } 591 592 static void aarch64_neoverse_n1_initfn(Object *obj) 593 { 594 ARMCPU *cpu = ARM_CPU(obj); 595 596 cpu->dtb_compatible = "arm,neoverse-n1"; 597 set_feature(&cpu->env, ARM_FEATURE_V8); 598 set_feature(&cpu->env, ARM_FEATURE_NEON); 599 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 600 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 601 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 602 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 603 set_feature(&cpu->env, ARM_FEATURE_EL2); 604 set_feature(&cpu->env, ARM_FEATURE_EL3); 605 set_feature(&cpu->env, ARM_FEATURE_PMU); 606 607 /* Ordered by B2.4 AArch64 registers by functional group */ 608 cpu->clidr = 0x82000023; 609 cpu->ctr = 0x8444c004; 610 cpu->dcz_blocksize = 4; 611 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; 612 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 613 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 614 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; 615 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 616 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 617 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 618 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; 619 cpu->id_afr0 = 0x00000000; 620 cpu->isar.id_dfr0 = 0x04010088; 621 cpu->isar.id_isar0 = 0x02101110; 622 cpu->isar.id_isar1 = 0x13112111; 623 cpu->isar.id_isar2 = 0x21232042; 624 cpu->isar.id_isar3 = 0x01112131; 625 cpu->isar.id_isar4 = 0x00010142; 626 cpu->isar.id_isar5 = 0x01011121; 627 cpu->isar.id_isar6 = 0x00000010; 628 cpu->isar.id_mmfr0 = 0x10201105; 629 cpu->isar.id_mmfr1 = 0x40000000; 630 cpu->isar.id_mmfr2 = 0x01260000; 631 cpu->isar.id_mmfr3 = 0x02122211; 632 cpu->isar.id_mmfr4 = 0x00021110; 633 cpu->isar.id_pfr0 = 0x10010131; 634 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 635 cpu->isar.id_pfr2 = 0x00000011; 636 cpu->midr = 0x414fd0c1; /* r4p1 */ 637 cpu->revidr = 0; 638 639 /* From B2.23 CCSIDR_EL1 */ 640 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 641 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 642 cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ 643 644 /* From B2.98 SCTLR_EL3 */ 645 cpu->reset_sctlr = 0x30c50838; 646 647 /* From B4.23 ICH_VTR_EL2 */ 648 cpu->gic_num_lrs = 4; 649 cpu->gic_vpribits = 5; 650 cpu->gic_vprebits = 5; 651 cpu->gic_pribits = 5; 652 653 /* From B5.1 AdvSIMD AArch64 register summary */ 654 cpu->isar.mvfr0 = 0x10110222; 655 cpu->isar.mvfr1 = 0x13211111; 656 cpu->isar.mvfr2 = 0x00000043; 657 658 /* From D5.1 AArch64 PMU register summary */ 659 cpu->isar.reset_pmcr_el0 = 0x410c3000; 660 661 define_neoverse_n1_cp_reginfo(cpu); 662 } 663 664 static void aarch64_neoverse_v1_initfn(Object *obj) 665 { 666 ARMCPU *cpu = ARM_CPU(obj); 667 668 cpu->dtb_compatible = "arm,neoverse-v1"; 669 set_feature(&cpu->env, ARM_FEATURE_V8); 670 set_feature(&cpu->env, ARM_FEATURE_NEON); 671 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 672 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 673 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 674 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 675 set_feature(&cpu->env, ARM_FEATURE_EL2); 676 set_feature(&cpu->env, ARM_FEATURE_EL3); 677 set_feature(&cpu->env, ARM_FEATURE_PMU); 678 679 /* Ordered by 3.2.4 AArch64 registers by functional group */ 680 cpu->clidr = 0x82000023; 681 cpu->ctr = 0xb444c004; /* With DIC and IDC set */ 682 cpu->dcz_blocksize = 4; 683 cpu->id_aa64afr0 = 0x00000000; 684 cpu->id_aa64afr1 = 0x00000000; 685 cpu->isar.id_aa64dfr0 = 0x000001f210305519ull; 686 cpu->isar.id_aa64dfr1 = 0x00000000; 687 cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */ 688 cpu->isar.id_aa64isar1 = 0x0111000001211032ull; 689 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; 690 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 691 cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull; 692 cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */ 693 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; 694 cpu->id_afr0 = 0x00000000; 695 cpu->isar.id_dfr0 = 0x15011099; 696 cpu->isar.id_isar0 = 0x02101110; 697 cpu->isar.id_isar1 = 0x13112111; 698 cpu->isar.id_isar2 = 0x21232042; 699 cpu->isar.id_isar3 = 0x01112131; 700 cpu->isar.id_isar4 = 0x00010142; 701 cpu->isar.id_isar5 = 0x11011121; 702 cpu->isar.id_isar6 = 0x01100111; 703 cpu->isar.id_mmfr0 = 0x10201105; 704 cpu->isar.id_mmfr1 = 0x40000000; 705 cpu->isar.id_mmfr2 = 0x01260000; 706 cpu->isar.id_mmfr3 = 0x02122211; 707 cpu->isar.id_mmfr4 = 0x01021110; 708 cpu->isar.id_pfr0 = 0x21110131; 709 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 710 cpu->isar.id_pfr2 = 0x00000011; 711 cpu->midr = 0x411FD402; /* r1p2 */ 712 cpu->revidr = 0; 713 714 /* 715 * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values, 716 * but also says it implements CCIDX, which means they should be 717 * 64-bit format. So we here use values which are based on the textual 718 * information in chapter 2 of the TRM: 719 * 720 * L1: 4-way set associative 64-byte line size, total size 64K. 721 * L2: 8-way set associative, 64 byte line size, either 512K or 1MB. 722 * L3: No L3 (this matches the CLIDR_EL1 value). 723 */ 724 cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ 725 cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ 726 cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */ 727 728 /* From 3.2.115 SCTLR_EL3 */ 729 cpu->reset_sctlr = 0x30c50838; 730 731 /* From 3.4.8 ICC_CTLR_EL3 and 3.4.23 ICH_VTR_EL2 */ 732 cpu->gic_num_lrs = 4; 733 cpu->gic_vpribits = 5; 734 cpu->gic_vprebits = 5; 735 cpu->gic_pribits = 5; 736 737 /* From 3.5.1 AdvSIMD AArch64 register summary */ 738 cpu->isar.mvfr0 = 0x10110222; 739 cpu->isar.mvfr1 = 0x13211111; 740 cpu->isar.mvfr2 = 0x00000043; 741 742 /* From 3.7.5 ID_AA64ZFR0_EL1 */ 743 cpu->isar.id_aa64zfr0 = 0x0000100000100000; 744 cpu->sve_vq.supported = (1 << 0) /* 128bit */ 745 | (1 << 1); /* 256bit */ 746 747 /* From 5.5.1 AArch64 PMU register summary */ 748 cpu->isar.reset_pmcr_el0 = 0x41213000; 749 750 define_neoverse_v1_cp_reginfo(cpu); 751 752 aarch64_add_pauth_properties(obj); 753 aarch64_add_sve_properties(obj); 754 } 755 756 static const ARMCPRegInfo cortex_a710_cp_reginfo[] = { 757 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 758 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, 759 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 760 .accessfn = access_actlr_w }, 761 { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, 762 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, 763 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 764 .accessfn = access_actlr_w }, 765 { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, 766 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, 767 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 768 .accessfn = access_actlr_w }, 769 { .name = "CPUACTLR4_EL1", .state = ARM_CP_STATE_AA64, 770 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 3, 771 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 772 .accessfn = access_actlr_w }, 773 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 774 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, 775 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 776 .accessfn = access_actlr_w }, 777 { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, 778 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, 779 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 780 .accessfn = access_actlr_w }, 781 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, 782 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 4, 783 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 784 { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, 785 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, 786 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 787 .accessfn = access_actlr_w }, 788 { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, 789 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, 790 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 791 { .name = "CPUACTLR5_EL1", .state = ARM_CP_STATE_AA64, 792 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 0, 793 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 794 .accessfn = access_actlr_w }, 795 { .name = "CPUACTLR6_EL1", .state = ARM_CP_STATE_AA64, 796 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 1, 797 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 798 .accessfn = access_actlr_w }, 799 { .name = "CPUACTLR7_EL1", .state = ARM_CP_STATE_AA64, 800 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 2, 801 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 802 .accessfn = access_actlr_w }, 803 { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, 804 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, 805 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 806 { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64, 807 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1, 808 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 809 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, 810 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, 811 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 812 { .name = "CPUPPMCR2_EL3", .state = ARM_CP_STATE_AA64, 813 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 1, 814 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 815 { .name = "CPUPPMCR4_EL3", .state = ARM_CP_STATE_AA64, 816 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 4, 817 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 818 { .name = "CPUPPMCR5_EL3", .state = ARM_CP_STATE_AA64, 819 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 5, 820 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 821 { .name = "CPUPPMCR6_EL3", .state = ARM_CP_STATE_AA64, 822 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6, 823 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 824 { .name = "CPUACTLR_EL3", .state = ARM_CP_STATE_AA64, 825 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 4, .opc2 = 0, 826 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 827 { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64, 828 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0, 829 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 830 { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64, 831 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0, 832 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 833 { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, 834 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, 835 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 836 { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64, 837 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2, 838 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 839 { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64, 840 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3, 841 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 842 { .name = "CPUPOR2_EL3", .state = ARM_CP_STATE_AA64, 843 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 4, 844 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 845 { .name = "CPUPMR2_EL3", .state = ARM_CP_STATE_AA64, 846 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 5, 847 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 848 { .name = "CPUPFR_EL3", .state = ARM_CP_STATE_AA64, 849 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 6, 850 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 851 /* 852 * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU 853 * (and in particular its system registers). 854 */ 855 { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64, 856 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, 857 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, 858 859 /* 860 * Stub RAMINDEX, as we don't actually implement caches, BTB, 861 * or anything else with cpu internal memory. 862 * "Read" zeros into the IDATA* and DDATA* output registers. 863 */ 864 { .name = "RAMINDEX_EL3", .state = ARM_CP_STATE_AA64, 865 .opc0 = 1, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0, 866 .access = PL3_W, .type = ARM_CP_CONST, .resetvalue = 0 }, 867 { .name = "IDATA0_EL3", .state = ARM_CP_STATE_AA64, 868 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0, 869 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 870 { .name = "IDATA1_EL3", .state = ARM_CP_STATE_AA64, 871 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 1, 872 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 873 { .name = "IDATA2_EL3", .state = ARM_CP_STATE_AA64, 874 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 2, 875 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 876 { .name = "DDATA0_EL3", .state = ARM_CP_STATE_AA64, 877 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 0, 878 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 879 { .name = "DDATA1_EL3", .state = ARM_CP_STATE_AA64, 880 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 1, 881 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 882 { .name = "DDATA2_EL3", .state = ARM_CP_STATE_AA64, 883 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 2, 884 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 885 }; 886 887 static void aarch64_a710_initfn(Object *obj) 888 { 889 ARMCPU *cpu = ARM_CPU(obj); 890 891 cpu->dtb_compatible = "arm,cortex-a710"; 892 set_feature(&cpu->env, ARM_FEATURE_V8); 893 set_feature(&cpu->env, ARM_FEATURE_NEON); 894 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 895 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 896 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 897 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 898 set_feature(&cpu->env, ARM_FEATURE_EL2); 899 set_feature(&cpu->env, ARM_FEATURE_EL3); 900 set_feature(&cpu->env, ARM_FEATURE_PMU); 901 902 /* Ordered by Section B.4: AArch64 registers */ 903 cpu->midr = 0x412FD471; /* r2p1 */ 904 cpu->revidr = 0; 905 cpu->isar.id_pfr0 = 0x21110131; 906 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 907 cpu->isar.id_dfr0 = 0x16011099; 908 cpu->id_afr0 = 0; 909 cpu->isar.id_mmfr0 = 0x10201105; 910 cpu->isar.id_mmfr1 = 0x40000000; 911 cpu->isar.id_mmfr2 = 0x01260000; 912 cpu->isar.id_mmfr3 = 0x02122211; 913 cpu->isar.id_isar0 = 0x02101110; 914 cpu->isar.id_isar1 = 0x13112111; 915 cpu->isar.id_isar2 = 0x21232042; 916 cpu->isar.id_isar3 = 0x01112131; 917 cpu->isar.id_isar4 = 0x00010142; 918 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */ 919 cpu->isar.id_mmfr4 = 0x21021110; 920 cpu->isar.id_isar6 = 0x01111111; 921 cpu->isar.mvfr0 = 0x10110222; 922 cpu->isar.mvfr1 = 0x13211111; 923 cpu->isar.mvfr2 = 0x00000043; 924 cpu->isar.id_pfr2 = 0x00000011; 925 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */ 926 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; 927 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */ 928 cpu->isar.id_aa64dfr0 = 0x000011f010305619ull; 929 cpu->isar.id_aa64dfr1 = 0; 930 cpu->id_aa64afr0 = 0; 931 cpu->id_aa64afr1 = 0; 932 cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */ 933 cpu->isar.id_aa64isar1 = 0x0010111101211052ull; 934 cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull; 935 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 936 cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull; 937 cpu->clidr = 0x0000001482000023ull; 938 cpu->gm_blocksize = 4; 939 cpu->ctr = 0x000000049444c004ull; 940 cpu->dcz_blocksize = 4; 941 /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_0006_003f */ 942 943 /* Section B.5.2: PMCR_EL0 */ 944 cpu->isar.reset_pmcr_el0 = 0xa000; /* with 20 counters */ 945 946 /* Section B.6.7: ICH_VTR_EL2 */ 947 cpu->gic_num_lrs = 4; 948 cpu->gic_vpribits = 5; 949 cpu->gic_vprebits = 5; 950 cpu->gic_pribits = 5; 951 952 /* Section 14: Scalable Vector Extensions support */ 953 cpu->sve_vq.supported = 1 << 0; /* 128bit */ 954 955 /* 956 * The cortex-a710 TRM does not list CCSIDR values. The layout of 957 * the caches are in text in Table 7-1, Table 8-1, and Table 9-1. 958 * 959 * L1: 4-way set associative 64-byte line size, total either 32K or 64K. 960 * L2: 8-way set associative 64 byte line size, total either 256K or 512K. 961 */ 962 cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ 963 cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ 964 cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ 965 966 /* FIXME: Not documented -- copied from neoverse-v1 */ 967 cpu->reset_sctlr = 0x30c50838; 968 969 define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); 970 971 aarch64_add_pauth_properties(obj); 972 aarch64_add_sve_properties(obj); 973 } 974 975 /* Extra IMPDEF regs in the N2 beyond those in the A710 */ 976 static const ARMCPRegInfo neoverse_n2_cp_reginfo[] = { 977 { .name = "CPURNDBR_EL3", .state = ARM_CP_STATE_AA64, 978 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 0, 979 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 980 { .name = "CPURNDPEID_EL3", .state = ARM_CP_STATE_AA64, 981 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 1, 982 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 983 }; 984 985 static void aarch64_neoverse_n2_initfn(Object *obj) 986 { 987 ARMCPU *cpu = ARM_CPU(obj); 988 989 cpu->dtb_compatible = "arm,neoverse-n2"; 990 set_feature(&cpu->env, ARM_FEATURE_V8); 991 set_feature(&cpu->env, ARM_FEATURE_NEON); 992 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 993 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 994 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 995 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 996 set_feature(&cpu->env, ARM_FEATURE_EL2); 997 set_feature(&cpu->env, ARM_FEATURE_EL3); 998 set_feature(&cpu->env, ARM_FEATURE_PMU); 999 1000 /* Ordered by Section B.5: AArch64 ID registers */ 1001 cpu->midr = 0x410FD493; /* r0p3 */ 1002 cpu->revidr = 0; 1003 cpu->isar.id_pfr0 = 0x21110131; 1004 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 1005 cpu->isar.id_dfr0 = 0x16011099; 1006 cpu->id_afr0 = 0; 1007 cpu->isar.id_mmfr0 = 0x10201105; 1008 cpu->isar.id_mmfr1 = 0x40000000; 1009 cpu->isar.id_mmfr2 = 0x01260000; 1010 cpu->isar.id_mmfr3 = 0x02122211; 1011 cpu->isar.id_isar0 = 0x02101110; 1012 cpu->isar.id_isar1 = 0x13112111; 1013 cpu->isar.id_isar2 = 0x21232042; 1014 cpu->isar.id_isar3 = 0x01112131; 1015 cpu->isar.id_isar4 = 0x00010142; 1016 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */ 1017 cpu->isar.id_mmfr4 = 0x01021110; 1018 cpu->isar.id_isar6 = 0x01111111; 1019 cpu->isar.mvfr0 = 0x10110222; 1020 cpu->isar.mvfr1 = 0x13211111; 1021 cpu->isar.mvfr2 = 0x00000043; 1022 cpu->isar.id_pfr2 = 0x00000011; 1023 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */ 1024 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; 1025 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */ 1026 cpu->isar.id_aa64dfr0 = 0x000011f210305619ull; 1027 cpu->isar.id_aa64dfr1 = 0; 1028 cpu->id_aa64afr0 = 0; 1029 cpu->id_aa64afr1 = 0; 1030 cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */ 1031 cpu->isar.id_aa64isar1 = 0x0011111101211052ull; 1032 cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull; 1033 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 1034 cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull; 1035 cpu->clidr = 0x0000001482000023ull; 1036 cpu->gm_blocksize = 4; 1037 cpu->ctr = 0x00000004b444c004ull; 1038 cpu->dcz_blocksize = 4; 1039 /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_001e_01ff */ 1040 1041 /* Section B.7.2: PMCR_EL0 */ 1042 cpu->isar.reset_pmcr_el0 = 0x3000; /* with 6 counters */ 1043 1044 /* Section B.8.9: ICH_VTR_EL2 */ 1045 cpu->gic_num_lrs = 4; 1046 cpu->gic_vpribits = 5; 1047 cpu->gic_vprebits = 5; 1048 cpu->gic_pribits = 5; 1049 1050 /* Section 14: Scalable Vector Extensions support */ 1051 cpu->sve_vq.supported = 1 << 0; /* 128bit */ 1052 1053 /* 1054 * The Neoverse N2 TRM does not list CCSIDR values. The layout of 1055 * the caches are in text in Table 7-1, Table 8-1, and Table 9-1. 1056 * 1057 * L1: 4-way set associative 64-byte line size, total 64K. 1058 * L2: 8-way set associative 64 byte line size, total either 512K or 1024K. 1059 */ 1060 cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ 1061 cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ 1062 cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ 1063 1064 /* FIXME: Not documented -- copied from neoverse-v1 */ 1065 cpu->reset_sctlr = 0x30c50838; 1066 1067 /* 1068 * The Neoverse N2 has all of the Cortex-A710 IMPDEF registers, 1069 * and a few more RNG related ones. 1070 */ 1071 define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); 1072 define_arm_cp_regs(cpu, neoverse_n2_cp_reginfo); 1073 1074 aarch64_add_pauth_properties(obj); 1075 aarch64_add_sve_properties(obj); 1076 } 1077 1078 /* 1079 * -cpu max: a CPU with as many features enabled as our emulation supports. 1080 * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; 1081 * this only needs to handle 64 bits. 1082 */ 1083 void aarch64_max_tcg_initfn(Object *obj) 1084 { 1085 ARMCPU *cpu = ARM_CPU(obj); 1086 uint64_t t; 1087 uint32_t u; 1088 1089 /* 1090 * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default 1091 * to because we started with aarch64_a57_initfn(). A 'max' CPU might 1092 * be a v8.6-or-later one, in which case the cntfrq must be 1GHz; and 1093 * because it is our "may change" CPU type we are OK with it not being 1094 * backwards-compatible with how it worked in old QEMU. 1095 */ 1096 unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 1097 1098 /* 1099 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 1100 * one and try to apply errata workarounds or use impdef features we 1101 * don't provide. 1102 * An IMPLEMENTER field of 0 means "reserved for software use"; 1103 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 1104 * to see which features are present"; 1105 * the VARIANT, PARTNUM and REVISION fields are all implementation 1106 * defined and we choose to define PARTNUM just in case guest 1107 * code needs to distinguish this QEMU CPU from other software 1108 * implementations, though this shouldn't be needed. 1109 */ 1110 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 1111 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 1112 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 1113 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 1114 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 1115 cpu->midr = t; 1116 1117 /* 1118 * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS} 1119 * are zero. 1120 */ 1121 u = cpu->clidr; 1122 u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); 1123 u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0); 1124 cpu->clidr = u; 1125 1126 /* 1127 * Set CTR_EL0.DIC and IDC to tell the guest it doesnt' need to 1128 * do any cache maintenance for data-to-instruction or 1129 * instruction-to-guest coherence. (Our cache ops are nops.) 1130 */ 1131 t = cpu->ctr; 1132 t = FIELD_DP64(t, CTR_EL0, IDC, 1); 1133 t = FIELD_DP64(t, CTR_EL0, DIC, 1); 1134 cpu->ctr = t; 1135 1136 t = cpu->isar.id_aa64isar0; 1137 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ 1138 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ 1139 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ 1140 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ 1141 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ 1142 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ 1143 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ 1144 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ 1145 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ 1146 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ 1147 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ 1148 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ 1149 t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ 1150 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ 1151 cpu->isar.id_aa64isar0 = t; 1152 1153 t = cpu->isar.id_aa64isar1; 1154 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ 1155 t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); 1156 t = FIELD_DP64(t, ID_AA64ISAR1, API, 1); 1157 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ 1158 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ 1159 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ 1160 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ 1161 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ 1162 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ 1163 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ 1164 t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ 1165 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ 1166 cpu->isar.id_aa64isar1 = t; 1167 1168 t = cpu->isar.id_aa64isar2; 1169 t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ 1170 t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ 1171 t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ 1172 cpu->isar.id_aa64isar2 = t; 1173 1174 t = cpu->isar.id_aa64pfr0; 1175 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ 1176 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ 1177 t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */ 1178 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 1179 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ 1180 t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ 1181 t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */ 1182 t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ 1183 cpu->isar.id_aa64pfr0 = t; 1184 1185 t = cpu->isar.id_aa64pfr1; 1186 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ 1187 t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ 1188 /* 1189 * Begin with full support for MTE. This will be downgraded to MTE=0 1190 * during realize if the board provides no tag memory, much like 1191 * we do for EL2 with the virtualization=on property. 1192 */ 1193 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ 1194 t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ 1195 t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ 1196 t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ 1197 t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ 1198 cpu->isar.id_aa64pfr1 = t; 1199 1200 t = cpu->isar.id_aa64mmfr0; 1201 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ 1202 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ 1203 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ 1204 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ 1205 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ 1206 t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ 1207 t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ 1208 cpu->isar.id_aa64mmfr0 = t; 1209 1210 t = cpu->isar.id_aa64mmfr1; 1211 t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ 1212 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ 1213 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ 1214 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */ 1215 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ 1216 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ 1217 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ 1218 t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */ 1219 t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ 1220 t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ 1221 cpu->isar.id_aa64mmfr1 = t; 1222 1223 t = cpu->isar.id_aa64mmfr2; 1224 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ 1225 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ 1226 t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ 1227 t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ 1228 t = FIELD_DP64(t, ID_AA64MMFR2, NV, 2); /* FEAT_NV2 */ 1229 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ 1230 t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ 1231 t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ 1232 t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ 1233 t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ 1234 t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ 1235 t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ 1236 t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ 1237 cpu->isar.id_aa64mmfr2 = t; 1238 1239 t = cpu->isar.id_aa64mmfr3; 1240 t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ 1241 cpu->isar.id_aa64mmfr3 = t; 1242 1243 t = cpu->isar.id_aa64zfr0; 1244 t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); 1245 t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ 1246 t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ 1247 t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ 1248 t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ 1249 t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ 1250 t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ 1251 t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ 1252 t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ 1253 cpu->isar.id_aa64zfr0 = t; 1254 1255 t = cpu->isar.id_aa64dfr0; 1256 t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ 1257 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ 1258 t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ 1259 cpu->isar.id_aa64dfr0 = t; 1260 1261 t = cpu->isar.id_aa64smfr0; 1262 t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ 1263 t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ 1264 t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ 1265 t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ 1266 t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ 1267 t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ 1268 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ 1269 cpu->isar.id_aa64smfr0 = t; 1270 1271 /* Replicate the same data to the 32-bit id registers. */ 1272 aa32_max_features(cpu); 1273 1274 #ifdef CONFIG_USER_ONLY 1275 /* 1276 * For usermode -cpu max we can use a larger and more efficient DCZ 1277 * blocksize since we don't have to follow what the hardware does. 1278 */ 1279 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 1280 cpu->dcz_blocksize = 7; /* 512 bytes */ 1281 #endif 1282 cpu->gm_blocksize = 6; /* 256 bytes */ 1283 1284 cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); 1285 cpu->sme_vq.supported = SVE_VQ_POW2_MAP; 1286 1287 aarch64_add_pauth_properties(obj); 1288 aarch64_add_sve_properties(obj); 1289 aarch64_add_sme_properties(obj); 1290 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, 1291 cpu_max_set_sve_max_vq, NULL, NULL); 1292 object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rme); 1293 object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, 1294 cpu_max_set_l0gptsz, NULL, NULL); 1295 qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); 1296 } 1297 1298 static const ARMCPUInfo aarch64_cpus[] = { 1299 { .name = "cortex-a35", .initfn = aarch64_a35_initfn }, 1300 { .name = "cortex-a55", .initfn = aarch64_a55_initfn }, 1301 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 1302 { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, 1303 { .name = "cortex-a710", .initfn = aarch64_a710_initfn }, 1304 { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, 1305 { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, 1306 { .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn }, 1307 { .name = "neoverse-n2", .initfn = aarch64_neoverse_n2_initfn }, 1308 }; 1309 1310 static void aarch64_cpu_register_types(void) 1311 { 1312 size_t i; 1313 1314 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 1315 aarch64_cpu_register(&aarch64_cpus[i]); 1316 } 1317 } 1318 1319 type_init(aarch64_cpu_register_types) 1320