1 /* 2 * QEMU AArch64 TCG CPUs 3 * 4 * Copyright (c) 2013 Linaro Ltd 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu/module.h" 25 #include "qapi/visitor.h" 26 #include "hw/qdev-properties.h" 27 #include "qemu/units.h" 28 #include "internals.h" 29 #include "cpregs.h" 30 31 static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize, 32 unsigned cachesize) 33 { 34 unsigned lg_linesize = ctz32(linesize); 35 unsigned sets; 36 37 /* 38 * The 64-bit CCSIDR_EL1 format is: 39 * [55:32] number of sets - 1 40 * [23:3] associativity - 1 41 * [2:0] log2(linesize) - 4 42 * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc 43 */ 44 assert(assoc != 0); 45 assert(is_power_of_2(linesize)); 46 assert(lg_linesize >= 4 && lg_linesize <= 7 + 4); 47 48 /* sets * associativity * linesize == cachesize. */ 49 sets = cachesize / (assoc * linesize); 50 assert(cachesize % (assoc * linesize) == 0); 51 52 return ((uint64_t)(sets - 1) << 32) 53 | ((assoc - 1) << 3) 54 | (lg_linesize - 4); 55 } 56 57 static void aarch64_a35_initfn(Object *obj) 58 { 59 ARMCPU *cpu = ARM_CPU(obj); 60 61 cpu->dtb_compatible = "arm,cortex-a35"; 62 set_feature(&cpu->env, ARM_FEATURE_V8); 63 set_feature(&cpu->env, ARM_FEATURE_NEON); 64 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 65 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 66 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 67 set_feature(&cpu->env, ARM_FEATURE_EL2); 68 set_feature(&cpu->env, ARM_FEATURE_EL3); 69 set_feature(&cpu->env, ARM_FEATURE_PMU); 70 71 /* From B2.2 AArch64 identification registers. */ 72 cpu->midr = 0x411fd040; 73 cpu->revidr = 0; 74 cpu->ctr = 0x84448004; 75 cpu->isar.id_pfr0 = 0x00000131; 76 cpu->isar.id_pfr1 = 0x00011011; 77 cpu->isar.id_dfr0 = 0x03010066; 78 cpu->id_afr0 = 0; 79 cpu->isar.id_mmfr0 = 0x10201105; 80 cpu->isar.id_mmfr1 = 0x40000000; 81 cpu->isar.id_mmfr2 = 0x01260000; 82 cpu->isar.id_mmfr3 = 0x02102211; 83 cpu->isar.id_isar0 = 0x02101110; 84 cpu->isar.id_isar1 = 0x13112111; 85 cpu->isar.id_isar2 = 0x21232042; 86 cpu->isar.id_isar3 = 0x01112131; 87 cpu->isar.id_isar4 = 0x00011142; 88 cpu->isar.id_isar5 = 0x00011121; 89 cpu->isar.id_aa64pfr0 = 0x00002222; 90 cpu->isar.id_aa64pfr1 = 0; 91 cpu->isar.id_aa64dfr0 = 0x10305106; 92 cpu->isar.id_aa64dfr1 = 0; 93 cpu->isar.id_aa64isar0 = 0x00011120; 94 cpu->isar.id_aa64isar1 = 0; 95 cpu->isar.id_aa64mmfr0 = 0x00101122; 96 cpu->isar.id_aa64mmfr1 = 0; 97 cpu->clidr = 0x0a200023; 98 cpu->dcz_blocksize = 4; 99 100 /* From B2.4 AArch64 Virtual Memory control registers */ 101 cpu->reset_sctlr = 0x00c50838; 102 103 /* From B2.10 AArch64 performance monitor registers */ 104 cpu->isar.reset_pmcr_el0 = 0x410a3000; 105 106 /* From B2.29 Cache ID registers */ 107 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 108 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 109 cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */ 110 111 /* From B3.5 VGIC Type register */ 112 cpu->gic_num_lrs = 4; 113 cpu->gic_vpribits = 5; 114 cpu->gic_vprebits = 5; 115 cpu->gic_pribits = 5; 116 117 /* From C6.4 Debug ID Register */ 118 cpu->isar.dbgdidr = 0x3516d000; 119 /* From C6.5 Debug Device ID Register */ 120 cpu->isar.dbgdevid = 0x00110f13; 121 /* From C6.6 Debug Device ID Register 1 */ 122 cpu->isar.dbgdevid1 = 0x2; 123 124 /* From Cortex-A35 SIMD and Floating-point Support r1p0 */ 125 /* From 3.2 AArch32 register summary */ 126 cpu->reset_fpsid = 0x41034043; 127 128 /* From 2.2 AArch64 register summary */ 129 cpu->isar.mvfr0 = 0x10110222; 130 cpu->isar.mvfr1 = 0x12111111; 131 cpu->isar.mvfr2 = 0x00000043; 132 133 /* These values are the same with A53/A57/A72. */ 134 define_cortex_a72_a57_a53_cp_reginfo(cpu); 135 } 136 137 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, 138 void *opaque, Error **errp) 139 { 140 ARMCPU *cpu = ARM_CPU(obj); 141 uint32_t value; 142 143 /* All vector lengths are disabled when SVE is off. */ 144 if (!cpu_isar_feature(aa64_sve, cpu)) { 145 value = 0; 146 } else { 147 value = cpu->sve_max_vq; 148 } 149 visit_type_uint32(v, name, &value, errp); 150 } 151 152 static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, 153 void *opaque, Error **errp) 154 { 155 ARMCPU *cpu = ARM_CPU(obj); 156 uint32_t max_vq; 157 158 if (!visit_type_uint32(v, name, &max_vq, errp)) { 159 return; 160 } 161 162 if (max_vq == 0 || max_vq > ARM_MAX_VQ) { 163 error_setg(errp, "unsupported SVE vector length"); 164 error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", 165 ARM_MAX_VQ); 166 return; 167 } 168 169 cpu->sve_max_vq = max_vq; 170 } 171 172 static bool cpu_arm_get_rme(Object *obj, Error **errp) 173 { 174 ARMCPU *cpu = ARM_CPU(obj); 175 return cpu_isar_feature(aa64_rme, cpu); 176 } 177 178 static void cpu_arm_set_rme(Object *obj, bool value, Error **errp) 179 { 180 ARMCPU *cpu = ARM_CPU(obj); 181 uint64_t t; 182 183 t = cpu->isar.id_aa64pfr0; 184 t = FIELD_DP64(t, ID_AA64PFR0, RME, value); 185 cpu->isar.id_aa64pfr0 = t; 186 } 187 188 static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, 189 void *opaque, Error **errp) 190 { 191 ARMCPU *cpu = ARM_CPU(obj); 192 uint32_t value; 193 194 if (!visit_type_uint32(v, name, &value, errp)) { 195 return; 196 } 197 198 /* Encode the value for the GPCCR_EL3 field. */ 199 switch (value) { 200 case 30: 201 case 34: 202 case 36: 203 case 39: 204 cpu->reset_l0gptsz = value - 30; 205 break; 206 default: 207 error_setg(errp, "invalid value for l0gptsz"); 208 error_append_hint(errp, "valid values are 30, 34, 36, 39\n"); 209 break; 210 } 211 } 212 213 static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name, 214 void *opaque, Error **errp) 215 { 216 ARMCPU *cpu = ARM_CPU(obj); 217 uint32_t value = cpu->reset_l0gptsz + 30; 218 219 visit_type_uint32(v, name, &value, errp); 220 } 221 222 static Property arm_cpu_lpa2_property = 223 DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); 224 225 static void aarch64_a55_initfn(Object *obj) 226 { 227 ARMCPU *cpu = ARM_CPU(obj); 228 229 cpu->dtb_compatible = "arm,cortex-a55"; 230 set_feature(&cpu->env, ARM_FEATURE_V8); 231 set_feature(&cpu->env, ARM_FEATURE_NEON); 232 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 233 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 234 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 235 set_feature(&cpu->env, ARM_FEATURE_EL2); 236 set_feature(&cpu->env, ARM_FEATURE_EL3); 237 set_feature(&cpu->env, ARM_FEATURE_PMU); 238 239 /* Ordered by B2.4 AArch64 registers by functional group */ 240 cpu->clidr = 0x82000023; 241 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ 242 cpu->dcz_blocksize = 4; /* 64 bytes */ 243 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; 244 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 245 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 246 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; 247 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 248 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 249 cpu->isar.id_aa64pfr0 = 0x0000000010112222ull; 250 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; 251 cpu->id_afr0 = 0x00000000; 252 cpu->isar.id_dfr0 = 0x04010088; 253 cpu->isar.id_isar0 = 0x02101110; 254 cpu->isar.id_isar1 = 0x13112111; 255 cpu->isar.id_isar2 = 0x21232042; 256 cpu->isar.id_isar3 = 0x01112131; 257 cpu->isar.id_isar4 = 0x00011142; 258 cpu->isar.id_isar5 = 0x01011121; 259 cpu->isar.id_isar6 = 0x00000010; 260 cpu->isar.id_mmfr0 = 0x10201105; 261 cpu->isar.id_mmfr1 = 0x40000000; 262 cpu->isar.id_mmfr2 = 0x01260000; 263 cpu->isar.id_mmfr3 = 0x02122211; 264 cpu->isar.id_mmfr4 = 0x00021110; 265 cpu->isar.id_pfr0 = 0x10010131; 266 cpu->isar.id_pfr1 = 0x00011011; 267 cpu->isar.id_pfr2 = 0x00000011; 268 cpu->midr = 0x412FD050; /* r2p0 */ 269 cpu->revidr = 0; 270 271 /* From B2.23 CCSIDR_EL1 */ 272 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 273 cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */ 274 cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */ 275 276 /* From B2.96 SCTLR_EL3 */ 277 cpu->reset_sctlr = 0x30c50838; 278 279 /* From B4.45 ICH_VTR_EL2 */ 280 cpu->gic_num_lrs = 4; 281 cpu->gic_vpribits = 5; 282 cpu->gic_vprebits = 5; 283 cpu->gic_pribits = 5; 284 285 cpu->isar.mvfr0 = 0x10110222; 286 cpu->isar.mvfr1 = 0x13211111; 287 cpu->isar.mvfr2 = 0x00000043; 288 289 /* From D5.4 AArch64 PMU register summary */ 290 cpu->isar.reset_pmcr_el0 = 0x410b3000; 291 } 292 293 static void aarch64_a72_initfn(Object *obj) 294 { 295 ARMCPU *cpu = ARM_CPU(obj); 296 297 cpu->dtb_compatible = "arm,cortex-a72"; 298 set_feature(&cpu->env, ARM_FEATURE_V8); 299 set_feature(&cpu->env, ARM_FEATURE_NEON); 300 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 301 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 302 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 303 set_feature(&cpu->env, ARM_FEATURE_EL2); 304 set_feature(&cpu->env, ARM_FEATURE_EL3); 305 set_feature(&cpu->env, ARM_FEATURE_PMU); 306 cpu->midr = 0x410fd083; 307 cpu->revidr = 0x00000000; 308 cpu->reset_fpsid = 0x41034080; 309 cpu->isar.mvfr0 = 0x10110222; 310 cpu->isar.mvfr1 = 0x12111111; 311 cpu->isar.mvfr2 = 0x00000043; 312 cpu->ctr = 0x8444c004; 313 cpu->reset_sctlr = 0x00c50838; 314 cpu->isar.id_pfr0 = 0x00000131; 315 cpu->isar.id_pfr1 = 0x00011011; 316 cpu->isar.id_dfr0 = 0x03010066; 317 cpu->id_afr0 = 0x00000000; 318 cpu->isar.id_mmfr0 = 0x10201105; 319 cpu->isar.id_mmfr1 = 0x40000000; 320 cpu->isar.id_mmfr2 = 0x01260000; 321 cpu->isar.id_mmfr3 = 0x02102211; 322 cpu->isar.id_isar0 = 0x02101110; 323 cpu->isar.id_isar1 = 0x13112111; 324 cpu->isar.id_isar2 = 0x21232042; 325 cpu->isar.id_isar3 = 0x01112131; 326 cpu->isar.id_isar4 = 0x00011142; 327 cpu->isar.id_isar5 = 0x00011121; 328 cpu->isar.id_aa64pfr0 = 0x00002222; 329 cpu->isar.id_aa64dfr0 = 0x10305106; 330 cpu->isar.id_aa64isar0 = 0x00011120; 331 cpu->isar.id_aa64mmfr0 = 0x00001124; 332 cpu->isar.dbgdidr = 0x3516d000; 333 cpu->isar.dbgdevid = 0x01110f13; 334 cpu->isar.dbgdevid1 = 0x2; 335 cpu->isar.reset_pmcr_el0 = 0x41023000; 336 cpu->clidr = 0x0a200023; 337 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 338 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 339 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ 340 cpu->dcz_blocksize = 4; /* 64 bytes */ 341 cpu->gic_num_lrs = 4; 342 cpu->gic_vpribits = 5; 343 cpu->gic_vprebits = 5; 344 cpu->gic_pribits = 5; 345 define_cortex_a72_a57_a53_cp_reginfo(cpu); 346 } 347 348 static void aarch64_a76_initfn(Object *obj) 349 { 350 ARMCPU *cpu = ARM_CPU(obj); 351 352 cpu->dtb_compatible = "arm,cortex-a76"; 353 set_feature(&cpu->env, ARM_FEATURE_V8); 354 set_feature(&cpu->env, ARM_FEATURE_NEON); 355 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 356 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 357 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 358 set_feature(&cpu->env, ARM_FEATURE_EL2); 359 set_feature(&cpu->env, ARM_FEATURE_EL3); 360 set_feature(&cpu->env, ARM_FEATURE_PMU); 361 362 /* Ordered by B2.4 AArch64 registers by functional group */ 363 cpu->clidr = 0x82000023; 364 cpu->ctr = 0x8444C004; 365 cpu->dcz_blocksize = 4; 366 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; 367 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 368 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 369 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; 370 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 371 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 372 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 373 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; 374 cpu->id_afr0 = 0x00000000; 375 cpu->isar.id_dfr0 = 0x04010088; 376 cpu->isar.id_isar0 = 0x02101110; 377 cpu->isar.id_isar1 = 0x13112111; 378 cpu->isar.id_isar2 = 0x21232042; 379 cpu->isar.id_isar3 = 0x01112131; 380 cpu->isar.id_isar4 = 0x00010142; 381 cpu->isar.id_isar5 = 0x01011121; 382 cpu->isar.id_isar6 = 0x00000010; 383 cpu->isar.id_mmfr0 = 0x10201105; 384 cpu->isar.id_mmfr1 = 0x40000000; 385 cpu->isar.id_mmfr2 = 0x01260000; 386 cpu->isar.id_mmfr3 = 0x02122211; 387 cpu->isar.id_mmfr4 = 0x00021110; 388 cpu->isar.id_pfr0 = 0x10010131; 389 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 390 cpu->isar.id_pfr2 = 0x00000011; 391 cpu->midr = 0x414fd0b1; /* r4p1 */ 392 cpu->revidr = 0; 393 394 /* From B2.18 CCSIDR_EL1 */ 395 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 396 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 397 cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ 398 399 /* From B2.93 SCTLR_EL3 */ 400 cpu->reset_sctlr = 0x30c50838; 401 402 /* From B4.23 ICH_VTR_EL2 */ 403 cpu->gic_num_lrs = 4; 404 cpu->gic_vpribits = 5; 405 cpu->gic_vprebits = 5; 406 cpu->gic_pribits = 5; 407 408 /* From B5.1 AdvSIMD AArch64 register summary */ 409 cpu->isar.mvfr0 = 0x10110222; 410 cpu->isar.mvfr1 = 0x13211111; 411 cpu->isar.mvfr2 = 0x00000043; 412 413 /* From D5.1 AArch64 PMU register summary */ 414 cpu->isar.reset_pmcr_el0 = 0x410b3000; 415 } 416 417 static void aarch64_a64fx_initfn(Object *obj) 418 { 419 ARMCPU *cpu = ARM_CPU(obj); 420 421 cpu->dtb_compatible = "arm,a64fx"; 422 set_feature(&cpu->env, ARM_FEATURE_V8); 423 set_feature(&cpu->env, ARM_FEATURE_NEON); 424 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 425 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 426 set_feature(&cpu->env, ARM_FEATURE_EL2); 427 set_feature(&cpu->env, ARM_FEATURE_EL3); 428 set_feature(&cpu->env, ARM_FEATURE_PMU); 429 cpu->midr = 0x461f0010; 430 cpu->revidr = 0x00000000; 431 cpu->ctr = 0x86668006; 432 cpu->reset_sctlr = 0x30000180; 433 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ 434 cpu->isar.id_aa64pfr1 = 0x0000000000000000; 435 cpu->isar.id_aa64dfr0 = 0x0000000010305408; 436 cpu->isar.id_aa64dfr1 = 0x0000000000000000; 437 cpu->id_aa64afr0 = 0x0000000000000000; 438 cpu->id_aa64afr1 = 0x0000000000000000; 439 cpu->isar.id_aa64mmfr0 = 0x0000000000001122; 440 cpu->isar.id_aa64mmfr1 = 0x0000000011212100; 441 cpu->isar.id_aa64mmfr2 = 0x0000000000001011; 442 cpu->isar.id_aa64isar0 = 0x0000000010211120; 443 cpu->isar.id_aa64isar1 = 0x0000000000010001; 444 cpu->isar.id_aa64zfr0 = 0x0000000000000000; 445 cpu->clidr = 0x0000000080000023; 446 cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ 447 cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ 448 cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ 449 cpu->dcz_blocksize = 6; /* 256 bytes */ 450 cpu->gic_num_lrs = 4; 451 cpu->gic_vpribits = 5; 452 cpu->gic_vprebits = 5; 453 cpu->gic_pribits = 5; 454 455 /* The A64FX supports only 128, 256 and 512 bit vector lengths */ 456 aarch64_add_sve_properties(obj); 457 cpu->sve_vq.supported = (1 << 0) /* 128bit */ 458 | (1 << 1) /* 256bit */ 459 | (1 << 3); /* 512bit */ 460 461 cpu->isar.reset_pmcr_el0 = 0x46014040; 462 463 /* TODO: Add A64FX specific HPC extension registers */ 464 } 465 466 static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r, 467 bool read) 468 { 469 if (!read) { 470 int el = arm_current_el(env); 471 472 /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */ 473 if (el < 2 && arm_is_el2_enabled(env)) { 474 return CP_ACCESS_TRAP_EL2; 475 } 476 /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */ 477 if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { 478 return CP_ACCESS_TRAP_EL3; 479 } 480 } 481 return CP_ACCESS_OK; 482 } 483 484 static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { 485 { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, 486 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, 487 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 488 /* Traps and enables are the same as for TCR_EL1. */ 489 .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, }, 490 { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, 491 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, 492 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 493 { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64, 494 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0, 495 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 496 { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64, 497 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0, 498 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 499 { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64, 500 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1, 501 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 502 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 503 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, 504 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 505 .accessfn = access_actlr_w }, 506 { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, 507 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, 508 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 509 .accessfn = access_actlr_w }, 510 { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, 511 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, 512 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 513 .accessfn = access_actlr_w }, 514 /* 515 * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU 516 * (and in particular its system registers). 517 */ 518 { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64, 519 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, 520 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, 521 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 522 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, 523 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010, 524 .accessfn = access_actlr_w }, 525 { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, 526 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, 527 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 528 { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64, 529 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3, 530 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 531 { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64, 532 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2, 533 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 534 { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64, 535 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0, 536 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 537 { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, 538 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, 539 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 540 .accessfn = access_actlr_w }, 541 { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64, 542 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2, 543 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 544 .accessfn = access_actlr_w }, 545 { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64, 546 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1, 547 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 548 .accessfn = access_actlr_w }, 549 { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64, 550 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, 551 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 552 .accessfn = access_actlr_w }, 553 }; 554 555 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) 556 { 557 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); 558 } 559 560 static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { 561 { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, 562 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, 563 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 564 .accessfn = access_actlr_w }, 565 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, 566 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, 567 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 568 { .name = "CPUPPMCR2_EL3", .state = ARM_CP_STATE_AA64, 569 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 1, 570 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 571 { .name = "CPUPPMCR3_EL3", .state = ARM_CP_STATE_AA64, 572 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6, 573 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 574 }; 575 576 static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) 577 { 578 /* 579 * The Neoverse V1 has all of the Neoverse N1's IMPDEF 580 * registers and a few more of its own. 581 */ 582 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); 583 define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo); 584 } 585 586 static void aarch64_neoverse_n1_initfn(Object *obj) 587 { 588 ARMCPU *cpu = ARM_CPU(obj); 589 590 cpu->dtb_compatible = "arm,neoverse-n1"; 591 set_feature(&cpu->env, ARM_FEATURE_V8); 592 set_feature(&cpu->env, ARM_FEATURE_NEON); 593 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 594 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 595 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 596 set_feature(&cpu->env, ARM_FEATURE_EL2); 597 set_feature(&cpu->env, ARM_FEATURE_EL3); 598 set_feature(&cpu->env, ARM_FEATURE_PMU); 599 600 /* Ordered by B2.4 AArch64 registers by functional group */ 601 cpu->clidr = 0x82000023; 602 cpu->ctr = 0x8444c004; 603 cpu->dcz_blocksize = 4; 604 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; 605 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; 606 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; 607 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; 608 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 609 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; 610 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ 611 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; 612 cpu->id_afr0 = 0x00000000; 613 cpu->isar.id_dfr0 = 0x04010088; 614 cpu->isar.id_isar0 = 0x02101110; 615 cpu->isar.id_isar1 = 0x13112111; 616 cpu->isar.id_isar2 = 0x21232042; 617 cpu->isar.id_isar3 = 0x01112131; 618 cpu->isar.id_isar4 = 0x00010142; 619 cpu->isar.id_isar5 = 0x01011121; 620 cpu->isar.id_isar6 = 0x00000010; 621 cpu->isar.id_mmfr0 = 0x10201105; 622 cpu->isar.id_mmfr1 = 0x40000000; 623 cpu->isar.id_mmfr2 = 0x01260000; 624 cpu->isar.id_mmfr3 = 0x02122211; 625 cpu->isar.id_mmfr4 = 0x00021110; 626 cpu->isar.id_pfr0 = 0x10010131; 627 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 628 cpu->isar.id_pfr2 = 0x00000011; 629 cpu->midr = 0x414fd0c1; /* r4p1 */ 630 cpu->revidr = 0; 631 632 /* From B2.23 CCSIDR_EL1 */ 633 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ 634 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ 635 cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ 636 637 /* From B2.98 SCTLR_EL3 */ 638 cpu->reset_sctlr = 0x30c50838; 639 640 /* From B4.23 ICH_VTR_EL2 */ 641 cpu->gic_num_lrs = 4; 642 cpu->gic_vpribits = 5; 643 cpu->gic_vprebits = 5; 644 cpu->gic_pribits = 5; 645 646 /* From B5.1 AdvSIMD AArch64 register summary */ 647 cpu->isar.mvfr0 = 0x10110222; 648 cpu->isar.mvfr1 = 0x13211111; 649 cpu->isar.mvfr2 = 0x00000043; 650 651 /* From D5.1 AArch64 PMU register summary */ 652 cpu->isar.reset_pmcr_el0 = 0x410c3000; 653 654 define_neoverse_n1_cp_reginfo(cpu); 655 } 656 657 static void aarch64_neoverse_v1_initfn(Object *obj) 658 { 659 ARMCPU *cpu = ARM_CPU(obj); 660 661 cpu->dtb_compatible = "arm,neoverse-v1"; 662 set_feature(&cpu->env, ARM_FEATURE_V8); 663 set_feature(&cpu->env, ARM_FEATURE_NEON); 664 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 665 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 666 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 667 set_feature(&cpu->env, ARM_FEATURE_EL2); 668 set_feature(&cpu->env, ARM_FEATURE_EL3); 669 set_feature(&cpu->env, ARM_FEATURE_PMU); 670 671 /* Ordered by 3.2.4 AArch64 registers by functional group */ 672 cpu->clidr = 0x82000023; 673 cpu->ctr = 0xb444c004; /* With DIC and IDC set */ 674 cpu->dcz_blocksize = 4; 675 cpu->id_aa64afr0 = 0x00000000; 676 cpu->id_aa64afr1 = 0x00000000; 677 cpu->isar.id_aa64dfr0 = 0x000001f210305519ull; 678 cpu->isar.id_aa64dfr1 = 0x00000000; 679 cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */ 680 cpu->isar.id_aa64isar1 = 0x0111000001211032ull; 681 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; 682 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 683 cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull; 684 cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */ 685 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; 686 cpu->id_afr0 = 0x00000000; 687 cpu->isar.id_dfr0 = 0x15011099; 688 cpu->isar.id_isar0 = 0x02101110; 689 cpu->isar.id_isar1 = 0x13112111; 690 cpu->isar.id_isar2 = 0x21232042; 691 cpu->isar.id_isar3 = 0x01112131; 692 cpu->isar.id_isar4 = 0x00010142; 693 cpu->isar.id_isar5 = 0x11011121; 694 cpu->isar.id_isar6 = 0x01100111; 695 cpu->isar.id_mmfr0 = 0x10201105; 696 cpu->isar.id_mmfr1 = 0x40000000; 697 cpu->isar.id_mmfr2 = 0x01260000; 698 cpu->isar.id_mmfr3 = 0x02122211; 699 cpu->isar.id_mmfr4 = 0x01021110; 700 cpu->isar.id_pfr0 = 0x21110131; 701 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 702 cpu->isar.id_pfr2 = 0x00000011; 703 cpu->midr = 0x411FD402; /* r1p2 */ 704 cpu->revidr = 0; 705 706 /* 707 * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values, 708 * but also says it implements CCIDX, which means they should be 709 * 64-bit format. So we here use values which are based on the textual 710 * information in chapter 2 of the TRM: 711 * 712 * L1: 4-way set associative 64-byte line size, total size 64K. 713 * L2: 8-way set associative, 64 byte line size, either 512K or 1MB. 714 * L3: No L3 (this matches the CLIDR_EL1 value). 715 */ 716 cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ 717 cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ 718 cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */ 719 720 /* From 3.2.115 SCTLR_EL3 */ 721 cpu->reset_sctlr = 0x30c50838; 722 723 /* From 3.4.8 ICC_CTLR_EL3 and 3.4.23 ICH_VTR_EL2 */ 724 cpu->gic_num_lrs = 4; 725 cpu->gic_vpribits = 5; 726 cpu->gic_vprebits = 5; 727 cpu->gic_pribits = 5; 728 729 /* From 3.5.1 AdvSIMD AArch64 register summary */ 730 cpu->isar.mvfr0 = 0x10110222; 731 cpu->isar.mvfr1 = 0x13211111; 732 cpu->isar.mvfr2 = 0x00000043; 733 734 /* From 3.7.5 ID_AA64ZFR0_EL1 */ 735 cpu->isar.id_aa64zfr0 = 0x0000100000100000; 736 cpu->sve_vq.supported = (1 << 0) /* 128bit */ 737 | (1 << 1); /* 256bit */ 738 739 /* From 5.5.1 AArch64 PMU register summary */ 740 cpu->isar.reset_pmcr_el0 = 0x41213000; 741 742 define_neoverse_v1_cp_reginfo(cpu); 743 744 aarch64_add_pauth_properties(obj); 745 aarch64_add_sve_properties(obj); 746 } 747 748 static const ARMCPRegInfo cortex_a710_cp_reginfo[] = { 749 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 750 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, 751 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 752 .accessfn = access_actlr_w }, 753 { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, 754 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, 755 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 756 .accessfn = access_actlr_w }, 757 { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, 758 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, 759 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 760 .accessfn = access_actlr_w }, 761 { .name = "CPUACTLR4_EL1", .state = ARM_CP_STATE_AA64, 762 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 3, 763 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 764 .accessfn = access_actlr_w }, 765 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 766 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, 767 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 768 .accessfn = access_actlr_w }, 769 { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, 770 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, 771 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 772 .accessfn = access_actlr_w }, 773 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, 774 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 4, 775 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 776 { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, 777 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, 778 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 779 .accessfn = access_actlr_w }, 780 { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, 781 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, 782 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 783 { .name = "CPUACTLR5_EL1", .state = ARM_CP_STATE_AA64, 784 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 0, 785 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 786 .accessfn = access_actlr_w }, 787 { .name = "CPUACTLR6_EL1", .state = ARM_CP_STATE_AA64, 788 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 1, 789 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 790 .accessfn = access_actlr_w }, 791 { .name = "CPUACTLR7_EL1", .state = ARM_CP_STATE_AA64, 792 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 2, 793 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, 794 .accessfn = access_actlr_w }, 795 { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, 796 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, 797 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 798 { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64, 799 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1, 800 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 801 { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, 802 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, 803 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 804 { .name = "CPUPPMCR2_EL3", .state = ARM_CP_STATE_AA64, 805 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 1, 806 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 807 { .name = "CPUPPMCR4_EL3", .state = ARM_CP_STATE_AA64, 808 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 4, 809 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 810 { .name = "CPUPPMCR5_EL3", .state = ARM_CP_STATE_AA64, 811 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 5, 812 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 813 { .name = "CPUPPMCR6_EL3", .state = ARM_CP_STATE_AA64, 814 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6, 815 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 816 { .name = "CPUACTLR_EL3", .state = ARM_CP_STATE_AA64, 817 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 4, .opc2 = 0, 818 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 819 { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64, 820 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0, 821 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 822 { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64, 823 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0, 824 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 825 { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, 826 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, 827 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 828 { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64, 829 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2, 830 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 831 { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64, 832 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3, 833 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 834 { .name = "CPUPOR2_EL3", .state = ARM_CP_STATE_AA64, 835 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 4, 836 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 837 { .name = "CPUPMR2_EL3", .state = ARM_CP_STATE_AA64, 838 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 5, 839 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 840 { .name = "CPUPFR_EL3", .state = ARM_CP_STATE_AA64, 841 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 6, 842 .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 843 844 /* 845 * Stub RAMINDEX, as we don't actually implement caches, BTB, 846 * or anything else with cpu internal memory. 847 * "Read" zeros into the IDATA* and DDATA* output registers. 848 */ 849 { .name = "RAMINDEX_EL3", .state = ARM_CP_STATE_AA64, 850 .opc0 = 1, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0, 851 .access = PL3_W, .type = ARM_CP_CONST, .resetvalue = 0 }, 852 { .name = "IDATA0_EL3", .state = ARM_CP_STATE_AA64, 853 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0, 854 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 855 { .name = "IDATA1_EL3", .state = ARM_CP_STATE_AA64, 856 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 1, 857 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 858 { .name = "IDATA2_EL3", .state = ARM_CP_STATE_AA64, 859 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 2, 860 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 861 { .name = "DDATA0_EL3", .state = ARM_CP_STATE_AA64, 862 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 0, 863 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 864 { .name = "DDATA1_EL3", .state = ARM_CP_STATE_AA64, 865 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 1, 866 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 867 { .name = "DDATA2_EL3", .state = ARM_CP_STATE_AA64, 868 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 2, 869 .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 870 }; 871 872 static void aarch64_a710_initfn(Object *obj) 873 { 874 ARMCPU *cpu = ARM_CPU(obj); 875 876 cpu->dtb_compatible = "arm,cortex-a710"; 877 set_feature(&cpu->env, ARM_FEATURE_V8); 878 set_feature(&cpu->env, ARM_FEATURE_NEON); 879 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 880 set_feature(&cpu->env, ARM_FEATURE_AARCH64); 881 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 882 set_feature(&cpu->env, ARM_FEATURE_EL2); 883 set_feature(&cpu->env, ARM_FEATURE_EL3); 884 set_feature(&cpu->env, ARM_FEATURE_PMU); 885 886 /* Ordered by Section B.4: AArch64 registers */ 887 cpu->midr = 0x412FD471; /* r2p1 */ 888 cpu->revidr = 0; 889 cpu->isar.id_pfr0 = 0x21110131; 890 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ 891 cpu->isar.id_dfr0 = 0x16011099; 892 cpu->id_afr0 = 0; 893 cpu->isar.id_mmfr0 = 0x10201105; 894 cpu->isar.id_mmfr1 = 0x40000000; 895 cpu->isar.id_mmfr2 = 0x01260000; 896 cpu->isar.id_mmfr3 = 0x02122211; 897 cpu->isar.id_isar0 = 0x02101110; 898 cpu->isar.id_isar1 = 0x13112111; 899 cpu->isar.id_isar2 = 0x21232042; 900 cpu->isar.id_isar3 = 0x01112131; 901 cpu->isar.id_isar4 = 0x00010142; 902 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */ 903 cpu->isar.id_mmfr4 = 0x21021110; 904 cpu->isar.id_isar6 = 0x01111111; 905 cpu->isar.mvfr0 = 0x10110222; 906 cpu->isar.mvfr1 = 0x13211111; 907 cpu->isar.mvfr2 = 0x00000043; 908 cpu->isar.id_pfr2 = 0x00000011; 909 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */ 910 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; 911 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */ 912 cpu->isar.id_aa64dfr0 = 0x000011f010305611ull; 913 cpu->isar.id_aa64dfr1 = 0; 914 cpu->id_aa64afr0 = 0; 915 cpu->id_aa64afr1 = 0; 916 cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */ 917 cpu->isar.id_aa64isar1 = 0x0010111101211032ull; 918 cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull; 919 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; 920 cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull; 921 cpu->clidr = 0x0000001482000023ull; 922 cpu->gm_blocksize = 4; 923 cpu->ctr = 0x000000049444c004ull; 924 cpu->dcz_blocksize = 4; 925 /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_0006_003f */ 926 927 /* Section B.5.2: PMCR_EL0 */ 928 cpu->isar.reset_pmcr_el0 = 0xa000; /* with 20 counters */ 929 930 /* Section B.6.7: ICH_VTR_EL2 */ 931 cpu->gic_num_lrs = 4; 932 cpu->gic_vpribits = 5; 933 cpu->gic_vprebits = 5; 934 cpu->gic_pribits = 5; 935 936 /* Section 14: Scalable Vector Extensions support */ 937 cpu->sve_vq.supported = 1 << 0; /* 128bit */ 938 939 /* 940 * The cortex-a710 TRM does not list CCSIDR values. The layout of 941 * the caches are in text in Table 7-1, Table 8-1, and Table 9-1. 942 * 943 * L1: 4-way set associative 64-byte line size, total either 32K or 64K. 944 * L2: 8-way set associative 64 byte line size, total either 256K or 512K. 945 */ 946 cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ 947 cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ 948 cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ 949 950 /* FIXME: Not documented -- copied from neoverse-v1 */ 951 cpu->reset_sctlr = 0x30c50838; 952 953 define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); 954 955 aarch64_add_pauth_properties(obj); 956 aarch64_add_sve_properties(obj); 957 } 958 959 /* 960 * -cpu max: a CPU with as many features enabled as our emulation supports. 961 * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; 962 * this only needs to handle 64 bits. 963 */ 964 void aarch64_max_tcg_initfn(Object *obj) 965 { 966 ARMCPU *cpu = ARM_CPU(obj); 967 uint64_t t; 968 uint32_t u; 969 970 /* 971 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real 972 * one and try to apply errata workarounds or use impdef features we 973 * don't provide. 974 * An IMPLEMENTER field of 0 means "reserved for software use"; 975 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers 976 * to see which features are present"; 977 * the VARIANT, PARTNUM and REVISION fields are all implementation 978 * defined and we choose to define PARTNUM just in case guest 979 * code needs to distinguish this QEMU CPU from other software 980 * implementations, though this shouldn't be needed. 981 */ 982 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); 983 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); 984 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); 985 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); 986 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); 987 cpu->midr = t; 988 989 /* 990 * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS} 991 * are zero. 992 */ 993 u = cpu->clidr; 994 u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); 995 u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0); 996 cpu->clidr = u; 997 998 t = cpu->isar.id_aa64isar0; 999 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ 1000 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ 1001 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ 1002 t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ 1003 t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ 1004 t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ 1005 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ 1006 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ 1007 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ 1008 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ 1009 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ 1010 t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ 1011 t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ 1012 t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ 1013 cpu->isar.id_aa64isar0 = t; 1014 1015 t = cpu->isar.id_aa64isar1; 1016 t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ 1017 t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); 1018 t = FIELD_DP64(t, ID_AA64ISAR1, API, 1); 1019 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ 1020 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ 1021 t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ 1022 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ 1023 t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ 1024 t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ 1025 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ 1026 t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ 1027 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ 1028 cpu->isar.id_aa64isar1 = t; 1029 1030 t = cpu->isar.id_aa64pfr0; 1031 t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ 1032 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ 1033 t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */ 1034 t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); 1035 t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ 1036 t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ 1037 t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ 1038 t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ 1039 cpu->isar.id_aa64pfr0 = t; 1040 1041 t = cpu->isar.id_aa64pfr1; 1042 t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ 1043 t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ 1044 /* 1045 * Begin with full support for MTE. This will be downgraded to MTE=0 1046 * during realize if the board provides no tag memory, much like 1047 * we do for EL2 with the virtualization=on property. 1048 */ 1049 t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ 1050 t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ 1051 t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ 1052 t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ 1053 cpu->isar.id_aa64pfr1 = t; 1054 1055 t = cpu->isar.id_aa64mmfr0; 1056 t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ 1057 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ 1058 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ 1059 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ 1060 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ 1061 t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ 1062 cpu->isar.id_aa64mmfr0 = t; 1063 1064 t = cpu->isar.id_aa64mmfr1; 1065 t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ 1066 t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ 1067 t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ 1068 t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */ 1069 t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ 1070 t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ 1071 t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ 1072 t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ 1073 t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ 1074 t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ 1075 cpu->isar.id_aa64mmfr1 = t; 1076 1077 t = cpu->isar.id_aa64mmfr2; 1078 t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ 1079 t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ 1080 t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ 1081 t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ 1082 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ 1083 t = FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ 1084 t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ 1085 t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ 1086 t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ 1087 t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ 1088 t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ 1089 t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ 1090 cpu->isar.id_aa64mmfr2 = t; 1091 1092 t = cpu->isar.id_aa64zfr0; 1093 t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); 1094 t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ 1095 t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ 1096 t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ 1097 t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ 1098 t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ 1099 t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ 1100 t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ 1101 t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ 1102 cpu->isar.id_aa64zfr0 = t; 1103 1104 t = cpu->isar.id_aa64dfr0; 1105 t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ 1106 t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ 1107 cpu->isar.id_aa64dfr0 = t; 1108 1109 t = cpu->isar.id_aa64smfr0; 1110 t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ 1111 t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ 1112 t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ 1113 t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ 1114 t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ 1115 t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ 1116 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ 1117 cpu->isar.id_aa64smfr0 = t; 1118 1119 /* Replicate the same data to the 32-bit id registers. */ 1120 aa32_max_features(cpu); 1121 1122 #ifdef CONFIG_USER_ONLY 1123 /* 1124 * For usermode -cpu max we can use a larger and more efficient DCZ 1125 * blocksize since we don't have to follow what the hardware does. 1126 */ 1127 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ 1128 cpu->dcz_blocksize = 7; /* 512 bytes */ 1129 #endif 1130 cpu->gm_blocksize = 6; /* 256 bytes */ 1131 1132 cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); 1133 cpu->sme_vq.supported = SVE_VQ_POW2_MAP; 1134 1135 aarch64_add_pauth_properties(obj); 1136 aarch64_add_sve_properties(obj); 1137 aarch64_add_sme_properties(obj); 1138 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, 1139 cpu_max_set_sve_max_vq, NULL, NULL); 1140 object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rme); 1141 object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, 1142 cpu_max_set_l0gptsz, NULL, NULL); 1143 qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); 1144 } 1145 1146 static const ARMCPUInfo aarch64_cpus[] = { 1147 { .name = "cortex-a35", .initfn = aarch64_a35_initfn }, 1148 { .name = "cortex-a55", .initfn = aarch64_a55_initfn }, 1149 { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, 1150 { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, 1151 { .name = "cortex-a710", .initfn = aarch64_a710_initfn }, 1152 { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, 1153 { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, 1154 { .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn }, 1155 }; 1156 1157 static void aarch64_cpu_register_types(void) 1158 { 1159 size_t i; 1160 1161 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { 1162 aarch64_cpu_register(&aarch64_cpus[i]); 1163 } 1164 } 1165 1166 type_init(aarch64_cpu_register_types) 1167