1 /* 2 * QEMU ARM TCG-only CPUs. 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This code is licensed under the GNU GPL v2 or later. 7 * 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 11 #include "qemu/osdep.h" 12 #include "cpu.h" 13 #include "accel/tcg/cpu-ops.h" 14 #include "internals.h" 15 #include "target/arm/idau.h" 16 #if !defined(CONFIG_USER_ONLY) 17 #include "hw/boards.h" 18 #endif 19 #include "cpregs.h" 20 21 22 /* Share AArch32 -cpu max features with AArch64. */ 23 void aa32_max_features(ARMCPU *cpu) 24 { 25 uint32_t t; 26 ARMISARegisters *isar = &cpu->isar; 27 28 /* Add additional features supported by QEMU */ 29 t = GET_IDREG(isar, ID_ISAR5); 30 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ 31 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ 32 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ 33 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 34 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ 35 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ 36 SET_IDREG(isar, ID_ISAR5, t); 37 38 t = GET_IDREG(isar, ID_ISAR6); 39 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ 40 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ 41 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ 42 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ 43 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ 44 t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ 45 t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ 46 SET_IDREG(isar, ID_ISAR6, t); 47 48 t = cpu->isar.mvfr1; 49 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ 50 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ 51 cpu->isar.mvfr1 = t; 52 53 t = cpu->isar.mvfr2; 54 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 55 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 56 cpu->isar.mvfr2 = t; 57 58 FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ 59 60 t = GET_IDREG(isar, ID_MMFR4); 61 t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ 62 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 63 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ 64 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ 65 t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ 66 SET_IDREG(isar, ID_MMFR4, t); 67 68 FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ 69 70 t = GET_IDREG(isar, ID_PFR0); 71 t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ 72 t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ 73 t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ 74 SET_IDREG(isar, ID_PFR0, t); 75 76 t = GET_IDREG(isar, ID_PFR2); 77 t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ 78 t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ 79 SET_IDREG(isar, ID_PFR2, t); 80 81 t = GET_IDREG(isar, ID_DFR0); 82 t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ 83 t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ 84 t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ 85 SET_IDREG(isar, ID_DFR0, t); 86 87 /* Debug ID registers. */ 88 89 /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ 90 t = 0x00008000; 91 t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); 92 t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); 93 t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ 94 t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); 95 t = FIELD_DP32(t, DBGDIDR, BRPS, 5); 96 t = FIELD_DP32(t, DBGDIDR, WRPS, 3); 97 cpu->isar.dbgdidr = t; 98 99 t = 0; 100 t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); 101 t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); 102 t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); 103 t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); 104 t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); 105 t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); 106 t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0); 107 t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0); 108 cpu->isar.dbgdevid = t; 109 110 /* Bits[31:4] are RES0. */ 111 t = 0; 112 t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); 113 cpu->isar.dbgdevid1 = t; 114 115 FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ 116 } 117 118 /* CPU models. These are not needed for the AArch64 linux-user build. */ 119 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 120 121 static void arm926_initfn(Object *obj) 122 { 123 ARMCPU *cpu = ARM_CPU(obj); 124 125 cpu->dtb_compatible = "arm,arm926"; 126 set_feature(&cpu->env, ARM_FEATURE_V5); 127 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 128 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 129 cpu->midr = 0x41069265; 130 cpu->reset_fpsid = 0x41011090; 131 cpu->ctr = 0x1dd20d2; 132 cpu->reset_sctlr = 0x00090078; 133 134 /* 135 * ARMv5 does not have the ID_ISAR registers, but we can still 136 * set the field to indicate Jazelle support within QEMU. 137 */ 138 FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); 139 /* 140 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 141 * support even though ARMv5 doesn't have this register. 142 */ 143 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 144 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 145 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 146 } 147 148 static void arm946_initfn(Object *obj) 149 { 150 ARMCPU *cpu = ARM_CPU(obj); 151 152 cpu->dtb_compatible = "arm,arm946"; 153 set_feature(&cpu->env, ARM_FEATURE_V5); 154 set_feature(&cpu->env, ARM_FEATURE_PMSA); 155 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 156 cpu->midr = 0x41059461; 157 cpu->ctr = 0x0f004006; 158 cpu->reset_sctlr = 0x00000078; 159 } 160 161 static void arm1026_initfn(Object *obj) 162 { 163 ARMCPU *cpu = ARM_CPU(obj); 164 165 cpu->dtb_compatible = "arm,arm1026"; 166 set_feature(&cpu->env, ARM_FEATURE_V5); 167 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 168 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 169 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 170 cpu->midr = 0x4106a262; 171 cpu->reset_fpsid = 0x410110a0; 172 cpu->ctr = 0x1dd20d2; 173 cpu->reset_sctlr = 0x00090078; 174 cpu->reset_auxcr = 1; 175 176 /* 177 * ARMv5 does not have the ID_ISAR registers, but we can still 178 * set the field to indicate Jazelle support within QEMU. 179 */ 180 FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); 181 /* 182 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 183 * support even though ARMv5 doesn't have this register. 184 */ 185 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 186 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 187 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 188 189 { 190 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 191 ARMCPRegInfo ifar = { 192 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 193 .access = PL1_RW, 194 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 195 .resetvalue = 0 196 }; 197 define_one_arm_cp_reg(cpu, &ifar); 198 } 199 } 200 201 static void arm1136_r2_initfn(Object *obj) 202 { 203 ARMCPU *cpu = ARM_CPU(obj); 204 ARMISARegisters *isar = &cpu->isar; 205 /* 206 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 207 * older core than plain "arm1136". In particular this does not 208 * have the v6K features. 209 * These ID register values are correct for 1136 but may be wrong 210 * for 1136_r2 (in particular r0p2 does not actually implement most 211 * of the ID registers). 212 */ 213 214 cpu->dtb_compatible = "arm,arm1136"; 215 set_feature(&cpu->env, ARM_FEATURE_V6); 216 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 217 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 218 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 219 cpu->midr = 0x4107b362; 220 cpu->reset_fpsid = 0x410120b4; 221 cpu->isar.mvfr0 = 0x11111111; 222 cpu->isar.mvfr1 = 0x00000000; 223 cpu->ctr = 0x1dd20d2; 224 cpu->reset_sctlr = 0x00050078; 225 SET_IDREG(isar, ID_PFR0, 0x111); 226 SET_IDREG(isar, ID_PFR1, 0x1); 227 SET_IDREG(isar, ID_DFR0, 0x2); 228 SET_IDREG(isar, ID_AFR0, 0x3); 229 SET_IDREG(isar, ID_MMFR0, 0x01130003); 230 SET_IDREG(isar, ID_MMFR1, 0x10030302); 231 SET_IDREG(isar, ID_MMFR2, 0x01222110); 232 SET_IDREG(isar, ID_ISAR0, 0x00140011); 233 SET_IDREG(isar, ID_ISAR1, 0x12002111); 234 SET_IDREG(isar, ID_ISAR2, 0x11231111); 235 SET_IDREG(isar, ID_ISAR3, 0x01102131); 236 SET_IDREG(isar, ID_ISAR4, 0x141); 237 cpu->reset_auxcr = 7; 238 } 239 240 static void arm1136_initfn(Object *obj) 241 { 242 ARMCPU *cpu = ARM_CPU(obj); 243 ARMISARegisters *isar = &cpu->isar; 244 245 cpu->dtb_compatible = "arm,arm1136"; 246 set_feature(&cpu->env, ARM_FEATURE_V6K); 247 set_feature(&cpu->env, ARM_FEATURE_V6); 248 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 249 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 250 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 251 cpu->midr = 0x4117b363; 252 cpu->reset_fpsid = 0x410120b4; 253 cpu->isar.mvfr0 = 0x11111111; 254 cpu->isar.mvfr1 = 0x00000000; 255 cpu->ctr = 0x1dd20d2; 256 cpu->reset_sctlr = 0x00050078; 257 SET_IDREG(isar, ID_PFR0, 0x111); 258 SET_IDREG(isar, ID_PFR1, 0x1); 259 SET_IDREG(isar, ID_DFR0, 0x2); 260 SET_IDREG(isar, ID_AFR0, 0x3); 261 SET_IDREG(isar, ID_MMFR0, 0x01130003); 262 SET_IDREG(isar, ID_MMFR1, 0x10030302); 263 SET_IDREG(isar, ID_MMFR2, 0x01222110); 264 SET_IDREG(isar, ID_ISAR0, 0x00140011); 265 SET_IDREG(isar, ID_ISAR1, 0x12002111); 266 SET_IDREG(isar, ID_ISAR2, 0x11231111); 267 SET_IDREG(isar, ID_ISAR3, 0x01102131); 268 SET_IDREG(isar, ID_ISAR4, 0x141); 269 cpu->reset_auxcr = 7; 270 } 271 272 static void arm1176_initfn(Object *obj) 273 { 274 ARMCPU *cpu = ARM_CPU(obj); 275 ARMISARegisters *isar = &cpu->isar; 276 277 cpu->dtb_compatible = "arm,arm1176"; 278 set_feature(&cpu->env, ARM_FEATURE_V6K); 279 set_feature(&cpu->env, ARM_FEATURE_VAPA); 280 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 281 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 282 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 283 set_feature(&cpu->env, ARM_FEATURE_EL3); 284 cpu->midr = 0x410fb767; 285 cpu->reset_fpsid = 0x410120b5; 286 cpu->isar.mvfr0 = 0x11111111; 287 cpu->isar.mvfr1 = 0x00000000; 288 cpu->ctr = 0x1dd20d2; 289 cpu->reset_sctlr = 0x00050078; 290 SET_IDREG(isar, ID_PFR0, 0x111); 291 SET_IDREG(isar, ID_PFR1, 0x11); 292 SET_IDREG(isar, ID_DFR0, 0x33); 293 SET_IDREG(isar, ID_AFR0, 0); 294 SET_IDREG(isar, ID_MMFR0, 0x01130003); 295 SET_IDREG(isar, ID_MMFR1, 0x10030302); 296 SET_IDREG(isar, ID_MMFR2, 0x01222100); 297 SET_IDREG(isar, ID_ISAR0, 0x0140011); 298 SET_IDREG(isar, ID_ISAR1, 0x12002111); 299 SET_IDREG(isar, ID_ISAR2, 0x11231121); 300 SET_IDREG(isar, ID_ISAR3, 0x01102131); 301 SET_IDREG(isar, ID_ISAR4, 0x01141); 302 cpu->reset_auxcr = 7; 303 } 304 305 static void arm11mpcore_initfn(Object *obj) 306 { 307 ARMCPU *cpu = ARM_CPU(obj); 308 ARMISARegisters *isar = &cpu->isar; 309 310 cpu->dtb_compatible = "arm,arm11mpcore"; 311 set_feature(&cpu->env, ARM_FEATURE_V6K); 312 set_feature(&cpu->env, ARM_FEATURE_VAPA); 313 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 314 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 315 cpu->midr = 0x410fb022; 316 cpu->reset_fpsid = 0x410120b4; 317 cpu->isar.mvfr0 = 0x11111111; 318 cpu->isar.mvfr1 = 0x00000000; 319 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 320 SET_IDREG(isar, ID_PFR0, 0x111); 321 SET_IDREG(isar, ID_PFR1, 0x1); 322 SET_IDREG(isar, ID_DFR0, 0); 323 SET_IDREG(isar, ID_AFR0, 0x2); 324 SET_IDREG(isar, ID_MMFR0, 0x01100103); 325 SET_IDREG(isar, ID_MMFR1, 0x10020302); 326 SET_IDREG(isar, ID_MMFR2, 0x01222000); 327 SET_IDREG(isar, ID_ISAR0, 0x00100011); 328 SET_IDREG(isar, ID_ISAR1, 0x12002111); 329 SET_IDREG(isar, ID_ISAR2, 0x11221011); 330 SET_IDREG(isar, ID_ISAR3, 0x01102131); 331 SET_IDREG(isar, ID_ISAR4, 0x141); 332 cpu->reset_auxcr = 1; 333 } 334 335 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 336 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 337 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 338 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 339 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 340 }; 341 342 static void cortex_a8_initfn(Object *obj) 343 { 344 ARMCPU *cpu = ARM_CPU(obj); 345 ARMISARegisters *isar = &cpu->isar; 346 347 cpu->dtb_compatible = "arm,cortex-a8"; 348 set_feature(&cpu->env, ARM_FEATURE_V7); 349 set_feature(&cpu->env, ARM_FEATURE_NEON); 350 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 351 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 352 set_feature(&cpu->env, ARM_FEATURE_EL3); 353 set_feature(&cpu->env, ARM_FEATURE_PMU); 354 cpu->midr = 0x410fc080; 355 cpu->reset_fpsid = 0x410330c0; 356 cpu->isar.mvfr0 = 0x11110222; 357 cpu->isar.mvfr1 = 0x00011111; 358 cpu->ctr = 0x82048004; 359 cpu->reset_sctlr = 0x00c50078; 360 SET_IDREG(isar, ID_PFR0, 0x1031); 361 SET_IDREG(isar, ID_PFR1, 0x11); 362 SET_IDREG(isar, ID_DFR0, 0x400); 363 SET_IDREG(isar, ID_AFR0, 0); 364 SET_IDREG(isar, ID_MMFR0, 0x31100003); 365 SET_IDREG(isar, ID_MMFR1, 0x20000000); 366 SET_IDREG(isar, ID_MMFR2, 0x01202000); 367 SET_IDREG(isar, ID_MMFR3, 0x11); 368 SET_IDREG(isar, ID_ISAR0, 0x00101111); 369 SET_IDREG(isar, ID_ISAR1, 0x12112111); 370 SET_IDREG(isar, ID_ISAR2, 0x21232031); 371 SET_IDREG(isar, ID_ISAR3, 0x11112131); 372 SET_IDREG(isar, ID_ISAR4, 0x00111142); 373 cpu->isar.dbgdidr = 0x15141000; 374 SET_IDREG(isar, CLIDR, (1 << 27) | (2 << 24) | 3); 375 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 376 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 377 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 378 cpu->reset_auxcr = 2; 379 cpu->isar.reset_pmcr_el0 = 0x41002000; 380 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 381 } 382 383 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 384 /* 385 * power_control should be set to maximum latency. Again, 386 * default to 0 and set by private hook 387 */ 388 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 389 .access = PL1_RW, .resetvalue = 0, 390 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 391 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 392 .access = PL1_RW, .resetvalue = 0, 393 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 394 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 395 .access = PL1_RW, .resetvalue = 0, 396 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 397 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 398 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 399 /* TLB lockdown control */ 400 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 401 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 402 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 403 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 404 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 405 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 406 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 407 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 408 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 409 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 410 }; 411 412 static void cortex_a9_initfn(Object *obj) 413 { 414 ARMCPU *cpu = ARM_CPU(obj); 415 ARMISARegisters *isar = &cpu->isar; 416 417 cpu->dtb_compatible = "arm,cortex-a9"; 418 set_feature(&cpu->env, ARM_FEATURE_V7); 419 set_feature(&cpu->env, ARM_FEATURE_NEON); 420 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 421 set_feature(&cpu->env, ARM_FEATURE_EL3); 422 set_feature(&cpu->env, ARM_FEATURE_PMU); 423 /* 424 * Note that A9 supports the MP extensions even for 425 * A9UP and single-core A9MP (which are both different 426 * and valid configurations; we don't model A9UP). 427 */ 428 set_feature(&cpu->env, ARM_FEATURE_V7MP); 429 set_feature(&cpu->env, ARM_FEATURE_CBAR); 430 cpu->midr = 0x410fc090; 431 cpu->reset_fpsid = 0x41033090; 432 cpu->isar.mvfr0 = 0x11110222; 433 cpu->isar.mvfr1 = 0x01111111; 434 cpu->ctr = 0x80038003; 435 cpu->reset_sctlr = 0x00c50078; 436 SET_IDREG(isar, ID_PFR0, 0x1031); 437 SET_IDREG(isar, ID_PFR1, 0x11); 438 SET_IDREG(isar, ID_DFR0, 0x000); 439 SET_IDREG(isar, ID_AFR0, 0); 440 SET_IDREG(isar, ID_MMFR0, 0x00100103); 441 SET_IDREG(isar, ID_MMFR1, 0x20000000); 442 SET_IDREG(isar, ID_MMFR2, 0x01230000); 443 SET_IDREG(isar, ID_MMFR3, 0x00002111); 444 SET_IDREG(isar, ID_ISAR0, 0x00101111); 445 SET_IDREG(isar, ID_ISAR1, 0x13112111); 446 SET_IDREG(isar, ID_ISAR2, 0x21232041); 447 SET_IDREG(isar, ID_ISAR3, 0x11112131); 448 SET_IDREG(isar, ID_ISAR4, 0x00111142); 449 cpu->isar.dbgdidr = 0x35141000; 450 SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 3); 451 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 452 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 453 cpu->isar.reset_pmcr_el0 = 0x41093000; 454 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 455 } 456 457 #ifndef CONFIG_USER_ONLY 458 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 459 { 460 MachineState *ms = MACHINE(qdev_get_machine()); 461 462 /* 463 * Linux wants the number of processors from here. 464 * Might as well set the interrupt-controller bit too. 465 */ 466 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 467 } 468 #endif 469 470 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 471 #ifndef CONFIG_USER_ONLY 472 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 473 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 474 .writefn = arm_cp_write_ignore, }, 475 #endif 476 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 477 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 478 }; 479 480 static void cortex_a7_initfn(Object *obj) 481 { 482 ARMCPU *cpu = ARM_CPU(obj); 483 ARMISARegisters *isar = &cpu->isar; 484 485 cpu->dtb_compatible = "arm,cortex-a7"; 486 set_feature(&cpu->env, ARM_FEATURE_V7VE); 487 set_feature(&cpu->env, ARM_FEATURE_NEON); 488 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 489 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 490 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 491 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 492 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 493 set_feature(&cpu->env, ARM_FEATURE_EL2); 494 set_feature(&cpu->env, ARM_FEATURE_EL3); 495 set_feature(&cpu->env, ARM_FEATURE_PMU); 496 cpu->midr = 0x410fc075; 497 cpu->reset_fpsid = 0x41023075; 498 cpu->isar.mvfr0 = 0x10110222; 499 cpu->isar.mvfr1 = 0x11111111; 500 cpu->ctr = 0x84448003; 501 cpu->reset_sctlr = 0x00c50078; 502 SET_IDREG(isar, ID_PFR0, 0x00001131); 503 SET_IDREG(isar, ID_PFR1, 0x00011011); 504 SET_IDREG(isar, ID_DFR0, 0x02010555); 505 SET_IDREG(isar, ID_AFR0, 0x00000000); 506 SET_IDREG(isar, ID_MMFR0, 0x10101105); 507 SET_IDREG(isar, ID_MMFR1, 0x40000000); 508 SET_IDREG(isar, ID_MMFR2, 0x01240000); 509 SET_IDREG(isar, ID_MMFR3, 0x02102211); 510 /* 511 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 512 * table 4-41 gives 0x02101110, which includes the arm div insns. 513 */ 514 SET_IDREG(isar, ID_ISAR0, 0x02101110); 515 SET_IDREG(isar, ID_ISAR1, 0x13112111); 516 SET_IDREG(isar, ID_ISAR2, 0x21232041); 517 SET_IDREG(isar, ID_ISAR3, 0x11112131); 518 SET_IDREG(isar, ID_ISAR4, 0x10011142); 519 cpu->isar.dbgdidr = 0x3515f005; 520 cpu->isar.dbgdevid = 0x01110f13; 521 cpu->isar.dbgdevid1 = 0x1; 522 SET_IDREG(isar, CLIDR, 0x0a200023); 523 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 524 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 525 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 526 cpu->isar.reset_pmcr_el0 = 0x41072000; 527 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 528 } 529 530 static void cortex_a15_initfn(Object *obj) 531 { 532 ARMCPU *cpu = ARM_CPU(obj); 533 ARMISARegisters *isar = &cpu->isar; 534 535 cpu->dtb_compatible = "arm,cortex-a15"; 536 set_feature(&cpu->env, ARM_FEATURE_V7VE); 537 set_feature(&cpu->env, ARM_FEATURE_NEON); 538 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 539 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 540 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 541 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 542 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 543 set_feature(&cpu->env, ARM_FEATURE_EL2); 544 set_feature(&cpu->env, ARM_FEATURE_EL3); 545 set_feature(&cpu->env, ARM_FEATURE_PMU); 546 /* r4p0 cpu, not requiring expensive tlb flush errata */ 547 cpu->midr = 0x414fc0f0; 548 cpu->revidr = 0x0; 549 cpu->reset_fpsid = 0x410430f0; 550 cpu->isar.mvfr0 = 0x10110222; 551 cpu->isar.mvfr1 = 0x11111111; 552 cpu->ctr = 0x8444c004; 553 cpu->reset_sctlr = 0x00c50078; 554 SET_IDREG(isar, ID_PFR0, 0x00001131); 555 SET_IDREG(isar, ID_PFR1, 0x00011011); 556 SET_IDREG(isar, ID_DFR0, 0x02010555); 557 SET_IDREG(isar, ID_AFR0, 0x00000000); 558 SET_IDREG(isar, ID_MMFR0, 0x10201105); 559 SET_IDREG(isar, ID_MMFR1, 0x20000000); 560 SET_IDREG(isar, ID_MMFR2, 0x01240000); 561 SET_IDREG(isar, ID_MMFR3, 0x02102211); 562 SET_IDREG(isar, ID_ISAR0, 0x02101110); 563 SET_IDREG(isar, ID_ISAR1, 0x13112111); 564 SET_IDREG(isar, ID_ISAR2, 0x21232041); 565 SET_IDREG(isar, ID_ISAR3, 0x11112131); 566 SET_IDREG(isar, ID_ISAR4, 0x10011142); 567 cpu->isar.dbgdidr = 0x3515f021; 568 cpu->isar.dbgdevid = 0x01110f13; 569 cpu->isar.dbgdevid1 = 0x0; 570 SET_IDREG(isar, CLIDR, 0x0a200023); 571 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 572 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 573 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 574 cpu->isar.reset_pmcr_el0 = 0x410F3000; 575 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 576 } 577 578 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 579 /* Dummy the TCM region regs for the moment */ 580 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 581 .access = PL1_RW, .type = ARM_CP_CONST }, 582 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 583 .access = PL1_RW, .type = ARM_CP_CONST }, 584 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 585 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 586 }; 587 588 static void cortex_r5_initfn(Object *obj) 589 { 590 ARMCPU *cpu = ARM_CPU(obj); 591 ARMISARegisters *isar = &cpu->isar; 592 593 set_feature(&cpu->env, ARM_FEATURE_V7); 594 set_feature(&cpu->env, ARM_FEATURE_V7MP); 595 set_feature(&cpu->env, ARM_FEATURE_PMSA); 596 set_feature(&cpu->env, ARM_FEATURE_PMU); 597 cpu->midr = 0x411fc153; /* r1p3 */ 598 SET_IDREG(isar, ID_PFR0, 0x0131); 599 SET_IDREG(isar, ID_PFR1, 0x001); 600 SET_IDREG(isar, ID_DFR0, 0x010400); 601 SET_IDREG(isar, ID_AFR0, 0x0); 602 SET_IDREG(isar, ID_MMFR0, 0x0210030); 603 SET_IDREG(isar, ID_MMFR1, 0x00000000); 604 SET_IDREG(isar, ID_MMFR2, 0x01200000); 605 SET_IDREG(isar, ID_MMFR3, 0x0211); 606 SET_IDREG(isar, ID_ISAR0, 0x02101111); 607 SET_IDREG(isar, ID_ISAR1, 0x13112111); 608 SET_IDREG(isar, ID_ISAR2, 0x21232141); 609 SET_IDREG(isar, ID_ISAR3, 0x01112131); 610 SET_IDREG(isar, ID_ISAR4, 0x0010142); 611 SET_IDREG(isar, ID_ISAR5, 0x0); 612 SET_IDREG(isar, ID_ISAR6, 0x0); 613 cpu->mp_is_up = true; 614 cpu->pmsav7_dregion = 16; 615 cpu->isar.reset_pmcr_el0 = 0x41151800; 616 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 617 } 618 619 static const ARMCPRegInfo cortex_r52_cp_reginfo[] = { 620 { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15, 621 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 622 { .name = "IMP_ATCMREGIONR", 623 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 624 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 625 { .name = "IMP_BTCMREGIONR", 626 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 627 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 628 { .name = "IMP_CTCMREGIONR", 629 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2, 630 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 631 { .name = "IMP_CSCTLR", 632 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0, 633 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 634 { .name = "IMP_BPCTLR", 635 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1, 636 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 637 { .name = "IMP_MEMPROTCLR", 638 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2, 639 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 640 { .name = "IMP_SLAVEPCTLR", 641 .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0, 642 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 643 { .name = "IMP_PERIPHREGIONR", 644 .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, 645 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 646 { .name = "IMP_FLASHIFREGIONR", 647 .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1, 648 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 649 { .name = "IMP_BUILDOPTR", 650 .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, 651 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 652 { .name = "IMP_PINOPTR", 653 .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, 654 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 655 { .name = "IMP_QOSR", 656 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1, 657 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 658 { .name = "IMP_BUSTIMEOUTR", 659 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2, 660 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 661 { .name = "IMP_INTMONR", 662 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4, 663 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 664 { .name = "IMP_ICERR0", 665 .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0, 666 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 667 { .name = "IMP_ICERR1", 668 .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1, 669 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 670 { .name = "IMP_DCERR0", 671 .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0, 672 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 673 { .name = "IMP_DCERR1", 674 .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1, 675 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 676 { .name = "IMP_TCMERR0", 677 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0, 678 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 679 { .name = "IMP_TCMERR1", 680 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1, 681 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 682 { .name = "IMP_TCMSYNDR0", 683 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2, 684 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 685 { .name = "IMP_TCMSYNDR1", 686 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3, 687 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 688 { .name = "IMP_FLASHERR0", 689 .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0, 690 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 691 { .name = "IMP_FLASHERR1", 692 .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1, 693 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 694 { .name = "IMP_CDBGDR0", 695 .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0, 696 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 697 { .name = "IMP_CBDGBR1", 698 .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1, 699 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 700 { .name = "IMP_TESTR0", 701 .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0, 702 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 703 { .name = "IMP_TESTR1", 704 .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1, 705 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 706 { .name = "IMP_CDBGDCI", 707 .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0, 708 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 709 { .name = "IMP_CDBGDCT", 710 .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0, 711 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 712 { .name = "IMP_CDBGICT", 713 .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1, 714 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 715 { .name = "IMP_CDBGDCD", 716 .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0, 717 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 718 { .name = "IMP_CDBGICD", 719 .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1, 720 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 721 }; 722 723 724 static void cortex_r52_initfn(Object *obj) 725 { 726 ARMCPU *cpu = ARM_CPU(obj); 727 ARMISARegisters *isar = &cpu->isar; 728 729 set_feature(&cpu->env, ARM_FEATURE_V8); 730 set_feature(&cpu->env, ARM_FEATURE_EL2); 731 set_feature(&cpu->env, ARM_FEATURE_PMSA); 732 set_feature(&cpu->env, ARM_FEATURE_NEON); 733 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 734 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 735 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 736 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 737 cpu->midr = 0x411fd133; /* r1p3 */ 738 cpu->revidr = 0x00000000; 739 cpu->reset_fpsid = 0x41034023; 740 cpu->isar.mvfr0 = 0x10110222; 741 cpu->isar.mvfr1 = 0x12111111; 742 cpu->isar.mvfr2 = 0x00000043; 743 cpu->ctr = 0x8144c004; 744 cpu->reset_sctlr = 0x30c50838; 745 SET_IDREG(isar, ID_PFR0, 0x00000131); 746 SET_IDREG(isar, ID_PFR1, 0x10111001); 747 SET_IDREG(isar, ID_DFR0, 0x03010006); 748 SET_IDREG(isar, ID_AFR0, 0x00000000); 749 SET_IDREG(isar, ID_MMFR0, 0x00211040); 750 SET_IDREG(isar, ID_MMFR1, 0x40000000); 751 SET_IDREG(isar, ID_MMFR2, 0x01200000); 752 SET_IDREG(isar, ID_MMFR3, 0xf0102211); 753 SET_IDREG(isar, ID_MMFR4, 0x00000010); 754 SET_IDREG(isar, ID_ISAR0, 0x02101110); 755 SET_IDREG(isar, ID_ISAR1, 0x13112111); 756 SET_IDREG(isar, ID_ISAR2, 0x21232142); 757 SET_IDREG(isar, ID_ISAR3, 0x01112131); 758 SET_IDREG(isar, ID_ISAR4, 0x00010142); 759 SET_IDREG(isar, ID_ISAR5, 0x00010001); 760 cpu->isar.dbgdidr = 0x77168000; 761 SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 0x3); 762 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 763 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 764 765 cpu->pmsav7_dregion = 16; 766 cpu->pmsav8r_hdregion = 16; 767 768 define_arm_cp_regs(cpu, cortex_r52_cp_reginfo); 769 } 770 771 static void cortex_r5f_initfn(Object *obj) 772 { 773 ARMCPU *cpu = ARM_CPU(obj); 774 775 cortex_r5_initfn(obj); 776 cpu->isar.mvfr0 = 0x10110221; 777 cpu->isar.mvfr1 = 0x00000011; 778 } 779 780 static void ti925t_initfn(Object *obj) 781 { 782 ARMCPU *cpu = ARM_CPU(obj); 783 set_feature(&cpu->env, ARM_FEATURE_V4T); 784 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 785 cpu->midr = ARM_CPUID_TI925T; 786 cpu->ctr = 0x5109149; 787 cpu->reset_sctlr = 0x00000070; 788 } 789 790 static void sa1100_initfn(Object *obj) 791 { 792 ARMCPU *cpu = ARM_CPU(obj); 793 794 cpu->dtb_compatible = "intel,sa1100"; 795 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 796 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 797 cpu->midr = 0x4401A11B; 798 cpu->reset_sctlr = 0x00000070; 799 } 800 801 static void sa1110_initfn(Object *obj) 802 { 803 ARMCPU *cpu = ARM_CPU(obj); 804 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 805 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 806 cpu->midr = 0x6901B119; 807 cpu->reset_sctlr = 0x00000070; 808 } 809 810 static void pxa250_initfn(Object *obj) 811 { 812 ARMCPU *cpu = ARM_CPU(obj); 813 814 cpu->dtb_compatible = "marvell,xscale"; 815 set_feature(&cpu->env, ARM_FEATURE_V5); 816 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 817 cpu->midr = 0x69052100; 818 cpu->ctr = 0xd172172; 819 cpu->reset_sctlr = 0x00000078; 820 } 821 822 static void pxa255_initfn(Object *obj) 823 { 824 ARMCPU *cpu = ARM_CPU(obj); 825 826 cpu->dtb_compatible = "marvell,xscale"; 827 set_feature(&cpu->env, ARM_FEATURE_V5); 828 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 829 cpu->midr = 0x69052d00; 830 cpu->ctr = 0xd172172; 831 cpu->reset_sctlr = 0x00000078; 832 } 833 834 static void pxa260_initfn(Object *obj) 835 { 836 ARMCPU *cpu = ARM_CPU(obj); 837 838 cpu->dtb_compatible = "marvell,xscale"; 839 set_feature(&cpu->env, ARM_FEATURE_V5); 840 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 841 cpu->midr = 0x69052903; 842 cpu->ctr = 0xd172172; 843 cpu->reset_sctlr = 0x00000078; 844 } 845 846 static void pxa261_initfn(Object *obj) 847 { 848 ARMCPU *cpu = ARM_CPU(obj); 849 850 cpu->dtb_compatible = "marvell,xscale"; 851 set_feature(&cpu->env, ARM_FEATURE_V5); 852 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 853 cpu->midr = 0x69052d05; 854 cpu->ctr = 0xd172172; 855 cpu->reset_sctlr = 0x00000078; 856 } 857 858 static void pxa262_initfn(Object *obj) 859 { 860 ARMCPU *cpu = ARM_CPU(obj); 861 862 cpu->dtb_compatible = "marvell,xscale"; 863 set_feature(&cpu->env, ARM_FEATURE_V5); 864 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 865 cpu->midr = 0x69052d06; 866 cpu->ctr = 0xd172172; 867 cpu->reset_sctlr = 0x00000078; 868 } 869 870 static void pxa270a0_initfn(Object *obj) 871 { 872 ARMCPU *cpu = ARM_CPU(obj); 873 874 cpu->dtb_compatible = "marvell,xscale"; 875 set_feature(&cpu->env, ARM_FEATURE_V5); 876 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 877 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 878 cpu->midr = 0x69054110; 879 cpu->ctr = 0xd172172; 880 cpu->reset_sctlr = 0x00000078; 881 } 882 883 static void pxa270a1_initfn(Object *obj) 884 { 885 ARMCPU *cpu = ARM_CPU(obj); 886 887 cpu->dtb_compatible = "marvell,xscale"; 888 set_feature(&cpu->env, ARM_FEATURE_V5); 889 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 890 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 891 cpu->midr = 0x69054111; 892 cpu->ctr = 0xd172172; 893 cpu->reset_sctlr = 0x00000078; 894 } 895 896 static void pxa270b0_initfn(Object *obj) 897 { 898 ARMCPU *cpu = ARM_CPU(obj); 899 900 cpu->dtb_compatible = "marvell,xscale"; 901 set_feature(&cpu->env, ARM_FEATURE_V5); 902 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 903 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 904 cpu->midr = 0x69054112; 905 cpu->ctr = 0xd172172; 906 cpu->reset_sctlr = 0x00000078; 907 } 908 909 static void pxa270b1_initfn(Object *obj) 910 { 911 ARMCPU *cpu = ARM_CPU(obj); 912 913 cpu->dtb_compatible = "marvell,xscale"; 914 set_feature(&cpu->env, ARM_FEATURE_V5); 915 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 916 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 917 cpu->midr = 0x69054113; 918 cpu->ctr = 0xd172172; 919 cpu->reset_sctlr = 0x00000078; 920 } 921 922 static void pxa270c0_initfn(Object *obj) 923 { 924 ARMCPU *cpu = ARM_CPU(obj); 925 926 cpu->dtb_compatible = "marvell,xscale"; 927 set_feature(&cpu->env, ARM_FEATURE_V5); 928 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 929 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 930 cpu->midr = 0x69054114; 931 cpu->ctr = 0xd172172; 932 cpu->reset_sctlr = 0x00000078; 933 } 934 935 static void pxa270c5_initfn(Object *obj) 936 { 937 ARMCPU *cpu = ARM_CPU(obj); 938 939 cpu->dtb_compatible = "marvell,xscale"; 940 set_feature(&cpu->env, ARM_FEATURE_V5); 941 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 942 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 943 cpu->midr = 0x69054117; 944 cpu->ctr = 0xd172172; 945 cpu->reset_sctlr = 0x00000078; 946 } 947 948 #ifndef TARGET_AARCH64 949 /* 950 * -cpu max: a CPU with as many features enabled as our emulation supports. 951 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 952 * this only needs to handle 32 bits, and need not care about KVM. 953 */ 954 static void arm_max_initfn(Object *obj) 955 { 956 ARMCPU *cpu = ARM_CPU(obj); 957 ARMISARegisters *isar = &cpu->isar; 958 959 /* aarch64_a57_initfn, advertising none of the aarch64 features */ 960 cpu->dtb_compatible = "arm,cortex-a57"; 961 set_feature(&cpu->env, ARM_FEATURE_V8); 962 set_feature(&cpu->env, ARM_FEATURE_NEON); 963 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 964 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 965 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 966 set_feature(&cpu->env, ARM_FEATURE_EL2); 967 set_feature(&cpu->env, ARM_FEATURE_EL3); 968 set_feature(&cpu->env, ARM_FEATURE_PMU); 969 cpu->midr = 0x411fd070; 970 cpu->revidr = 0x00000000; 971 cpu->reset_fpsid = 0x41034070; 972 cpu->isar.mvfr0 = 0x10110222; 973 cpu->isar.mvfr1 = 0x12111111; 974 cpu->isar.mvfr2 = 0x00000043; 975 cpu->ctr = 0x8444c004; 976 cpu->reset_sctlr = 0x00c50838; 977 SET_IDREG(isar, ID_PFR0, 0x00000131); 978 SET_IDREG(isar, ID_PFR1, 0x00011011); 979 SET_IDREG(isar, ID_DFR0, 0x03010066); 980 SET_IDREG(isar, ID_AFR0, 0x00000000); 981 SET_IDREG(isar, ID_MMFR0, 0x10101105); 982 SET_IDREG(isar, ID_MMFR1, 0x40000000); 983 SET_IDREG(isar, ID_MMFR2, 0x01260000); 984 SET_IDREG(isar, ID_MMFR3, 0x02102211); 985 SET_IDREG(isar, ID_ISAR0, 0x02101110); 986 SET_IDREG(isar, ID_ISAR1, 0x13112111); 987 SET_IDREG(isar, ID_ISAR2, 0x21232042); 988 SET_IDREG(isar, ID_ISAR3, 0x01112131); 989 SET_IDREG(isar, ID_ISAR4, 0x00011142); 990 SET_IDREG(isar, ID_ISAR5, 0x00011121); 991 SET_IDREG(isar, ID_ISAR6, 0); 992 cpu->isar.reset_pmcr_el0 = 0x41013000; 993 SET_IDREG(isar, CLIDR, 0x0a200023); 994 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 995 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 996 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 997 define_cortex_a72_a57_a53_cp_reginfo(cpu); 998 999 aa32_max_features(cpu); 1000 1001 #ifdef CONFIG_USER_ONLY 1002 /* 1003 * Break with true ARMv8 and add back old-style VFP short-vector support. 1004 * Only do this for user-mode, where -cpu max is the default, so that 1005 * older v6 and v7 programs are more likely to work without adjustment. 1006 */ 1007 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1008 #endif 1009 } 1010 #endif /* !TARGET_AARCH64 */ 1011 1012 static const ARMCPUInfo arm_tcg_cpus[] = { 1013 { .name = "arm926", .initfn = arm926_initfn }, 1014 { .name = "arm946", .initfn = arm946_initfn }, 1015 { .name = "arm1026", .initfn = arm1026_initfn }, 1016 /* 1017 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1018 * older core than plain "arm1136". In particular this does not 1019 * have the v6K features. 1020 */ 1021 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1022 { .name = "arm1136", .initfn = arm1136_initfn }, 1023 { .name = "arm1176", .initfn = arm1176_initfn }, 1024 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1025 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1026 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1027 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1028 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1029 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1030 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 1031 { .name = "cortex-r52", .initfn = cortex_r52_initfn }, 1032 { .name = "ti925t", .initfn = ti925t_initfn }, 1033 { .name = "sa1100", .initfn = sa1100_initfn }, 1034 { .name = "sa1110", .initfn = sa1110_initfn }, 1035 { .name = "pxa250", .initfn = pxa250_initfn, 1036 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1037 { .name = "pxa255", .initfn = pxa255_initfn, 1038 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1039 { .name = "pxa260", .initfn = pxa260_initfn, 1040 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1041 { .name = "pxa261", .initfn = pxa261_initfn, 1042 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1043 { .name = "pxa262", .initfn = pxa262_initfn, 1044 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1045 /* "pxa270" is an alias for "pxa270-a0" */ 1046 { .name = "pxa270", .initfn = pxa270a0_initfn, 1047 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1048 { .name = "pxa270-a0", .initfn = pxa270a0_initfn, 1049 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1050 { .name = "pxa270-a1", .initfn = pxa270a1_initfn, 1051 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1052 { .name = "pxa270-b0", .initfn = pxa270b0_initfn, 1053 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1054 { .name = "pxa270-b1", .initfn = pxa270b1_initfn, 1055 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1056 { .name = "pxa270-c0", .initfn = pxa270c0_initfn, 1057 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1058 { .name = "pxa270-c5", .initfn = pxa270c5_initfn, 1059 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1060 #ifndef TARGET_AARCH64 1061 { .name = "max", .initfn = arm_max_initfn }, 1062 #endif 1063 #ifdef CONFIG_USER_ONLY 1064 { .name = "any", .initfn = arm_max_initfn }, 1065 #endif 1066 }; 1067 1068 static const TypeInfo idau_interface_type_info = { 1069 .name = TYPE_IDAU_INTERFACE, 1070 .parent = TYPE_INTERFACE, 1071 .class_size = sizeof(IDAUInterfaceClass), 1072 }; 1073 1074 static void arm_tcg_cpu_register_types(void) 1075 { 1076 size_t i; 1077 1078 type_register_static(&idau_interface_type_info); 1079 for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { 1080 arm_cpu_register(&arm_tcg_cpus[i]); 1081 } 1082 } 1083 1084 type_init(arm_tcg_cpu_register_types) 1085 1086 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ 1087