1 /* 2 * QEMU ARM TCG-only CPUs. 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This code is licensed under the GNU GPL v2 or later. 7 * 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 11 #include "qemu/osdep.h" 12 #include "cpu.h" 13 #include "hw/core/tcg-cpu-ops.h" 14 #include "internals.h" 15 #include "target/arm/idau.h" 16 #if !defined(CONFIG_USER_ONLY) 17 #include "hw/boards.h" 18 #endif 19 #include "cpregs.h" 20 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 21 #include "hw/intc/armv7m_nvic.h" 22 #endif 23 24 25 /* Share AArch32 -cpu max features with AArch64. */ 26 void aa32_max_features(ARMCPU *cpu) 27 { 28 uint32_t t; 29 30 /* Add additional features supported by QEMU */ 31 t = cpu->isar.id_isar5; 32 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ 33 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ 34 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ 35 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 36 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ 37 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ 38 cpu->isar.id_isar5 = t; 39 40 t = cpu->isar.id_isar6; 41 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ 42 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ 43 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ 44 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ 45 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ 46 t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ 47 t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ 48 cpu->isar.id_isar6 = t; 49 50 t = cpu->isar.mvfr1; 51 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ 52 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ 53 cpu->isar.mvfr1 = t; 54 55 t = cpu->isar.mvfr2; 56 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 57 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 58 cpu->isar.mvfr2 = t; 59 60 t = cpu->isar.id_mmfr3; 61 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ 62 cpu->isar.id_mmfr3 = t; 63 64 t = cpu->isar.id_mmfr4; 65 t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ 66 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 67 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ 68 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ 69 t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ 70 cpu->isar.id_mmfr4 = t; 71 72 t = cpu->isar.id_mmfr5; 73 t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */ 74 cpu->isar.id_mmfr5 = t; 75 76 t = cpu->isar.id_pfr0; 77 t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ 78 t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ 79 t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ 80 cpu->isar.id_pfr0 = t; 81 82 t = cpu->isar.id_pfr2; 83 t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ 84 t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ 85 cpu->isar.id_pfr2 = t; 86 87 t = cpu->isar.id_dfr0; 88 t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ 89 t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ 90 t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ 91 cpu->isar.id_dfr0 = t; 92 93 t = cpu->isar.id_dfr1; 94 t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ 95 cpu->isar.id_dfr1 = t; 96 } 97 98 /* CPU models. These are not needed for the AArch64 linux-user build. */ 99 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 100 101 #if !defined(CONFIG_USER_ONLY) 102 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 103 { 104 CPUClass *cc = CPU_GET_CLASS(cs); 105 ARMCPU *cpu = ARM_CPU(cs); 106 CPUARMState *env = &cpu->env; 107 bool ret = false; 108 109 /* 110 * ARMv7-M interrupt masking works differently than -A or -R. 111 * There is no FIQ/IRQ distinction. Instead of I and F bits 112 * masking FIQ and IRQ interrupts, an exception is taken only 113 * if it is higher priority than the current execution priority 114 * (which depends on state like BASEPRI, FAULTMASK and the 115 * currently active exception). 116 */ 117 if (interrupt_request & CPU_INTERRUPT_HARD 118 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 119 cs->exception_index = EXCP_IRQ; 120 cc->tcg_ops->do_interrupt(cs); 121 ret = true; 122 } 123 return ret; 124 } 125 #endif /* !CONFIG_USER_ONLY */ 126 127 static void arm926_initfn(Object *obj) 128 { 129 ARMCPU *cpu = ARM_CPU(obj); 130 131 cpu->dtb_compatible = "arm,arm926"; 132 set_feature(&cpu->env, ARM_FEATURE_V5); 133 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 134 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 135 cpu->midr = 0x41069265; 136 cpu->reset_fpsid = 0x41011090; 137 cpu->ctr = 0x1dd20d2; 138 cpu->reset_sctlr = 0x00090078; 139 140 /* 141 * ARMv5 does not have the ID_ISAR registers, but we can still 142 * set the field to indicate Jazelle support within QEMU. 143 */ 144 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 145 /* 146 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 147 * support even though ARMv5 doesn't have this register. 148 */ 149 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 150 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 151 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 152 } 153 154 static void arm946_initfn(Object *obj) 155 { 156 ARMCPU *cpu = ARM_CPU(obj); 157 158 cpu->dtb_compatible = "arm,arm946"; 159 set_feature(&cpu->env, ARM_FEATURE_V5); 160 set_feature(&cpu->env, ARM_FEATURE_PMSA); 161 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 162 cpu->midr = 0x41059461; 163 cpu->ctr = 0x0f004006; 164 cpu->reset_sctlr = 0x00000078; 165 } 166 167 static void arm1026_initfn(Object *obj) 168 { 169 ARMCPU *cpu = ARM_CPU(obj); 170 171 cpu->dtb_compatible = "arm,arm1026"; 172 set_feature(&cpu->env, ARM_FEATURE_V5); 173 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 174 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 175 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 176 cpu->midr = 0x4106a262; 177 cpu->reset_fpsid = 0x410110a0; 178 cpu->ctr = 0x1dd20d2; 179 cpu->reset_sctlr = 0x00090078; 180 cpu->reset_auxcr = 1; 181 182 /* 183 * ARMv5 does not have the ID_ISAR registers, but we can still 184 * set the field to indicate Jazelle support within QEMU. 185 */ 186 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 187 /* 188 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 189 * support even though ARMv5 doesn't have this register. 190 */ 191 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 192 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 193 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 194 195 { 196 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 197 ARMCPRegInfo ifar = { 198 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 199 .access = PL1_RW, 200 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 201 .resetvalue = 0 202 }; 203 define_one_arm_cp_reg(cpu, &ifar); 204 } 205 } 206 207 static void arm1136_r2_initfn(Object *obj) 208 { 209 ARMCPU *cpu = ARM_CPU(obj); 210 /* 211 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 212 * older core than plain "arm1136". In particular this does not 213 * have the v6K features. 214 * These ID register values are correct for 1136 but may be wrong 215 * for 1136_r2 (in particular r0p2 does not actually implement most 216 * of the ID registers). 217 */ 218 219 cpu->dtb_compatible = "arm,arm1136"; 220 set_feature(&cpu->env, ARM_FEATURE_V6); 221 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 222 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 223 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 224 cpu->midr = 0x4107b362; 225 cpu->reset_fpsid = 0x410120b4; 226 cpu->isar.mvfr0 = 0x11111111; 227 cpu->isar.mvfr1 = 0x00000000; 228 cpu->ctr = 0x1dd20d2; 229 cpu->reset_sctlr = 0x00050078; 230 cpu->isar.id_pfr0 = 0x111; 231 cpu->isar.id_pfr1 = 0x1; 232 cpu->isar.id_dfr0 = 0x2; 233 cpu->id_afr0 = 0x3; 234 cpu->isar.id_mmfr0 = 0x01130003; 235 cpu->isar.id_mmfr1 = 0x10030302; 236 cpu->isar.id_mmfr2 = 0x01222110; 237 cpu->isar.id_isar0 = 0x00140011; 238 cpu->isar.id_isar1 = 0x12002111; 239 cpu->isar.id_isar2 = 0x11231111; 240 cpu->isar.id_isar3 = 0x01102131; 241 cpu->isar.id_isar4 = 0x141; 242 cpu->reset_auxcr = 7; 243 } 244 245 static void arm1136_initfn(Object *obj) 246 { 247 ARMCPU *cpu = ARM_CPU(obj); 248 249 cpu->dtb_compatible = "arm,arm1136"; 250 set_feature(&cpu->env, ARM_FEATURE_V6K); 251 set_feature(&cpu->env, ARM_FEATURE_V6); 252 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 253 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 254 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 255 cpu->midr = 0x4117b363; 256 cpu->reset_fpsid = 0x410120b4; 257 cpu->isar.mvfr0 = 0x11111111; 258 cpu->isar.mvfr1 = 0x00000000; 259 cpu->ctr = 0x1dd20d2; 260 cpu->reset_sctlr = 0x00050078; 261 cpu->isar.id_pfr0 = 0x111; 262 cpu->isar.id_pfr1 = 0x1; 263 cpu->isar.id_dfr0 = 0x2; 264 cpu->id_afr0 = 0x3; 265 cpu->isar.id_mmfr0 = 0x01130003; 266 cpu->isar.id_mmfr1 = 0x10030302; 267 cpu->isar.id_mmfr2 = 0x01222110; 268 cpu->isar.id_isar0 = 0x00140011; 269 cpu->isar.id_isar1 = 0x12002111; 270 cpu->isar.id_isar2 = 0x11231111; 271 cpu->isar.id_isar3 = 0x01102131; 272 cpu->isar.id_isar4 = 0x141; 273 cpu->reset_auxcr = 7; 274 } 275 276 static void arm1176_initfn(Object *obj) 277 { 278 ARMCPU *cpu = ARM_CPU(obj); 279 280 cpu->dtb_compatible = "arm,arm1176"; 281 set_feature(&cpu->env, ARM_FEATURE_V6K); 282 set_feature(&cpu->env, ARM_FEATURE_VAPA); 283 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 284 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 285 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 286 set_feature(&cpu->env, ARM_FEATURE_EL3); 287 cpu->midr = 0x410fb767; 288 cpu->reset_fpsid = 0x410120b5; 289 cpu->isar.mvfr0 = 0x11111111; 290 cpu->isar.mvfr1 = 0x00000000; 291 cpu->ctr = 0x1dd20d2; 292 cpu->reset_sctlr = 0x00050078; 293 cpu->isar.id_pfr0 = 0x111; 294 cpu->isar.id_pfr1 = 0x11; 295 cpu->isar.id_dfr0 = 0x33; 296 cpu->id_afr0 = 0; 297 cpu->isar.id_mmfr0 = 0x01130003; 298 cpu->isar.id_mmfr1 = 0x10030302; 299 cpu->isar.id_mmfr2 = 0x01222100; 300 cpu->isar.id_isar0 = 0x0140011; 301 cpu->isar.id_isar1 = 0x12002111; 302 cpu->isar.id_isar2 = 0x11231121; 303 cpu->isar.id_isar3 = 0x01102131; 304 cpu->isar.id_isar4 = 0x01141; 305 cpu->reset_auxcr = 7; 306 } 307 308 static void arm11mpcore_initfn(Object *obj) 309 { 310 ARMCPU *cpu = ARM_CPU(obj); 311 312 cpu->dtb_compatible = "arm,arm11mpcore"; 313 set_feature(&cpu->env, ARM_FEATURE_V6K); 314 set_feature(&cpu->env, ARM_FEATURE_VAPA); 315 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 316 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 317 cpu->midr = 0x410fb022; 318 cpu->reset_fpsid = 0x410120b4; 319 cpu->isar.mvfr0 = 0x11111111; 320 cpu->isar.mvfr1 = 0x00000000; 321 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 322 cpu->isar.id_pfr0 = 0x111; 323 cpu->isar.id_pfr1 = 0x1; 324 cpu->isar.id_dfr0 = 0; 325 cpu->id_afr0 = 0x2; 326 cpu->isar.id_mmfr0 = 0x01100103; 327 cpu->isar.id_mmfr1 = 0x10020302; 328 cpu->isar.id_mmfr2 = 0x01222000; 329 cpu->isar.id_isar0 = 0x00100011; 330 cpu->isar.id_isar1 = 0x12002111; 331 cpu->isar.id_isar2 = 0x11221011; 332 cpu->isar.id_isar3 = 0x01102131; 333 cpu->isar.id_isar4 = 0x141; 334 cpu->reset_auxcr = 1; 335 } 336 337 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 338 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 339 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 340 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 341 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 342 }; 343 344 static void cortex_a8_initfn(Object *obj) 345 { 346 ARMCPU *cpu = ARM_CPU(obj); 347 348 cpu->dtb_compatible = "arm,cortex-a8"; 349 set_feature(&cpu->env, ARM_FEATURE_V7); 350 set_feature(&cpu->env, ARM_FEATURE_NEON); 351 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 352 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 353 set_feature(&cpu->env, ARM_FEATURE_EL3); 354 set_feature(&cpu->env, ARM_FEATURE_PMU); 355 cpu->midr = 0x410fc080; 356 cpu->reset_fpsid = 0x410330c0; 357 cpu->isar.mvfr0 = 0x11110222; 358 cpu->isar.mvfr1 = 0x00011111; 359 cpu->ctr = 0x82048004; 360 cpu->reset_sctlr = 0x00c50078; 361 cpu->isar.id_pfr0 = 0x1031; 362 cpu->isar.id_pfr1 = 0x11; 363 cpu->isar.id_dfr0 = 0x400; 364 cpu->id_afr0 = 0; 365 cpu->isar.id_mmfr0 = 0x31100003; 366 cpu->isar.id_mmfr1 = 0x20000000; 367 cpu->isar.id_mmfr2 = 0x01202000; 368 cpu->isar.id_mmfr3 = 0x11; 369 cpu->isar.id_isar0 = 0x00101111; 370 cpu->isar.id_isar1 = 0x12112111; 371 cpu->isar.id_isar2 = 0x21232031; 372 cpu->isar.id_isar3 = 0x11112131; 373 cpu->isar.id_isar4 = 0x00111142; 374 cpu->isar.dbgdidr = 0x15141000; 375 cpu->clidr = (1 << 27) | (2 << 24) | 3; 376 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 377 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 378 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 379 cpu->reset_auxcr = 2; 380 cpu->isar.reset_pmcr_el0 = 0x41002000; 381 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 382 } 383 384 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 385 /* 386 * power_control should be set to maximum latency. Again, 387 * default to 0 and set by private hook 388 */ 389 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 390 .access = PL1_RW, .resetvalue = 0, 391 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 392 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 393 .access = PL1_RW, .resetvalue = 0, 394 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 395 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 396 .access = PL1_RW, .resetvalue = 0, 397 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 398 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 399 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 400 /* TLB lockdown control */ 401 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 402 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 403 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 404 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 405 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 406 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 407 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 408 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 409 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 410 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 411 }; 412 413 static void cortex_a9_initfn(Object *obj) 414 { 415 ARMCPU *cpu = ARM_CPU(obj); 416 417 cpu->dtb_compatible = "arm,cortex-a9"; 418 set_feature(&cpu->env, ARM_FEATURE_V7); 419 set_feature(&cpu->env, ARM_FEATURE_NEON); 420 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 421 set_feature(&cpu->env, ARM_FEATURE_EL3); 422 set_feature(&cpu->env, ARM_FEATURE_PMU); 423 /* 424 * Note that A9 supports the MP extensions even for 425 * A9UP and single-core A9MP (which are both different 426 * and valid configurations; we don't model A9UP). 427 */ 428 set_feature(&cpu->env, ARM_FEATURE_V7MP); 429 set_feature(&cpu->env, ARM_FEATURE_CBAR); 430 cpu->midr = 0x410fc090; 431 cpu->reset_fpsid = 0x41033090; 432 cpu->isar.mvfr0 = 0x11110222; 433 cpu->isar.mvfr1 = 0x01111111; 434 cpu->ctr = 0x80038003; 435 cpu->reset_sctlr = 0x00c50078; 436 cpu->isar.id_pfr0 = 0x1031; 437 cpu->isar.id_pfr1 = 0x11; 438 cpu->isar.id_dfr0 = 0x000; 439 cpu->id_afr0 = 0; 440 cpu->isar.id_mmfr0 = 0x00100103; 441 cpu->isar.id_mmfr1 = 0x20000000; 442 cpu->isar.id_mmfr2 = 0x01230000; 443 cpu->isar.id_mmfr3 = 0x00002111; 444 cpu->isar.id_isar0 = 0x00101111; 445 cpu->isar.id_isar1 = 0x13112111; 446 cpu->isar.id_isar2 = 0x21232041; 447 cpu->isar.id_isar3 = 0x11112131; 448 cpu->isar.id_isar4 = 0x00111142; 449 cpu->isar.dbgdidr = 0x35141000; 450 cpu->clidr = (1 << 27) | (1 << 24) | 3; 451 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 452 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 453 cpu->isar.reset_pmcr_el0 = 0x41093000; 454 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 455 } 456 457 #ifndef CONFIG_USER_ONLY 458 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 459 { 460 MachineState *ms = MACHINE(qdev_get_machine()); 461 462 /* 463 * Linux wants the number of processors from here. 464 * Might as well set the interrupt-controller bit too. 465 */ 466 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 467 } 468 #endif 469 470 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 471 #ifndef CONFIG_USER_ONLY 472 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 473 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 474 .writefn = arm_cp_write_ignore, }, 475 #endif 476 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 477 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 478 }; 479 480 static void cortex_a7_initfn(Object *obj) 481 { 482 ARMCPU *cpu = ARM_CPU(obj); 483 484 cpu->dtb_compatible = "arm,cortex-a7"; 485 set_feature(&cpu->env, ARM_FEATURE_V7VE); 486 set_feature(&cpu->env, ARM_FEATURE_NEON); 487 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 488 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 489 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 490 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 491 set_feature(&cpu->env, ARM_FEATURE_EL2); 492 set_feature(&cpu->env, ARM_FEATURE_EL3); 493 set_feature(&cpu->env, ARM_FEATURE_PMU); 494 cpu->midr = 0x410fc075; 495 cpu->reset_fpsid = 0x41023075; 496 cpu->isar.mvfr0 = 0x10110222; 497 cpu->isar.mvfr1 = 0x11111111; 498 cpu->ctr = 0x84448003; 499 cpu->reset_sctlr = 0x00c50078; 500 cpu->isar.id_pfr0 = 0x00001131; 501 cpu->isar.id_pfr1 = 0x00011011; 502 cpu->isar.id_dfr0 = 0x02010555; 503 cpu->id_afr0 = 0x00000000; 504 cpu->isar.id_mmfr0 = 0x10101105; 505 cpu->isar.id_mmfr1 = 0x40000000; 506 cpu->isar.id_mmfr2 = 0x01240000; 507 cpu->isar.id_mmfr3 = 0x02102211; 508 /* 509 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 510 * table 4-41 gives 0x02101110, which includes the arm div insns. 511 */ 512 cpu->isar.id_isar0 = 0x02101110; 513 cpu->isar.id_isar1 = 0x13112111; 514 cpu->isar.id_isar2 = 0x21232041; 515 cpu->isar.id_isar3 = 0x11112131; 516 cpu->isar.id_isar4 = 0x10011142; 517 cpu->isar.dbgdidr = 0x3515f005; 518 cpu->isar.dbgdevid = 0x01110f13; 519 cpu->isar.dbgdevid1 = 0x1; 520 cpu->clidr = 0x0a200023; 521 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 522 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 523 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 524 cpu->isar.reset_pmcr_el0 = 0x41072000; 525 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 526 } 527 528 static void cortex_a15_initfn(Object *obj) 529 { 530 ARMCPU *cpu = ARM_CPU(obj); 531 532 cpu->dtb_compatible = "arm,cortex-a15"; 533 set_feature(&cpu->env, ARM_FEATURE_V7VE); 534 set_feature(&cpu->env, ARM_FEATURE_NEON); 535 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 536 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 537 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 538 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 539 set_feature(&cpu->env, ARM_FEATURE_EL2); 540 set_feature(&cpu->env, ARM_FEATURE_EL3); 541 set_feature(&cpu->env, ARM_FEATURE_PMU); 542 /* r4p0 cpu, not requiring expensive tlb flush errata */ 543 cpu->midr = 0x414fc0f0; 544 cpu->revidr = 0x0; 545 cpu->reset_fpsid = 0x410430f0; 546 cpu->isar.mvfr0 = 0x10110222; 547 cpu->isar.mvfr1 = 0x11111111; 548 cpu->ctr = 0x8444c004; 549 cpu->reset_sctlr = 0x00c50078; 550 cpu->isar.id_pfr0 = 0x00001131; 551 cpu->isar.id_pfr1 = 0x00011011; 552 cpu->isar.id_dfr0 = 0x02010555; 553 cpu->id_afr0 = 0x00000000; 554 cpu->isar.id_mmfr0 = 0x10201105; 555 cpu->isar.id_mmfr1 = 0x20000000; 556 cpu->isar.id_mmfr2 = 0x01240000; 557 cpu->isar.id_mmfr3 = 0x02102211; 558 cpu->isar.id_isar0 = 0x02101110; 559 cpu->isar.id_isar1 = 0x13112111; 560 cpu->isar.id_isar2 = 0x21232041; 561 cpu->isar.id_isar3 = 0x11112131; 562 cpu->isar.id_isar4 = 0x10011142; 563 cpu->isar.dbgdidr = 0x3515f021; 564 cpu->isar.dbgdevid = 0x01110f13; 565 cpu->isar.dbgdevid1 = 0x0; 566 cpu->clidr = 0x0a200023; 567 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 568 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 569 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 570 cpu->isar.reset_pmcr_el0 = 0x410F3000; 571 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 572 } 573 574 static void cortex_m0_initfn(Object *obj) 575 { 576 ARMCPU *cpu = ARM_CPU(obj); 577 set_feature(&cpu->env, ARM_FEATURE_V6); 578 set_feature(&cpu->env, ARM_FEATURE_M); 579 580 cpu->midr = 0x410cc200; 581 582 /* 583 * These ID register values are not guest visible, because 584 * we do not implement the Main Extension. They must be set 585 * to values corresponding to the Cortex-M0's implemented 586 * features, because QEMU generally controls its emulation 587 * by looking at ID register fields. We use the same values as 588 * for the M3. 589 */ 590 cpu->isar.id_pfr0 = 0x00000030; 591 cpu->isar.id_pfr1 = 0x00000200; 592 cpu->isar.id_dfr0 = 0x00100000; 593 cpu->id_afr0 = 0x00000000; 594 cpu->isar.id_mmfr0 = 0x00000030; 595 cpu->isar.id_mmfr1 = 0x00000000; 596 cpu->isar.id_mmfr2 = 0x00000000; 597 cpu->isar.id_mmfr3 = 0x00000000; 598 cpu->isar.id_isar0 = 0x01141110; 599 cpu->isar.id_isar1 = 0x02111000; 600 cpu->isar.id_isar2 = 0x21112231; 601 cpu->isar.id_isar3 = 0x01111110; 602 cpu->isar.id_isar4 = 0x01310102; 603 cpu->isar.id_isar5 = 0x00000000; 604 cpu->isar.id_isar6 = 0x00000000; 605 } 606 607 static void cortex_m3_initfn(Object *obj) 608 { 609 ARMCPU *cpu = ARM_CPU(obj); 610 set_feature(&cpu->env, ARM_FEATURE_V7); 611 set_feature(&cpu->env, ARM_FEATURE_M); 612 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 613 cpu->midr = 0x410fc231; 614 cpu->pmsav7_dregion = 8; 615 cpu->isar.id_pfr0 = 0x00000030; 616 cpu->isar.id_pfr1 = 0x00000200; 617 cpu->isar.id_dfr0 = 0x00100000; 618 cpu->id_afr0 = 0x00000000; 619 cpu->isar.id_mmfr0 = 0x00000030; 620 cpu->isar.id_mmfr1 = 0x00000000; 621 cpu->isar.id_mmfr2 = 0x00000000; 622 cpu->isar.id_mmfr3 = 0x00000000; 623 cpu->isar.id_isar0 = 0x01141110; 624 cpu->isar.id_isar1 = 0x02111000; 625 cpu->isar.id_isar2 = 0x21112231; 626 cpu->isar.id_isar3 = 0x01111110; 627 cpu->isar.id_isar4 = 0x01310102; 628 cpu->isar.id_isar5 = 0x00000000; 629 cpu->isar.id_isar6 = 0x00000000; 630 } 631 632 static void cortex_m4_initfn(Object *obj) 633 { 634 ARMCPU *cpu = ARM_CPU(obj); 635 636 set_feature(&cpu->env, ARM_FEATURE_V7); 637 set_feature(&cpu->env, ARM_FEATURE_M); 638 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 639 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 640 cpu->midr = 0x410fc240; /* r0p0 */ 641 cpu->pmsav7_dregion = 8; 642 cpu->isar.mvfr0 = 0x10110021; 643 cpu->isar.mvfr1 = 0x11000011; 644 cpu->isar.mvfr2 = 0x00000000; 645 cpu->isar.id_pfr0 = 0x00000030; 646 cpu->isar.id_pfr1 = 0x00000200; 647 cpu->isar.id_dfr0 = 0x00100000; 648 cpu->id_afr0 = 0x00000000; 649 cpu->isar.id_mmfr0 = 0x00000030; 650 cpu->isar.id_mmfr1 = 0x00000000; 651 cpu->isar.id_mmfr2 = 0x00000000; 652 cpu->isar.id_mmfr3 = 0x00000000; 653 cpu->isar.id_isar0 = 0x01141110; 654 cpu->isar.id_isar1 = 0x02111000; 655 cpu->isar.id_isar2 = 0x21112231; 656 cpu->isar.id_isar3 = 0x01111110; 657 cpu->isar.id_isar4 = 0x01310102; 658 cpu->isar.id_isar5 = 0x00000000; 659 cpu->isar.id_isar6 = 0x00000000; 660 } 661 662 static void cortex_m7_initfn(Object *obj) 663 { 664 ARMCPU *cpu = ARM_CPU(obj); 665 666 set_feature(&cpu->env, ARM_FEATURE_V7); 667 set_feature(&cpu->env, ARM_FEATURE_M); 668 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 669 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 670 cpu->midr = 0x411fc272; /* r1p2 */ 671 cpu->pmsav7_dregion = 8; 672 cpu->isar.mvfr0 = 0x10110221; 673 cpu->isar.mvfr1 = 0x12000011; 674 cpu->isar.mvfr2 = 0x00000040; 675 cpu->isar.id_pfr0 = 0x00000030; 676 cpu->isar.id_pfr1 = 0x00000200; 677 cpu->isar.id_dfr0 = 0x00100000; 678 cpu->id_afr0 = 0x00000000; 679 cpu->isar.id_mmfr0 = 0x00100030; 680 cpu->isar.id_mmfr1 = 0x00000000; 681 cpu->isar.id_mmfr2 = 0x01000000; 682 cpu->isar.id_mmfr3 = 0x00000000; 683 cpu->isar.id_isar0 = 0x01101110; 684 cpu->isar.id_isar1 = 0x02112000; 685 cpu->isar.id_isar2 = 0x20232231; 686 cpu->isar.id_isar3 = 0x01111131; 687 cpu->isar.id_isar4 = 0x01310132; 688 cpu->isar.id_isar5 = 0x00000000; 689 cpu->isar.id_isar6 = 0x00000000; 690 } 691 692 static void cortex_m33_initfn(Object *obj) 693 { 694 ARMCPU *cpu = ARM_CPU(obj); 695 696 set_feature(&cpu->env, ARM_FEATURE_V8); 697 set_feature(&cpu->env, ARM_FEATURE_M); 698 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 699 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 700 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 701 cpu->midr = 0x410fd213; /* r0p3 */ 702 cpu->pmsav7_dregion = 16; 703 cpu->sau_sregion = 8; 704 cpu->isar.mvfr0 = 0x10110021; 705 cpu->isar.mvfr1 = 0x11000011; 706 cpu->isar.mvfr2 = 0x00000040; 707 cpu->isar.id_pfr0 = 0x00000030; 708 cpu->isar.id_pfr1 = 0x00000210; 709 cpu->isar.id_dfr0 = 0x00200000; 710 cpu->id_afr0 = 0x00000000; 711 cpu->isar.id_mmfr0 = 0x00101F40; 712 cpu->isar.id_mmfr1 = 0x00000000; 713 cpu->isar.id_mmfr2 = 0x01000000; 714 cpu->isar.id_mmfr3 = 0x00000000; 715 cpu->isar.id_isar0 = 0x01101110; 716 cpu->isar.id_isar1 = 0x02212000; 717 cpu->isar.id_isar2 = 0x20232232; 718 cpu->isar.id_isar3 = 0x01111131; 719 cpu->isar.id_isar4 = 0x01310132; 720 cpu->isar.id_isar5 = 0x00000000; 721 cpu->isar.id_isar6 = 0x00000000; 722 cpu->clidr = 0x00000000; 723 cpu->ctr = 0x8000c000; 724 } 725 726 static void cortex_m55_initfn(Object *obj) 727 { 728 ARMCPU *cpu = ARM_CPU(obj); 729 730 set_feature(&cpu->env, ARM_FEATURE_V8); 731 set_feature(&cpu->env, ARM_FEATURE_V8_1M); 732 set_feature(&cpu->env, ARM_FEATURE_M); 733 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 734 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 735 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 736 cpu->midr = 0x410fd221; /* r0p1 */ 737 cpu->revidr = 0; 738 cpu->pmsav7_dregion = 16; 739 cpu->sau_sregion = 8; 740 /* These are the MVFR* values for the FPU + full MVE configuration */ 741 cpu->isar.mvfr0 = 0x10110221; 742 cpu->isar.mvfr1 = 0x12100211; 743 cpu->isar.mvfr2 = 0x00000040; 744 cpu->isar.id_pfr0 = 0x20000030; 745 cpu->isar.id_pfr1 = 0x00000230; 746 cpu->isar.id_dfr0 = 0x10200000; 747 cpu->id_afr0 = 0x00000000; 748 cpu->isar.id_mmfr0 = 0x00111040; 749 cpu->isar.id_mmfr1 = 0x00000000; 750 cpu->isar.id_mmfr2 = 0x01000000; 751 cpu->isar.id_mmfr3 = 0x00000011; 752 cpu->isar.id_isar0 = 0x01103110; 753 cpu->isar.id_isar1 = 0x02212000; 754 cpu->isar.id_isar2 = 0x20232232; 755 cpu->isar.id_isar3 = 0x01111131; 756 cpu->isar.id_isar4 = 0x01310132; 757 cpu->isar.id_isar5 = 0x00000000; 758 cpu->isar.id_isar6 = 0x00000000; 759 cpu->clidr = 0x00000000; /* caches not implemented */ 760 cpu->ctr = 0x8303c003; 761 } 762 763 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 764 /* Dummy the TCM region regs for the moment */ 765 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 766 .access = PL1_RW, .type = ARM_CP_CONST }, 767 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 768 .access = PL1_RW, .type = ARM_CP_CONST }, 769 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 770 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 771 }; 772 773 static void cortex_r5_initfn(Object *obj) 774 { 775 ARMCPU *cpu = ARM_CPU(obj); 776 777 set_feature(&cpu->env, ARM_FEATURE_V7); 778 set_feature(&cpu->env, ARM_FEATURE_V7MP); 779 set_feature(&cpu->env, ARM_FEATURE_PMSA); 780 set_feature(&cpu->env, ARM_FEATURE_PMU); 781 cpu->midr = 0x411fc153; /* r1p3 */ 782 cpu->isar.id_pfr0 = 0x0131; 783 cpu->isar.id_pfr1 = 0x001; 784 cpu->isar.id_dfr0 = 0x010400; 785 cpu->id_afr0 = 0x0; 786 cpu->isar.id_mmfr0 = 0x0210030; 787 cpu->isar.id_mmfr1 = 0x00000000; 788 cpu->isar.id_mmfr2 = 0x01200000; 789 cpu->isar.id_mmfr3 = 0x0211; 790 cpu->isar.id_isar0 = 0x02101111; 791 cpu->isar.id_isar1 = 0x13112111; 792 cpu->isar.id_isar2 = 0x21232141; 793 cpu->isar.id_isar3 = 0x01112131; 794 cpu->isar.id_isar4 = 0x0010142; 795 cpu->isar.id_isar5 = 0x0; 796 cpu->isar.id_isar6 = 0x0; 797 cpu->mp_is_up = true; 798 cpu->pmsav7_dregion = 16; 799 cpu->isar.reset_pmcr_el0 = 0x41151800; 800 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 801 } 802 803 static void cortex_r52_initfn(Object *obj) 804 { 805 ARMCPU *cpu = ARM_CPU(obj); 806 807 set_feature(&cpu->env, ARM_FEATURE_V8); 808 set_feature(&cpu->env, ARM_FEATURE_EL2); 809 set_feature(&cpu->env, ARM_FEATURE_PMSA); 810 set_feature(&cpu->env, ARM_FEATURE_NEON); 811 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 812 cpu->midr = 0x411fd133; /* r1p3 */ 813 cpu->revidr = 0x00000000; 814 cpu->reset_fpsid = 0x41034023; 815 cpu->isar.mvfr0 = 0x10110222; 816 cpu->isar.mvfr1 = 0x12111111; 817 cpu->isar.mvfr2 = 0x00000043; 818 cpu->ctr = 0x8144c004; 819 cpu->reset_sctlr = 0x30c50838; 820 cpu->isar.id_pfr0 = 0x00000131; 821 cpu->isar.id_pfr1 = 0x10111001; 822 cpu->isar.id_dfr0 = 0x03010006; 823 cpu->id_afr0 = 0x00000000; 824 cpu->isar.id_mmfr0 = 0x00211040; 825 cpu->isar.id_mmfr1 = 0x40000000; 826 cpu->isar.id_mmfr2 = 0x01200000; 827 cpu->isar.id_mmfr3 = 0xf0102211; 828 cpu->isar.id_mmfr4 = 0x00000010; 829 cpu->isar.id_isar0 = 0x02101110; 830 cpu->isar.id_isar1 = 0x13112111; 831 cpu->isar.id_isar2 = 0x21232142; 832 cpu->isar.id_isar3 = 0x01112131; 833 cpu->isar.id_isar4 = 0x00010142; 834 cpu->isar.id_isar5 = 0x00010001; 835 cpu->isar.dbgdidr = 0x77168000; 836 cpu->clidr = (1 << 27) | (1 << 24) | 0x3; 837 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 838 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 839 840 cpu->pmsav7_dregion = 16; 841 cpu->pmsav8r_hdregion = 16; 842 } 843 844 static void cortex_r5f_initfn(Object *obj) 845 { 846 ARMCPU *cpu = ARM_CPU(obj); 847 848 cortex_r5_initfn(obj); 849 cpu->isar.mvfr0 = 0x10110221; 850 cpu->isar.mvfr1 = 0x00000011; 851 } 852 853 static void ti925t_initfn(Object *obj) 854 { 855 ARMCPU *cpu = ARM_CPU(obj); 856 set_feature(&cpu->env, ARM_FEATURE_V4T); 857 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 858 cpu->midr = ARM_CPUID_TI925T; 859 cpu->ctr = 0x5109149; 860 cpu->reset_sctlr = 0x00000070; 861 } 862 863 static void sa1100_initfn(Object *obj) 864 { 865 ARMCPU *cpu = ARM_CPU(obj); 866 867 cpu->dtb_compatible = "intel,sa1100"; 868 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 869 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 870 cpu->midr = 0x4401A11B; 871 cpu->reset_sctlr = 0x00000070; 872 } 873 874 static void sa1110_initfn(Object *obj) 875 { 876 ARMCPU *cpu = ARM_CPU(obj); 877 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 878 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 879 cpu->midr = 0x6901B119; 880 cpu->reset_sctlr = 0x00000070; 881 } 882 883 static void pxa250_initfn(Object *obj) 884 { 885 ARMCPU *cpu = ARM_CPU(obj); 886 887 cpu->dtb_compatible = "marvell,xscale"; 888 set_feature(&cpu->env, ARM_FEATURE_V5); 889 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 890 cpu->midr = 0x69052100; 891 cpu->ctr = 0xd172172; 892 cpu->reset_sctlr = 0x00000078; 893 } 894 895 static void pxa255_initfn(Object *obj) 896 { 897 ARMCPU *cpu = ARM_CPU(obj); 898 899 cpu->dtb_compatible = "marvell,xscale"; 900 set_feature(&cpu->env, ARM_FEATURE_V5); 901 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 902 cpu->midr = 0x69052d00; 903 cpu->ctr = 0xd172172; 904 cpu->reset_sctlr = 0x00000078; 905 } 906 907 static void pxa260_initfn(Object *obj) 908 { 909 ARMCPU *cpu = ARM_CPU(obj); 910 911 cpu->dtb_compatible = "marvell,xscale"; 912 set_feature(&cpu->env, ARM_FEATURE_V5); 913 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 914 cpu->midr = 0x69052903; 915 cpu->ctr = 0xd172172; 916 cpu->reset_sctlr = 0x00000078; 917 } 918 919 static void pxa261_initfn(Object *obj) 920 { 921 ARMCPU *cpu = ARM_CPU(obj); 922 923 cpu->dtb_compatible = "marvell,xscale"; 924 set_feature(&cpu->env, ARM_FEATURE_V5); 925 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 926 cpu->midr = 0x69052d05; 927 cpu->ctr = 0xd172172; 928 cpu->reset_sctlr = 0x00000078; 929 } 930 931 static void pxa262_initfn(Object *obj) 932 { 933 ARMCPU *cpu = ARM_CPU(obj); 934 935 cpu->dtb_compatible = "marvell,xscale"; 936 set_feature(&cpu->env, ARM_FEATURE_V5); 937 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 938 cpu->midr = 0x69052d06; 939 cpu->ctr = 0xd172172; 940 cpu->reset_sctlr = 0x00000078; 941 } 942 943 static void pxa270a0_initfn(Object *obj) 944 { 945 ARMCPU *cpu = ARM_CPU(obj); 946 947 cpu->dtb_compatible = "marvell,xscale"; 948 set_feature(&cpu->env, ARM_FEATURE_V5); 949 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 950 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 951 cpu->midr = 0x69054110; 952 cpu->ctr = 0xd172172; 953 cpu->reset_sctlr = 0x00000078; 954 } 955 956 static void pxa270a1_initfn(Object *obj) 957 { 958 ARMCPU *cpu = ARM_CPU(obj); 959 960 cpu->dtb_compatible = "marvell,xscale"; 961 set_feature(&cpu->env, ARM_FEATURE_V5); 962 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 963 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 964 cpu->midr = 0x69054111; 965 cpu->ctr = 0xd172172; 966 cpu->reset_sctlr = 0x00000078; 967 } 968 969 static void pxa270b0_initfn(Object *obj) 970 { 971 ARMCPU *cpu = ARM_CPU(obj); 972 973 cpu->dtb_compatible = "marvell,xscale"; 974 set_feature(&cpu->env, ARM_FEATURE_V5); 975 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 976 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 977 cpu->midr = 0x69054112; 978 cpu->ctr = 0xd172172; 979 cpu->reset_sctlr = 0x00000078; 980 } 981 982 static void pxa270b1_initfn(Object *obj) 983 { 984 ARMCPU *cpu = ARM_CPU(obj); 985 986 cpu->dtb_compatible = "marvell,xscale"; 987 set_feature(&cpu->env, ARM_FEATURE_V5); 988 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 989 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 990 cpu->midr = 0x69054113; 991 cpu->ctr = 0xd172172; 992 cpu->reset_sctlr = 0x00000078; 993 } 994 995 static void pxa270c0_initfn(Object *obj) 996 { 997 ARMCPU *cpu = ARM_CPU(obj); 998 999 cpu->dtb_compatible = "marvell,xscale"; 1000 set_feature(&cpu->env, ARM_FEATURE_V5); 1001 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1002 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1003 cpu->midr = 0x69054114; 1004 cpu->ctr = 0xd172172; 1005 cpu->reset_sctlr = 0x00000078; 1006 } 1007 1008 static void pxa270c5_initfn(Object *obj) 1009 { 1010 ARMCPU *cpu = ARM_CPU(obj); 1011 1012 cpu->dtb_compatible = "marvell,xscale"; 1013 set_feature(&cpu->env, ARM_FEATURE_V5); 1014 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1015 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1016 cpu->midr = 0x69054117; 1017 cpu->ctr = 0xd172172; 1018 cpu->reset_sctlr = 0x00000078; 1019 } 1020 1021 static const TCGCPUOps arm_v7m_tcg_ops = { 1022 .initialize = arm_translate_init, 1023 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 1024 .debug_excp_handler = arm_debug_excp_handler, 1025 .restore_state_to_opc = arm_restore_state_to_opc, 1026 1027 #ifdef CONFIG_USER_ONLY 1028 .record_sigsegv = arm_cpu_record_sigsegv, 1029 .record_sigbus = arm_cpu_record_sigbus, 1030 #else 1031 .tlb_fill = arm_cpu_tlb_fill, 1032 .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, 1033 .do_interrupt = arm_v7m_cpu_do_interrupt, 1034 .do_transaction_failed = arm_cpu_do_transaction_failed, 1035 .do_unaligned_access = arm_cpu_do_unaligned_access, 1036 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 1037 .debug_check_watchpoint = arm_debug_check_watchpoint, 1038 .debug_check_breakpoint = arm_debug_check_breakpoint, 1039 #endif /* !CONFIG_USER_ONLY */ 1040 }; 1041 1042 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1043 { 1044 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1045 CPUClass *cc = CPU_CLASS(oc); 1046 1047 acc->info = data; 1048 cc->tcg_ops = &arm_v7m_tcg_ops; 1049 cc->gdb_core_xml_file = "arm-m-profile.xml"; 1050 } 1051 1052 #ifndef TARGET_AARCH64 1053 /* 1054 * -cpu max: a CPU with as many features enabled as our emulation supports. 1055 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 1056 * this only needs to handle 32 bits, and need not care about KVM. 1057 */ 1058 static void arm_max_initfn(Object *obj) 1059 { 1060 ARMCPU *cpu = ARM_CPU(obj); 1061 1062 /* aarch64_a57_initfn, advertising none of the aarch64 features */ 1063 cpu->dtb_compatible = "arm,cortex-a57"; 1064 set_feature(&cpu->env, ARM_FEATURE_V8); 1065 set_feature(&cpu->env, ARM_FEATURE_NEON); 1066 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1067 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1068 set_feature(&cpu->env, ARM_FEATURE_EL2); 1069 set_feature(&cpu->env, ARM_FEATURE_EL3); 1070 set_feature(&cpu->env, ARM_FEATURE_PMU); 1071 cpu->midr = 0x411fd070; 1072 cpu->revidr = 0x00000000; 1073 cpu->reset_fpsid = 0x41034070; 1074 cpu->isar.mvfr0 = 0x10110222; 1075 cpu->isar.mvfr1 = 0x12111111; 1076 cpu->isar.mvfr2 = 0x00000043; 1077 cpu->ctr = 0x8444c004; 1078 cpu->reset_sctlr = 0x00c50838; 1079 cpu->isar.id_pfr0 = 0x00000131; 1080 cpu->isar.id_pfr1 = 0x00011011; 1081 cpu->isar.id_dfr0 = 0x03010066; 1082 cpu->id_afr0 = 0x00000000; 1083 cpu->isar.id_mmfr0 = 0x10101105; 1084 cpu->isar.id_mmfr1 = 0x40000000; 1085 cpu->isar.id_mmfr2 = 0x01260000; 1086 cpu->isar.id_mmfr3 = 0x02102211; 1087 cpu->isar.id_isar0 = 0x02101110; 1088 cpu->isar.id_isar1 = 0x13112111; 1089 cpu->isar.id_isar2 = 0x21232042; 1090 cpu->isar.id_isar3 = 0x01112131; 1091 cpu->isar.id_isar4 = 0x00011142; 1092 cpu->isar.id_isar5 = 0x00011121; 1093 cpu->isar.id_isar6 = 0; 1094 cpu->isar.dbgdidr = 0x3516d000; 1095 cpu->isar.dbgdevid = 0x00110f13; 1096 cpu->isar.dbgdevid1 = 0x2; 1097 cpu->isar.reset_pmcr_el0 = 0x41013000; 1098 cpu->clidr = 0x0a200023; 1099 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 1100 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 1101 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 1102 define_cortex_a72_a57_a53_cp_reginfo(cpu); 1103 1104 aa32_max_features(cpu); 1105 1106 #ifdef CONFIG_USER_ONLY 1107 /* 1108 * Break with true ARMv8 and add back old-style VFP short-vector support. 1109 * Only do this for user-mode, where -cpu max is the default, so that 1110 * older v6 and v7 programs are more likely to work without adjustment. 1111 */ 1112 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1113 #endif 1114 } 1115 #endif /* !TARGET_AARCH64 */ 1116 1117 static const ARMCPUInfo arm_tcg_cpus[] = { 1118 { .name = "arm926", .initfn = arm926_initfn }, 1119 { .name = "arm946", .initfn = arm946_initfn }, 1120 { .name = "arm1026", .initfn = arm1026_initfn }, 1121 /* 1122 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1123 * older core than plain "arm1136". In particular this does not 1124 * have the v6K features. 1125 */ 1126 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1127 { .name = "arm1136", .initfn = arm1136_initfn }, 1128 { .name = "arm1176", .initfn = arm1176_initfn }, 1129 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1130 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1131 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1132 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1133 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1134 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 1135 .class_init = arm_v7m_class_init }, 1136 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1137 .class_init = arm_v7m_class_init }, 1138 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1139 .class_init = arm_v7m_class_init }, 1140 { .name = "cortex-m7", .initfn = cortex_m7_initfn, 1141 .class_init = arm_v7m_class_init }, 1142 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 1143 .class_init = arm_v7m_class_init }, 1144 { .name = "cortex-m55", .initfn = cortex_m55_initfn, 1145 .class_init = arm_v7m_class_init }, 1146 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1147 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 1148 { .name = "cortex-r52", .initfn = cortex_r52_initfn }, 1149 { .name = "ti925t", .initfn = ti925t_initfn }, 1150 { .name = "sa1100", .initfn = sa1100_initfn }, 1151 { .name = "sa1110", .initfn = sa1110_initfn }, 1152 { .name = "pxa250", .initfn = pxa250_initfn }, 1153 { .name = "pxa255", .initfn = pxa255_initfn }, 1154 { .name = "pxa260", .initfn = pxa260_initfn }, 1155 { .name = "pxa261", .initfn = pxa261_initfn }, 1156 { .name = "pxa262", .initfn = pxa262_initfn }, 1157 /* "pxa270" is an alias for "pxa270-a0" */ 1158 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1159 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1160 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1161 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1162 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1163 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1164 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1165 #ifndef TARGET_AARCH64 1166 { .name = "max", .initfn = arm_max_initfn }, 1167 #endif 1168 #ifdef CONFIG_USER_ONLY 1169 { .name = "any", .initfn = arm_max_initfn }, 1170 #endif 1171 }; 1172 1173 static const TypeInfo idau_interface_type_info = { 1174 .name = TYPE_IDAU_INTERFACE, 1175 .parent = TYPE_INTERFACE, 1176 .class_size = sizeof(IDAUInterfaceClass), 1177 }; 1178 1179 static void arm_tcg_cpu_register_types(void) 1180 { 1181 size_t i; 1182 1183 type_register_static(&idau_interface_type_info); 1184 for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { 1185 arm_cpu_register(&arm_tcg_cpus[i]); 1186 } 1187 } 1188 1189 type_init(arm_tcg_cpu_register_types) 1190 1191 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ 1192