1 /* 2 * QEMU ARM TCG-only CPUs. 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This code is licensed under the GNU GPL v2 or later. 7 * 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 11 #include "qemu/osdep.h" 12 #include "cpu.h" 13 #include "accel/tcg/cpu-ops.h" 14 #include "internals.h" 15 #include "target/arm/idau.h" 16 #if !defined(CONFIG_USER_ONLY) 17 #include "hw/boards.h" 18 #endif 19 #include "cpregs.h" 20 21 22 /* Share AArch32 -cpu max features with AArch64. */ 23 void aa32_max_features(ARMCPU *cpu) 24 { 25 uint32_t t; 26 ARMISARegisters *isar = &cpu->isar; 27 28 /* Add additional features supported by QEMU */ 29 t = GET_IDREG(isar, ID_ISAR5); 30 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ 31 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ 32 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ 33 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 34 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ 35 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ 36 SET_IDREG(isar, ID_ISAR5, t); 37 38 t = GET_IDREG(isar, ID_ISAR6); 39 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ 40 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ 41 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ 42 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ 43 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ 44 t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ 45 t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ 46 SET_IDREG(isar, ID_ISAR6, t); 47 48 t = cpu->isar.mvfr1; 49 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ 50 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ 51 cpu->isar.mvfr1 = t; 52 53 t = cpu->isar.mvfr2; 54 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 55 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 56 cpu->isar.mvfr2 = t; 57 58 t = cpu->isar.id_mmfr3; 59 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ 60 cpu->isar.id_mmfr3 = t; 61 62 t = cpu->isar.id_mmfr4; 63 t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ 64 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 65 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ 66 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ 67 t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ 68 cpu->isar.id_mmfr4 = t; 69 70 t = cpu->isar.id_mmfr5; 71 t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ 72 cpu->isar.id_mmfr5 = t; 73 74 t = GET_IDREG(isar, ID_PFR0); 75 t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ 76 t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ 77 t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ 78 SET_IDREG(isar, ID_PFR0, t); 79 80 t = GET_IDREG(isar, ID_PFR2); 81 t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ 82 t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ 83 SET_IDREG(isar, ID_PFR2, t); 84 85 t = GET_IDREG(isar, ID_DFR0); 86 t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ 87 t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ 88 t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ 89 SET_IDREG(isar, ID_DFR0, t); 90 91 /* Debug ID registers. */ 92 93 /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ 94 t = 0x00008000; 95 t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); 96 t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); 97 t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */ 98 t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); 99 t = FIELD_DP32(t, DBGDIDR, BRPS, 5); 100 t = FIELD_DP32(t, DBGDIDR, WRPS, 3); 101 cpu->isar.dbgdidr = t; 102 103 t = 0; 104 t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3); 105 t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); 106 t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15); 107 t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); 108 t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); 109 t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); 110 t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0); 111 t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0); 112 cpu->isar.dbgdevid = t; 113 114 /* Bits[31:4] are RES0. */ 115 t = 0; 116 t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); 117 cpu->isar.dbgdevid1 = t; 118 119 FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ 120 } 121 122 /* CPU models. These are not needed for the AArch64 linux-user build. */ 123 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 124 125 static void arm926_initfn(Object *obj) 126 { 127 ARMCPU *cpu = ARM_CPU(obj); 128 129 cpu->dtb_compatible = "arm,arm926"; 130 set_feature(&cpu->env, ARM_FEATURE_V5); 131 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 132 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 133 cpu->midr = 0x41069265; 134 cpu->reset_fpsid = 0x41011090; 135 cpu->ctr = 0x1dd20d2; 136 cpu->reset_sctlr = 0x00090078; 137 138 /* 139 * ARMv5 does not have the ID_ISAR registers, but we can still 140 * set the field to indicate Jazelle support within QEMU. 141 */ 142 FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); 143 /* 144 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 145 * support even though ARMv5 doesn't have this register. 146 */ 147 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 148 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 149 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 150 } 151 152 static void arm946_initfn(Object *obj) 153 { 154 ARMCPU *cpu = ARM_CPU(obj); 155 156 cpu->dtb_compatible = "arm,arm946"; 157 set_feature(&cpu->env, ARM_FEATURE_V5); 158 set_feature(&cpu->env, ARM_FEATURE_PMSA); 159 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 160 cpu->midr = 0x41059461; 161 cpu->ctr = 0x0f004006; 162 cpu->reset_sctlr = 0x00000078; 163 } 164 165 static void arm1026_initfn(Object *obj) 166 { 167 ARMCPU *cpu = ARM_CPU(obj); 168 169 cpu->dtb_compatible = "arm,arm1026"; 170 set_feature(&cpu->env, ARM_FEATURE_V5); 171 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 172 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 173 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 174 cpu->midr = 0x4106a262; 175 cpu->reset_fpsid = 0x410110a0; 176 cpu->ctr = 0x1dd20d2; 177 cpu->reset_sctlr = 0x00090078; 178 cpu->reset_auxcr = 1; 179 180 /* 181 * ARMv5 does not have the ID_ISAR registers, but we can still 182 * set the field to indicate Jazelle support within QEMU. 183 */ 184 FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); 185 /* 186 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 187 * support even though ARMv5 doesn't have this register. 188 */ 189 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 190 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 191 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 192 193 { 194 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 195 ARMCPRegInfo ifar = { 196 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 197 .access = PL1_RW, 198 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 199 .resetvalue = 0 200 }; 201 define_one_arm_cp_reg(cpu, &ifar); 202 } 203 } 204 205 static void arm1136_r2_initfn(Object *obj) 206 { 207 ARMCPU *cpu = ARM_CPU(obj); 208 ARMISARegisters *isar = &cpu->isar; 209 /* 210 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 211 * older core than plain "arm1136". In particular this does not 212 * have the v6K features. 213 * These ID register values are correct for 1136 but may be wrong 214 * for 1136_r2 (in particular r0p2 does not actually implement most 215 * of the ID registers). 216 */ 217 218 cpu->dtb_compatible = "arm,arm1136"; 219 set_feature(&cpu->env, ARM_FEATURE_V6); 220 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 221 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 222 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 223 cpu->midr = 0x4107b362; 224 cpu->reset_fpsid = 0x410120b4; 225 cpu->isar.mvfr0 = 0x11111111; 226 cpu->isar.mvfr1 = 0x00000000; 227 cpu->ctr = 0x1dd20d2; 228 cpu->reset_sctlr = 0x00050078; 229 SET_IDREG(isar, ID_PFR0, 0x111); 230 SET_IDREG(isar, ID_PFR1, 0x1); 231 SET_IDREG(isar, ID_DFR0, 0x2); 232 cpu->id_afr0 = 0x3; 233 cpu->isar.id_mmfr0 = 0x01130003; 234 cpu->isar.id_mmfr1 = 0x10030302; 235 cpu->isar.id_mmfr2 = 0x01222110; 236 SET_IDREG(isar, ID_ISAR0, 0x00140011); 237 SET_IDREG(isar, ID_ISAR1, 0x12002111); 238 SET_IDREG(isar, ID_ISAR2, 0x11231111); 239 SET_IDREG(isar, ID_ISAR3, 0x01102131); 240 SET_IDREG(isar, ID_ISAR4, 0x141); 241 cpu->reset_auxcr = 7; 242 } 243 244 static void arm1136_initfn(Object *obj) 245 { 246 ARMCPU *cpu = ARM_CPU(obj); 247 ARMISARegisters *isar = &cpu->isar; 248 249 cpu->dtb_compatible = "arm,arm1136"; 250 set_feature(&cpu->env, ARM_FEATURE_V6K); 251 set_feature(&cpu->env, ARM_FEATURE_V6); 252 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 253 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 254 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 255 cpu->midr = 0x4117b363; 256 cpu->reset_fpsid = 0x410120b4; 257 cpu->isar.mvfr0 = 0x11111111; 258 cpu->isar.mvfr1 = 0x00000000; 259 cpu->ctr = 0x1dd20d2; 260 cpu->reset_sctlr = 0x00050078; 261 SET_IDREG(isar, ID_PFR0, 0x111); 262 SET_IDREG(isar, ID_PFR1, 0x1); 263 SET_IDREG(isar, ID_DFR0, 0x2); 264 cpu->id_afr0 = 0x3; 265 cpu->isar.id_mmfr0 = 0x01130003; 266 cpu->isar.id_mmfr1 = 0x10030302; 267 cpu->isar.id_mmfr2 = 0x01222110; 268 SET_IDREG(isar, ID_ISAR0, 0x00140011); 269 SET_IDREG(isar, ID_ISAR1, 0x12002111); 270 SET_IDREG(isar, ID_ISAR2, 0x11231111); 271 SET_IDREG(isar, ID_ISAR3, 0x01102131); 272 SET_IDREG(isar, ID_ISAR4, 0x141); 273 cpu->reset_auxcr = 7; 274 } 275 276 static void arm1176_initfn(Object *obj) 277 { 278 ARMCPU *cpu = ARM_CPU(obj); 279 ARMISARegisters *isar = &cpu->isar; 280 281 cpu->dtb_compatible = "arm,arm1176"; 282 set_feature(&cpu->env, ARM_FEATURE_V6K); 283 set_feature(&cpu->env, ARM_FEATURE_VAPA); 284 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 285 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 286 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 287 set_feature(&cpu->env, ARM_FEATURE_EL3); 288 cpu->midr = 0x410fb767; 289 cpu->reset_fpsid = 0x410120b5; 290 cpu->isar.mvfr0 = 0x11111111; 291 cpu->isar.mvfr1 = 0x00000000; 292 cpu->ctr = 0x1dd20d2; 293 cpu->reset_sctlr = 0x00050078; 294 SET_IDREG(isar, ID_PFR0, 0x111); 295 SET_IDREG(isar, ID_PFR1, 0x11); 296 SET_IDREG(isar, ID_DFR0, 0x33); 297 cpu->id_afr0 = 0; 298 cpu->isar.id_mmfr0 = 0x01130003; 299 cpu->isar.id_mmfr1 = 0x10030302; 300 cpu->isar.id_mmfr2 = 0x01222100; 301 SET_IDREG(isar, ID_ISAR0, 0x0140011); 302 SET_IDREG(isar, ID_ISAR1, 0x12002111); 303 SET_IDREG(isar, ID_ISAR2, 0x11231121); 304 SET_IDREG(isar, ID_ISAR3, 0x01102131); 305 SET_IDREG(isar, ID_ISAR4, 0x01141); 306 cpu->reset_auxcr = 7; 307 } 308 309 static void arm11mpcore_initfn(Object *obj) 310 { 311 ARMCPU *cpu = ARM_CPU(obj); 312 ARMISARegisters *isar = &cpu->isar; 313 314 cpu->dtb_compatible = "arm,arm11mpcore"; 315 set_feature(&cpu->env, ARM_FEATURE_V6K); 316 set_feature(&cpu->env, ARM_FEATURE_VAPA); 317 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 318 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 319 cpu->midr = 0x410fb022; 320 cpu->reset_fpsid = 0x410120b4; 321 cpu->isar.mvfr0 = 0x11111111; 322 cpu->isar.mvfr1 = 0x00000000; 323 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 324 SET_IDREG(isar, ID_PFR0, 0x111); 325 SET_IDREG(isar, ID_PFR1, 0x1); 326 SET_IDREG(isar, ID_DFR0, 0); 327 cpu->id_afr0 = 0x2; 328 cpu->isar.id_mmfr0 = 0x01100103; 329 cpu->isar.id_mmfr1 = 0x10020302; 330 cpu->isar.id_mmfr2 = 0x01222000; 331 SET_IDREG(isar, ID_ISAR0, 0x00100011); 332 SET_IDREG(isar, ID_ISAR1, 0x12002111); 333 SET_IDREG(isar, ID_ISAR2, 0x11221011); 334 SET_IDREG(isar, ID_ISAR3, 0x01102131); 335 SET_IDREG(isar, ID_ISAR4, 0x141); 336 cpu->reset_auxcr = 1; 337 } 338 339 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 340 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 341 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 342 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 343 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 344 }; 345 346 static void cortex_a8_initfn(Object *obj) 347 { 348 ARMCPU *cpu = ARM_CPU(obj); 349 ARMISARegisters *isar = &cpu->isar; 350 351 cpu->dtb_compatible = "arm,cortex-a8"; 352 set_feature(&cpu->env, ARM_FEATURE_V7); 353 set_feature(&cpu->env, ARM_FEATURE_NEON); 354 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 355 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 356 set_feature(&cpu->env, ARM_FEATURE_EL3); 357 set_feature(&cpu->env, ARM_FEATURE_PMU); 358 cpu->midr = 0x410fc080; 359 cpu->reset_fpsid = 0x410330c0; 360 cpu->isar.mvfr0 = 0x11110222; 361 cpu->isar.mvfr1 = 0x00011111; 362 cpu->ctr = 0x82048004; 363 cpu->reset_sctlr = 0x00c50078; 364 SET_IDREG(isar, ID_PFR0, 0x1031); 365 SET_IDREG(isar, ID_PFR1, 0x11); 366 SET_IDREG(isar, ID_DFR0, 0x400); 367 cpu->id_afr0 = 0; 368 cpu->isar.id_mmfr0 = 0x31100003; 369 cpu->isar.id_mmfr1 = 0x20000000; 370 cpu->isar.id_mmfr2 = 0x01202000; 371 cpu->isar.id_mmfr3 = 0x11; 372 SET_IDREG(isar, ID_ISAR0, 0x00101111); 373 SET_IDREG(isar, ID_ISAR1, 0x12112111); 374 SET_IDREG(isar, ID_ISAR2, 0x21232031); 375 SET_IDREG(isar, ID_ISAR3, 0x11112131); 376 SET_IDREG(isar, ID_ISAR4, 0x00111142); 377 cpu->isar.dbgdidr = 0x15141000; 378 cpu->clidr = (1 << 27) | (2 << 24) | 3; 379 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 380 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 381 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 382 cpu->reset_auxcr = 2; 383 cpu->isar.reset_pmcr_el0 = 0x41002000; 384 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 385 } 386 387 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 388 /* 389 * power_control should be set to maximum latency. Again, 390 * default to 0 and set by private hook 391 */ 392 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 393 .access = PL1_RW, .resetvalue = 0, 394 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 395 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 396 .access = PL1_RW, .resetvalue = 0, 397 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 398 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 399 .access = PL1_RW, .resetvalue = 0, 400 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 401 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 402 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 403 /* TLB lockdown control */ 404 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 405 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 406 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 407 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 408 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 409 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 410 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 411 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 412 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 413 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 414 }; 415 416 static void cortex_a9_initfn(Object *obj) 417 { 418 ARMCPU *cpu = ARM_CPU(obj); 419 ARMISARegisters *isar = &cpu->isar; 420 421 cpu->dtb_compatible = "arm,cortex-a9"; 422 set_feature(&cpu->env, ARM_FEATURE_V7); 423 set_feature(&cpu->env, ARM_FEATURE_NEON); 424 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 425 set_feature(&cpu->env, ARM_FEATURE_EL3); 426 set_feature(&cpu->env, ARM_FEATURE_PMU); 427 /* 428 * Note that A9 supports the MP extensions even for 429 * A9UP and single-core A9MP (which are both different 430 * and valid configurations; we don't model A9UP). 431 */ 432 set_feature(&cpu->env, ARM_FEATURE_V7MP); 433 set_feature(&cpu->env, ARM_FEATURE_CBAR); 434 cpu->midr = 0x410fc090; 435 cpu->reset_fpsid = 0x41033090; 436 cpu->isar.mvfr0 = 0x11110222; 437 cpu->isar.mvfr1 = 0x01111111; 438 cpu->ctr = 0x80038003; 439 cpu->reset_sctlr = 0x00c50078; 440 SET_IDREG(isar, ID_PFR0, 0x1031); 441 SET_IDREG(isar, ID_PFR1, 0x11); 442 SET_IDREG(isar, ID_DFR0, 0x000); 443 cpu->id_afr0 = 0; 444 cpu->isar.id_mmfr0 = 0x00100103; 445 cpu->isar.id_mmfr1 = 0x20000000; 446 cpu->isar.id_mmfr2 = 0x01230000; 447 cpu->isar.id_mmfr3 = 0x00002111; 448 SET_IDREG(isar, ID_ISAR0, 0x00101111); 449 SET_IDREG(isar, ID_ISAR1, 0x13112111); 450 SET_IDREG(isar, ID_ISAR2, 0x21232041); 451 SET_IDREG(isar, ID_ISAR3, 0x11112131); 452 SET_IDREG(isar, ID_ISAR4, 0x00111142); 453 cpu->isar.dbgdidr = 0x35141000; 454 cpu->clidr = (1 << 27) | (1 << 24) | 3; 455 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 456 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 457 cpu->isar.reset_pmcr_el0 = 0x41093000; 458 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 459 } 460 461 #ifndef CONFIG_USER_ONLY 462 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 463 { 464 MachineState *ms = MACHINE(qdev_get_machine()); 465 466 /* 467 * Linux wants the number of processors from here. 468 * Might as well set the interrupt-controller bit too. 469 */ 470 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 471 } 472 #endif 473 474 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 475 #ifndef CONFIG_USER_ONLY 476 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 477 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 478 .writefn = arm_cp_write_ignore, }, 479 #endif 480 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 481 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 482 }; 483 484 static void cortex_a7_initfn(Object *obj) 485 { 486 ARMCPU *cpu = ARM_CPU(obj); 487 ARMISARegisters *isar = &cpu->isar; 488 489 cpu->dtb_compatible = "arm,cortex-a7"; 490 set_feature(&cpu->env, ARM_FEATURE_V7VE); 491 set_feature(&cpu->env, ARM_FEATURE_NEON); 492 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 493 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 494 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 495 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 496 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 497 set_feature(&cpu->env, ARM_FEATURE_EL2); 498 set_feature(&cpu->env, ARM_FEATURE_EL3); 499 set_feature(&cpu->env, ARM_FEATURE_PMU); 500 cpu->midr = 0x410fc075; 501 cpu->reset_fpsid = 0x41023075; 502 cpu->isar.mvfr0 = 0x10110222; 503 cpu->isar.mvfr1 = 0x11111111; 504 cpu->ctr = 0x84448003; 505 cpu->reset_sctlr = 0x00c50078; 506 SET_IDREG(isar, ID_PFR0, 0x00001131); 507 SET_IDREG(isar, ID_PFR1, 0x00011011); 508 SET_IDREG(isar, ID_DFR0, 0x02010555); 509 cpu->id_afr0 = 0x00000000; 510 cpu->isar.id_mmfr0 = 0x10101105; 511 cpu->isar.id_mmfr1 = 0x40000000; 512 cpu->isar.id_mmfr2 = 0x01240000; 513 cpu->isar.id_mmfr3 = 0x02102211; 514 /* 515 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 516 * table 4-41 gives 0x02101110, which includes the arm div insns. 517 */ 518 SET_IDREG(isar, ID_ISAR0, 0x02101110); 519 SET_IDREG(isar, ID_ISAR1, 0x13112111); 520 SET_IDREG(isar, ID_ISAR2, 0x21232041); 521 SET_IDREG(isar, ID_ISAR3, 0x11112131); 522 SET_IDREG(isar, ID_ISAR4, 0x10011142); 523 cpu->isar.dbgdidr = 0x3515f005; 524 cpu->isar.dbgdevid = 0x01110f13; 525 cpu->isar.dbgdevid1 = 0x1; 526 cpu->clidr = 0x0a200023; 527 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 528 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 529 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 530 cpu->isar.reset_pmcr_el0 = 0x41072000; 531 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 532 } 533 534 static void cortex_a15_initfn(Object *obj) 535 { 536 ARMCPU *cpu = ARM_CPU(obj); 537 ARMISARegisters *isar = &cpu->isar; 538 539 cpu->dtb_compatible = "arm,cortex-a15"; 540 set_feature(&cpu->env, ARM_FEATURE_V7VE); 541 set_feature(&cpu->env, ARM_FEATURE_NEON); 542 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 543 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 544 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 545 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 546 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 547 set_feature(&cpu->env, ARM_FEATURE_EL2); 548 set_feature(&cpu->env, ARM_FEATURE_EL3); 549 set_feature(&cpu->env, ARM_FEATURE_PMU); 550 /* r4p0 cpu, not requiring expensive tlb flush errata */ 551 cpu->midr = 0x414fc0f0; 552 cpu->revidr = 0x0; 553 cpu->reset_fpsid = 0x410430f0; 554 cpu->isar.mvfr0 = 0x10110222; 555 cpu->isar.mvfr1 = 0x11111111; 556 cpu->ctr = 0x8444c004; 557 cpu->reset_sctlr = 0x00c50078; 558 SET_IDREG(isar, ID_PFR0, 0x00001131); 559 SET_IDREG(isar, ID_PFR1, 0x00011011); 560 SET_IDREG(isar, ID_DFR0, 0x02010555); 561 cpu->id_afr0 = 0x00000000; 562 cpu->isar.id_mmfr0 = 0x10201105; 563 cpu->isar.id_mmfr1 = 0x20000000; 564 cpu->isar.id_mmfr2 = 0x01240000; 565 cpu->isar.id_mmfr3 = 0x02102211; 566 SET_IDREG(isar, ID_ISAR0, 0x02101110); 567 SET_IDREG(isar, ID_ISAR1, 0x13112111); 568 SET_IDREG(isar, ID_ISAR2, 0x21232041); 569 SET_IDREG(isar, ID_ISAR3, 0x11112131); 570 SET_IDREG(isar, ID_ISAR4, 0x10011142); 571 cpu->isar.dbgdidr = 0x3515f021; 572 cpu->isar.dbgdevid = 0x01110f13; 573 cpu->isar.dbgdevid1 = 0x0; 574 cpu->clidr = 0x0a200023; 575 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 576 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 577 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 578 cpu->isar.reset_pmcr_el0 = 0x410F3000; 579 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 580 } 581 582 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 583 /* Dummy the TCM region regs for the moment */ 584 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 585 .access = PL1_RW, .type = ARM_CP_CONST }, 586 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 587 .access = PL1_RW, .type = ARM_CP_CONST }, 588 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 589 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 590 }; 591 592 static void cortex_r5_initfn(Object *obj) 593 { 594 ARMCPU *cpu = ARM_CPU(obj); 595 ARMISARegisters *isar = &cpu->isar; 596 597 set_feature(&cpu->env, ARM_FEATURE_V7); 598 set_feature(&cpu->env, ARM_FEATURE_V7MP); 599 set_feature(&cpu->env, ARM_FEATURE_PMSA); 600 set_feature(&cpu->env, ARM_FEATURE_PMU); 601 cpu->midr = 0x411fc153; /* r1p3 */ 602 SET_IDREG(isar, ID_PFR0, 0x0131); 603 SET_IDREG(isar, ID_PFR1, 0x001); 604 SET_IDREG(isar, ID_DFR0, 0x010400); 605 cpu->id_afr0 = 0x0; 606 cpu->isar.id_mmfr0 = 0x0210030; 607 cpu->isar.id_mmfr1 = 0x00000000; 608 cpu->isar.id_mmfr2 = 0x01200000; 609 cpu->isar.id_mmfr3 = 0x0211; 610 SET_IDREG(isar, ID_ISAR0, 0x02101111); 611 SET_IDREG(isar, ID_ISAR1, 0x13112111); 612 SET_IDREG(isar, ID_ISAR2, 0x21232141); 613 SET_IDREG(isar, ID_ISAR3, 0x01112131); 614 SET_IDREG(isar, ID_ISAR4, 0x0010142); 615 SET_IDREG(isar, ID_ISAR5, 0x0); 616 SET_IDREG(isar, ID_ISAR6, 0x0); 617 cpu->mp_is_up = true; 618 cpu->pmsav7_dregion = 16; 619 cpu->isar.reset_pmcr_el0 = 0x41151800; 620 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 621 } 622 623 static const ARMCPRegInfo cortex_r52_cp_reginfo[] = { 624 { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15, 625 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 626 { .name = "IMP_ATCMREGIONR", 627 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 628 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 629 { .name = "IMP_BTCMREGIONR", 630 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 631 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 632 { .name = "IMP_CTCMREGIONR", 633 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2, 634 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 635 { .name = "IMP_CSCTLR", 636 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0, 637 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 638 { .name = "IMP_BPCTLR", 639 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1, 640 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 641 { .name = "IMP_MEMPROTCLR", 642 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2, 643 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 644 { .name = "IMP_SLAVEPCTLR", 645 .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0, 646 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 647 { .name = "IMP_PERIPHREGIONR", 648 .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, 649 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 650 { .name = "IMP_FLASHIFREGIONR", 651 .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1, 652 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 653 { .name = "IMP_BUILDOPTR", 654 .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, 655 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 656 { .name = "IMP_PINOPTR", 657 .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, 658 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 659 { .name = "IMP_QOSR", 660 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1, 661 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 662 { .name = "IMP_BUSTIMEOUTR", 663 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2, 664 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 665 { .name = "IMP_INTMONR", 666 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4, 667 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 668 { .name = "IMP_ICERR0", 669 .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0, 670 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 671 { .name = "IMP_ICERR1", 672 .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1, 673 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 674 { .name = "IMP_DCERR0", 675 .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0, 676 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 677 { .name = "IMP_DCERR1", 678 .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1, 679 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 680 { .name = "IMP_TCMERR0", 681 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0, 682 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 683 { .name = "IMP_TCMERR1", 684 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1, 685 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 686 { .name = "IMP_TCMSYNDR0", 687 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2, 688 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 689 { .name = "IMP_TCMSYNDR1", 690 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3, 691 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 692 { .name = "IMP_FLASHERR0", 693 .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0, 694 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 695 { .name = "IMP_FLASHERR1", 696 .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1, 697 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 698 { .name = "IMP_CDBGDR0", 699 .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0, 700 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 701 { .name = "IMP_CBDGBR1", 702 .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1, 703 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 704 { .name = "IMP_TESTR0", 705 .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0, 706 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, 707 { .name = "IMP_TESTR1", 708 .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1, 709 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 710 { .name = "IMP_CDBGDCI", 711 .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0, 712 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 713 { .name = "IMP_CDBGDCT", 714 .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0, 715 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 716 { .name = "IMP_CDBGICT", 717 .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1, 718 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 719 { .name = "IMP_CDBGDCD", 720 .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0, 721 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 722 { .name = "IMP_CDBGICD", 723 .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1, 724 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, 725 }; 726 727 728 static void cortex_r52_initfn(Object *obj) 729 { 730 ARMCPU *cpu = ARM_CPU(obj); 731 ARMISARegisters *isar = &cpu->isar; 732 733 set_feature(&cpu->env, ARM_FEATURE_V8); 734 set_feature(&cpu->env, ARM_FEATURE_EL2); 735 set_feature(&cpu->env, ARM_FEATURE_PMSA); 736 set_feature(&cpu->env, ARM_FEATURE_NEON); 737 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 738 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 739 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 740 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 741 cpu->midr = 0x411fd133; /* r1p3 */ 742 cpu->revidr = 0x00000000; 743 cpu->reset_fpsid = 0x41034023; 744 cpu->isar.mvfr0 = 0x10110222; 745 cpu->isar.mvfr1 = 0x12111111; 746 cpu->isar.mvfr2 = 0x00000043; 747 cpu->ctr = 0x8144c004; 748 cpu->reset_sctlr = 0x30c50838; 749 SET_IDREG(isar, ID_PFR0, 0x00000131); 750 SET_IDREG(isar, ID_PFR1, 0x10111001); 751 SET_IDREG(isar, ID_DFR0, 0x03010006); 752 cpu->id_afr0 = 0x00000000; 753 cpu->isar.id_mmfr0 = 0x00211040; 754 cpu->isar.id_mmfr1 = 0x40000000; 755 cpu->isar.id_mmfr2 = 0x01200000; 756 cpu->isar.id_mmfr3 = 0xf0102211; 757 cpu->isar.id_mmfr4 = 0x00000010; 758 SET_IDREG(isar, ID_ISAR0, 0x02101110); 759 SET_IDREG(isar, ID_ISAR1, 0x13112111); 760 SET_IDREG(isar, ID_ISAR2, 0x21232142); 761 SET_IDREG(isar, ID_ISAR3, 0x01112131); 762 SET_IDREG(isar, ID_ISAR4, 0x00010142); 763 SET_IDREG(isar, ID_ISAR5, 0x00010001); 764 cpu->isar.dbgdidr = 0x77168000; 765 cpu->clidr = (1 << 27) | (1 << 24) | 0x3; 766 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ 767 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ 768 769 cpu->pmsav7_dregion = 16; 770 cpu->pmsav8r_hdregion = 16; 771 772 define_arm_cp_regs(cpu, cortex_r52_cp_reginfo); 773 } 774 775 static void cortex_r5f_initfn(Object *obj) 776 { 777 ARMCPU *cpu = ARM_CPU(obj); 778 779 cortex_r5_initfn(obj); 780 cpu->isar.mvfr0 = 0x10110221; 781 cpu->isar.mvfr1 = 0x00000011; 782 } 783 784 static void ti925t_initfn(Object *obj) 785 { 786 ARMCPU *cpu = ARM_CPU(obj); 787 set_feature(&cpu->env, ARM_FEATURE_V4T); 788 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 789 cpu->midr = ARM_CPUID_TI925T; 790 cpu->ctr = 0x5109149; 791 cpu->reset_sctlr = 0x00000070; 792 } 793 794 static void sa1100_initfn(Object *obj) 795 { 796 ARMCPU *cpu = ARM_CPU(obj); 797 798 cpu->dtb_compatible = "intel,sa1100"; 799 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 800 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 801 cpu->midr = 0x4401A11B; 802 cpu->reset_sctlr = 0x00000070; 803 } 804 805 static void sa1110_initfn(Object *obj) 806 { 807 ARMCPU *cpu = ARM_CPU(obj); 808 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 809 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 810 cpu->midr = 0x6901B119; 811 cpu->reset_sctlr = 0x00000070; 812 } 813 814 static void pxa250_initfn(Object *obj) 815 { 816 ARMCPU *cpu = ARM_CPU(obj); 817 818 cpu->dtb_compatible = "marvell,xscale"; 819 set_feature(&cpu->env, ARM_FEATURE_V5); 820 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 821 cpu->midr = 0x69052100; 822 cpu->ctr = 0xd172172; 823 cpu->reset_sctlr = 0x00000078; 824 } 825 826 static void pxa255_initfn(Object *obj) 827 { 828 ARMCPU *cpu = ARM_CPU(obj); 829 830 cpu->dtb_compatible = "marvell,xscale"; 831 set_feature(&cpu->env, ARM_FEATURE_V5); 832 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 833 cpu->midr = 0x69052d00; 834 cpu->ctr = 0xd172172; 835 cpu->reset_sctlr = 0x00000078; 836 } 837 838 static void pxa260_initfn(Object *obj) 839 { 840 ARMCPU *cpu = ARM_CPU(obj); 841 842 cpu->dtb_compatible = "marvell,xscale"; 843 set_feature(&cpu->env, ARM_FEATURE_V5); 844 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 845 cpu->midr = 0x69052903; 846 cpu->ctr = 0xd172172; 847 cpu->reset_sctlr = 0x00000078; 848 } 849 850 static void pxa261_initfn(Object *obj) 851 { 852 ARMCPU *cpu = ARM_CPU(obj); 853 854 cpu->dtb_compatible = "marvell,xscale"; 855 set_feature(&cpu->env, ARM_FEATURE_V5); 856 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 857 cpu->midr = 0x69052d05; 858 cpu->ctr = 0xd172172; 859 cpu->reset_sctlr = 0x00000078; 860 } 861 862 static void pxa262_initfn(Object *obj) 863 { 864 ARMCPU *cpu = ARM_CPU(obj); 865 866 cpu->dtb_compatible = "marvell,xscale"; 867 set_feature(&cpu->env, ARM_FEATURE_V5); 868 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 869 cpu->midr = 0x69052d06; 870 cpu->ctr = 0xd172172; 871 cpu->reset_sctlr = 0x00000078; 872 } 873 874 static void pxa270a0_initfn(Object *obj) 875 { 876 ARMCPU *cpu = ARM_CPU(obj); 877 878 cpu->dtb_compatible = "marvell,xscale"; 879 set_feature(&cpu->env, ARM_FEATURE_V5); 880 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 881 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 882 cpu->midr = 0x69054110; 883 cpu->ctr = 0xd172172; 884 cpu->reset_sctlr = 0x00000078; 885 } 886 887 static void pxa270a1_initfn(Object *obj) 888 { 889 ARMCPU *cpu = ARM_CPU(obj); 890 891 cpu->dtb_compatible = "marvell,xscale"; 892 set_feature(&cpu->env, ARM_FEATURE_V5); 893 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 894 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 895 cpu->midr = 0x69054111; 896 cpu->ctr = 0xd172172; 897 cpu->reset_sctlr = 0x00000078; 898 } 899 900 static void pxa270b0_initfn(Object *obj) 901 { 902 ARMCPU *cpu = ARM_CPU(obj); 903 904 cpu->dtb_compatible = "marvell,xscale"; 905 set_feature(&cpu->env, ARM_FEATURE_V5); 906 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 907 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 908 cpu->midr = 0x69054112; 909 cpu->ctr = 0xd172172; 910 cpu->reset_sctlr = 0x00000078; 911 } 912 913 static void pxa270b1_initfn(Object *obj) 914 { 915 ARMCPU *cpu = ARM_CPU(obj); 916 917 cpu->dtb_compatible = "marvell,xscale"; 918 set_feature(&cpu->env, ARM_FEATURE_V5); 919 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 920 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 921 cpu->midr = 0x69054113; 922 cpu->ctr = 0xd172172; 923 cpu->reset_sctlr = 0x00000078; 924 } 925 926 static void pxa270c0_initfn(Object *obj) 927 { 928 ARMCPU *cpu = ARM_CPU(obj); 929 930 cpu->dtb_compatible = "marvell,xscale"; 931 set_feature(&cpu->env, ARM_FEATURE_V5); 932 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 933 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 934 cpu->midr = 0x69054114; 935 cpu->ctr = 0xd172172; 936 cpu->reset_sctlr = 0x00000078; 937 } 938 939 static void pxa270c5_initfn(Object *obj) 940 { 941 ARMCPU *cpu = ARM_CPU(obj); 942 943 cpu->dtb_compatible = "marvell,xscale"; 944 set_feature(&cpu->env, ARM_FEATURE_V5); 945 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 946 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 947 cpu->midr = 0x69054117; 948 cpu->ctr = 0xd172172; 949 cpu->reset_sctlr = 0x00000078; 950 } 951 952 #ifndef TARGET_AARCH64 953 /* 954 * -cpu max: a CPU with as many features enabled as our emulation supports. 955 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 956 * this only needs to handle 32 bits, and need not care about KVM. 957 */ 958 static void arm_max_initfn(Object *obj) 959 { 960 ARMCPU *cpu = ARM_CPU(obj); 961 ARMISARegisters *isar = &cpu->isar; 962 963 /* aarch64_a57_initfn, advertising none of the aarch64 features */ 964 cpu->dtb_compatible = "arm,cortex-a57"; 965 set_feature(&cpu->env, ARM_FEATURE_V8); 966 set_feature(&cpu->env, ARM_FEATURE_NEON); 967 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 968 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); 969 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 970 set_feature(&cpu->env, ARM_FEATURE_EL2); 971 set_feature(&cpu->env, ARM_FEATURE_EL3); 972 set_feature(&cpu->env, ARM_FEATURE_PMU); 973 cpu->midr = 0x411fd070; 974 cpu->revidr = 0x00000000; 975 cpu->reset_fpsid = 0x41034070; 976 cpu->isar.mvfr0 = 0x10110222; 977 cpu->isar.mvfr1 = 0x12111111; 978 cpu->isar.mvfr2 = 0x00000043; 979 cpu->ctr = 0x8444c004; 980 cpu->reset_sctlr = 0x00c50838; 981 SET_IDREG(isar, ID_PFR0, 0x00000131); 982 SET_IDREG(isar, ID_PFR1, 0x00011011); 983 SET_IDREG(isar, ID_DFR0, 0x03010066); 984 cpu->id_afr0 = 0x00000000; 985 cpu->isar.id_mmfr0 = 0x10101105; 986 cpu->isar.id_mmfr1 = 0x40000000; 987 cpu->isar.id_mmfr2 = 0x01260000; 988 cpu->isar.id_mmfr3 = 0x02102211; 989 SET_IDREG(isar, ID_ISAR0, 0x02101110); 990 SET_IDREG(isar, ID_ISAR1, 0x13112111); 991 SET_IDREG(isar, ID_ISAR2, 0x21232042); 992 SET_IDREG(isar, ID_ISAR3, 0x01112131); 993 SET_IDREG(isar, ID_ISAR4, 0x00011142); 994 SET_IDREG(isar, ID_ISAR5, 0x00011121); 995 SET_IDREG(isar, ID_ISAR6, 0); 996 cpu->isar.reset_pmcr_el0 = 0x41013000; 997 cpu->clidr = 0x0a200023; 998 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 999 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 1000 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 1001 define_cortex_a72_a57_a53_cp_reginfo(cpu); 1002 1003 aa32_max_features(cpu); 1004 1005 #ifdef CONFIG_USER_ONLY 1006 /* 1007 * Break with true ARMv8 and add back old-style VFP short-vector support. 1008 * Only do this for user-mode, where -cpu max is the default, so that 1009 * older v6 and v7 programs are more likely to work without adjustment. 1010 */ 1011 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1012 #endif 1013 } 1014 #endif /* !TARGET_AARCH64 */ 1015 1016 static const ARMCPUInfo arm_tcg_cpus[] = { 1017 { .name = "arm926", .initfn = arm926_initfn }, 1018 { .name = "arm946", .initfn = arm946_initfn }, 1019 { .name = "arm1026", .initfn = arm1026_initfn }, 1020 /* 1021 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1022 * older core than plain "arm1136". In particular this does not 1023 * have the v6K features. 1024 */ 1025 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1026 { .name = "arm1136", .initfn = arm1136_initfn }, 1027 { .name = "arm1176", .initfn = arm1176_initfn }, 1028 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1029 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1030 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1031 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1032 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1033 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1034 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 1035 { .name = "cortex-r52", .initfn = cortex_r52_initfn }, 1036 { .name = "ti925t", .initfn = ti925t_initfn }, 1037 { .name = "sa1100", .initfn = sa1100_initfn }, 1038 { .name = "sa1110", .initfn = sa1110_initfn }, 1039 { .name = "pxa250", .initfn = pxa250_initfn, 1040 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1041 { .name = "pxa255", .initfn = pxa255_initfn, 1042 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1043 { .name = "pxa260", .initfn = pxa260_initfn, 1044 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1045 { .name = "pxa261", .initfn = pxa261_initfn, 1046 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1047 { .name = "pxa262", .initfn = pxa262_initfn, 1048 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1049 /* "pxa270" is an alias for "pxa270-a0" */ 1050 { .name = "pxa270", .initfn = pxa270a0_initfn, 1051 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1052 { .name = "pxa270-a0", .initfn = pxa270a0_initfn, 1053 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1054 { .name = "pxa270-a1", .initfn = pxa270a1_initfn, 1055 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1056 { .name = "pxa270-b0", .initfn = pxa270b0_initfn, 1057 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1058 { .name = "pxa270-b1", .initfn = pxa270b1_initfn, 1059 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1060 { .name = "pxa270-c0", .initfn = pxa270c0_initfn, 1061 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1062 { .name = "pxa270-c5", .initfn = pxa270c5_initfn, 1063 .deprecation_note = "iwMMXt CPUs are no longer supported", }, 1064 #ifndef TARGET_AARCH64 1065 { .name = "max", .initfn = arm_max_initfn }, 1066 #endif 1067 #ifdef CONFIG_USER_ONLY 1068 { .name = "any", .initfn = arm_max_initfn }, 1069 #endif 1070 }; 1071 1072 static const TypeInfo idau_interface_type_info = { 1073 .name = TYPE_IDAU_INTERFACE, 1074 .parent = TYPE_INTERFACE, 1075 .class_size = sizeof(IDAUInterfaceClass), 1076 }; 1077 1078 static void arm_tcg_cpu_register_types(void) 1079 { 1080 size_t i; 1081 1082 type_register_static(&idau_interface_type_info); 1083 for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { 1084 arm_cpu_register(&arm_tcg_cpus[i]); 1085 } 1086 } 1087 1088 type_init(arm_tcg_cpu_register_types) 1089 1090 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ 1091