1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22%rd 0:5 23%esz_sd 22:1 !function=plus_2 24%esz_hsd 22:2 !function=xor_2 25%hl 11:1 21:1 26%hlm 11:1 20:2 27 28&r rn 29&ri rd imm 30&rri_sf rd rn imm sf 31&i imm 32&rr_e rd rn esz 33&rrr_e rd rn rm esz 34&rrx_e rd rn rm idx esz 35&rrrr_e rd rn rm ra esz 36&qrr_e q rd rn esz 37&qrrr_e q rd rn rm esz 38&qrrx_e q rd rn rm idx esz 39&qrrrr_e q rd rn rm ra esz 40 41@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1 42@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3 43@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd 44 45@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1 46@rrr_d ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=3 47@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd 48@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd 49@rrr_e ........ esz:2 . rm:5 ...... rn:5 rd:5 &rrr_e 50@r2r_e ........ esz:2 . ..... ...... rm:5 rd:5 &rrr_e rn=%rd 51 52@rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm 53@rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl 54@rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3 55 56@rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0 57@r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0 58@rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0 59@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3 60@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3 61 62@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0 63@qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1 64@qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd 65@qrrr_e . q:1 ...... esz:2 . rm:5 ...... rn:5 rd:5 &qrrr_e 66@qr2r_e . q:1 ...... esz:2 . ..... ...... rm:5 rd:5 &qrrr_e rn=%rd 67 68@qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \ 69 &qrrx_e esz=1 idx=%hlm 70@qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \ 71 &qrrx_e esz=2 idx=%hl 72@qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \ 73 &qrrx_e esz=3 74 75### Data Processing - Immediate 76 77# PC-rel addressing 78 79%imm_pcrel 5:s19 29:2 80@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 81 82ADR 0 .. 10000 ................... ..... @pcrel 83ADRP 1 .. 10000 ................... ..... @pcrel 84 85# Add/subtract (immediate) 86 87%imm12_sh12 10:12 !function=shl_12 88@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 89@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 90 91ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 92ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 93ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 94ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 95 96SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 97SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 98SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 99SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 100 101# Add/subtract (immediate with tags) 102 103&rri_tag rd rn uimm6 uimm4 104@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 105 106ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 107SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 108 109# Logical (immediate) 110 111&rri_log rd rn sf dbm 112@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 113@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 114 115AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 116AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 117ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 118ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 119EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 120EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 121ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 122ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 123 124# Move wide (immediate) 125 126&movw rd sf imm hw 127@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 128@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 129 130MOVN . 00 100101 .. ................ ..... @movw_64 131MOVN . 00 100101 .. ................ ..... @movw_32 132MOVZ . 10 100101 .. ................ ..... @movw_64 133MOVZ . 10 100101 .. ................ ..... @movw_32 134MOVK . 11 100101 .. ................ ..... @movw_64 135MOVK . 11 100101 .. ................ ..... @movw_32 136 137# Bitfield 138 139&bitfield rd rn sf immr imms 140@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 141@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 142 143SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 144SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 145BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 146BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 147UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 148UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 149 150# Extract 151 152&extract rd rn rm imm sf 153 154EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 155EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 156 157# Branches 158 159%imm26 0:s26 !function=times_4 160@branch . ..... .......................... &i imm=%imm26 161 162B 0 00101 .......................... @branch 163BL 1 00101 .......................... @branch 164 165%imm19 5:s19 !function=times_4 166&cbz rt imm sf nz 167 168CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 169 170%imm14 5:s14 !function=times_4 171%imm31_19 31:1 19:5 172&tbz rt imm nz bitpos 173 174TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 175 176# B.cond and BC.cond 177B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19 178 179BR 1101011 0000 11111 000000 rn:5 00000 &r 180BLR 1101011 0001 11111 000000 rn:5 00000 &r 181RET 1101011 0010 11111 000000 rn:5 00000 &r 182 183&braz rn m 184BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 185BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 186 187&reta m 188RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 189 190&bra rn rm m 191BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 192BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 193 194ERET 1101011 0100 11111 000000 11111 00000 195ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 196 197# We don't need to decode DRPS because it always UNDEFs except when 198# the processor is in halting debug state (which we don't implement). 199# The pattern is listed here as documentation. 200# DRPS 1101011 0101 11111 000000 11111 00000 201 202# Hint instruction group 203{ 204 [ 205 YIELD 1101 0101 0000 0011 0010 0000 001 11111 206 WFE 1101 0101 0000 0011 0010 0000 010 11111 207 WFI 1101 0101 0000 0011 0010 0000 011 11111 208 # We implement WFE to never block, so our SEV/SEVL are NOPs 209 # SEV 1101 0101 0000 0011 0010 0000 100 11111 210 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 211 # Our DGL is a NOP because we don't merge memory accesses anyway. 212 # DGL 1101 0101 0000 0011 0010 0000 110 11111 213 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 214 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 215 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 216 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 217 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 218 ESB 1101 0101 0000 0011 0010 0010 000 11111 219 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 220 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 221 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 222 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 223 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 224 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 225 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 226 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 227 ] 228 # The canonical NOP has CRm == op2 == 0, but all of the space 229 # that isn't specifically allocated to an instruction must NOP 230 NOP 1101 0101 0000 0011 0010 ---- --- 11111 231} 232 233# Barriers 234 235CLREX 1101 0101 0000 0011 0011 ---- 010 11111 236DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 237ISB 1101 0101 0000 0011 0011 ---- 110 11111 238SB 1101 0101 0000 0011 0011 0000 111 11111 239 240# PSTATE 241 242CFINV 1101 0101 0000 0 000 0100 0000 000 11111 243XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 244AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 245 246# These are architecturally all "MSR (immediate)"; we decode the destination 247# register too because there is no commonality in our implementation. 248@msr_i .... .... .... . ... .... imm:4 ... ..... 249MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 250MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 251MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 252MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 253MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 254MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 255MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 256MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 257MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 258MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 259 260# MRS, MSR (register), SYS, SYSL. These are all essentially the 261# same instruction as far as QEMU is concerned. 262# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 263# to hand-decode it. 264SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 265SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 266SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 267 268# Exception generation 269 270@i16 .... .... ... imm:16 ... .. &i 271SVC 1101 0100 000 ................ 000 01 @i16 272HVC 1101 0100 000 ................ 000 10 @i16 273SMC 1101 0100 000 ................ 000 11 @i16 274BRK 1101 0100 001 ................ 000 00 @i16 275HLT 1101 0100 010 ................ 000 00 @i16 276# These insns always UNDEF unless in halting debug state, which 277# we don't implement. So we don't need to decode them. The patterns 278# are listed here as documentation. 279# DCPS1 1101 0100 101 ................ 000 01 @i16 280# DCPS2 1101 0100 101 ................ 000 10 @i16 281# DCPS3 1101 0100 101 ................ 000 11 @i16 282 283# Loads and stores 284 285&stxr rn rt rt2 rs sz lasr 286&stlr rn rt sz lasr 287@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 288@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 289%imm1_30_p2 30:1 !function=plus_2 290@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 291STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 292LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 293STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 294LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 295 296STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 297LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 298 299# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 300# acquire/release semantics because QEMU's cmpxchg always has those) 301CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 302# CAS, CASA, CASAL, CASL 303CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 304 305&ldlit rt imm sz sign 306@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 307 308LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 309LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 310LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 311LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 312LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 313LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 314 315# PRFM 316NOP 11 011 0 00 ------------------- ----- 317 318&ldstpair rt2 rt rn imm sz sign w p 319@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 320 321# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 322# so we ignore hints about data access patterns, and handle these like 323# plain signed offset. 324STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 325LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 326STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 327LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 328STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 329LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 330STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 331LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 332STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 333LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 334 335# STP and LDP: post-indexed 336STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 337LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 338LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 339STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 340LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 341STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 342LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 343STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 344LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 345STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 346LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 347 348# STP and LDP: offset 349STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 350LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 351LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 352STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 353LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 354STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 355LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 356STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 357LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 358STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 359LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 360 361# STP and LDP: pre-indexed 362STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 363LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 364LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 365STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 366LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 367STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 368LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 369STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 370LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 371STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 372LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 373 374# STGP: store tag and pair 375STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 376STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 377STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 378 379# Load/store register (unscaled immediate) 380&ldst_imm rt rn imm sz sign w p unpriv ext 381@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 382@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 383@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 384@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 385 386STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 387LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 388LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 389LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 390LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 391LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 392LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 393LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 394LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 395LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 396 397STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 398LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 399LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 400LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 401LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 402LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 403LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 404LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 405LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 406LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 407 408STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 409LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 410LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 411LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 412LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 413LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 414LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 415LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 416LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 417LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 418 419STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 420LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 421LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 422LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 423LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 424LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 425LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 426LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 427LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 428LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 429 430# PRFM : prefetch memory: a no-op for QEMU 431NOP 11 111 0 00 10 0 --------- 00 ----- ----- 432 433STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 434STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 435LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 436LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 437 438STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 439STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 440LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 441LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 442 443STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 444STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 445LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 446LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 447 448# Load/store with an unsigned 12 bit immediate, which is scaled by the 449# element size. The function gets the sz:imm and returns the scaled immediate. 450%uimm_scaled 10:12 sz:3 !function=uimm_scaled 451 452@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 453 454STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 455LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 456LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 457LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 458LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 459LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 460LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 461LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 462LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 463LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 464 465# PRFM 466NOP 11 111 0 01 10 ------------ ----- ----- 467 468STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 469STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 470LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 471LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 472 473# Load/store with register offset 474&ldst rm rn rt sign ext sz opt s 475@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 476STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 477LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 478LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 479LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 480LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 481LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 482LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 483LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 484LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 485LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 486 487# PRFM 488NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 489 490STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 491STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 492LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 493LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 494 495# Atomic memory operations 496&atomic rs rn rt a r sz 497@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 498LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 499LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 500LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 501LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 502LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 503LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 504LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 505LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 506SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 507 508LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 509 510# Load/store register (pointer authentication) 511 512# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 513%ldra_imm 22:s1 12:9 !function=times_8 514 515LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 516 517&ldapr_stlr_i rn rt imm sz sign ext 518@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 519STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 520LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 521LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 522LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 523LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 524LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 525LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 526 527# Load/store multiple structures 528# The 4-bit opcode in [15:12] encodes repeat count and structure elements 529&ldst_mult rm rn rt sz q p rpt selem 530@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 531ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 532ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 533ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 534ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 535ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 536ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 537ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 538 539LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 540LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 541LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 542LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 543LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 544LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 545LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 546 547# Load/store single structure 548&ldst_single rm rn rt p selem index scale 549 550%ldst_single_selem 13:1 21:1 !function=plus_1 551 552%ldst_single_index_b 30:1 10:3 553%ldst_single_index_h 30:1 11:2 554%ldst_single_index_s 30:1 12:1 555 556@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 557 &ldst_single scale=0 selem=%ldst_single_selem \ 558 index=%ldst_single_index_b 559@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 560 &ldst_single scale=1 selem=%ldst_single_selem \ 561 index=%ldst_single_index_h 562@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 563 &ldst_single scale=2 selem=%ldst_single_selem \ 564 index=%ldst_single_index_s 565@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 566 &ldst_single scale=3 selem=%ldst_single_selem 567 568ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 569ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 570ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 571ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 572 573LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 574LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 575LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 576LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 577 578# Replicating load case 579LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 580 581%tag_offset 12:s9 !function=scale_by_log2_tag_granule 582&ldst_tag rn rt imm p w 583@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 584@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 585 586STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 587STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 588STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 589STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 590 591LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 592STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 593STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 594STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 595 596STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 597ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 598ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 599ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 600 601LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 602STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 603STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 604STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 605 606# Memory operations (memset, memcpy, memmove) 607# Each of these comes in a set of three, eg SETP (prologue), SETM (main), 608# SETE (epilogue), and each of those has different flavours to 609# indicate whether memory accesses should be unpriv or non-temporal. 610# We don't distinguish temporal and non-temporal accesses, but we 611# do need to report it in syndrome register values. 612 613# Memset 614&set rs rn rd unpriv nontemp 615# op2 bit 1 is nontemporal bit 616@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set 617 618SETP 00 011001110 ..... 00 . . 01 ..... ..... @set 619SETM 00 011001110 ..... 01 . . 01 ..... ..... @set 620SETE 00 011001110 ..... 10 . . 01 ..... ..... @set 621 622# Like SET, but also setting MTE tags 623SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set 624SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set 625SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set 626 627# Memmove/Memcopy: the CPY insns allow overlapping src/dest and 628# copy in the correct direction; the CPYF insns always copy forwards. 629# 630# options has the nontemporal and unpriv bits for src and dest 631&cpy rs rn rd options 632@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy 633 634CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy 635CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy 636CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy 637CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy 638CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy 639CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy 640 641### Cryptographic AES 642 643AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0 644AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0 645AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0 646AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0 647 648### Cryptographic three-register SHA 649 650SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0 651SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0 652SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0 653SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0 654SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0 655SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0 656SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0 657 658### Cryptographic two-register SHA 659 660SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0 661SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0 662SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0 663 664### Cryptographic three-register SHA512 665 666SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0 667SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0 668SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0 669RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3 670SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0 671SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0 672SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0 673 674### Cryptographic two-register SHA512 675 676SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0 677SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0 678 679### Cryptographic four-register 680 681EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3 682BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3 683SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3 684 685### Cryptographic three-register, imm2 686 687&crypto3i rd rn rm imm 688@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i 689 690SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i 691SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i 692SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i 693SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i 694 695### Cryptographic XAR 696 697XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5 698 699### Advanced SIMD scalar copy 700 701DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5 702 703### Advanced SIMD copy 704 705DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5 706DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5 707INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5 708SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5 709UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5 710INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5 711 712### Advanced SIMD scalar three same 713 714FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd 715FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd 716FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd 717FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd 718FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd 719 720FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd 721FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd 722FMAXNM_s 0001 1110 ..1 ..... 0110 10 ..... ..... @rrr_hsd 723FMINNM_s 0001 1110 ..1 ..... 0111 10 ..... ..... @rrr_hsd 724 725FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h 726FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd 727 728FCMEQ_s 0101 1110 010 ..... 00100 1 ..... ..... @rrr_h 729FCMEQ_s 0101 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 730 731FCMGE_s 0111 1110 010 ..... 00100 1 ..... ..... @rrr_h 732FCMGE_s 0111 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 733 734FCMGT_s 0111 1110 110 ..... 00100 1 ..... ..... @rrr_h 735FCMGT_s 0111 1110 1.1 ..... 11100 1 ..... ..... @rrr_sd 736 737FACGE_s 0111 1110 010 ..... 00101 1 ..... ..... @rrr_h 738FACGE_s 0111 1110 0.1 ..... 11101 1 ..... ..... @rrr_sd 739 740FACGT_s 0111 1110 110 ..... 00101 1 ..... ..... @rrr_h 741FACGT_s 0111 1110 1.1 ..... 11101 1 ..... ..... @rrr_sd 742 743FABD_s 0111 1110 110 ..... 00010 1 ..... ..... @rrr_h 744FABD_s 0111 1110 1.1 ..... 11010 1 ..... ..... @rrr_sd 745 746FRECPS_s 0101 1110 010 ..... 00111 1 ..... ..... @rrr_h 747FRECPS_s 0101 1110 0.1 ..... 11111 1 ..... ..... @rrr_sd 748 749FRSQRTS_s 0101 1110 110 ..... 00111 1 ..... ..... @rrr_h 750FRSQRTS_s 0101 1110 1.1 ..... 11111 1 ..... ..... @rrr_sd 751 752SQADD_s 0101 1110 ..1 ..... 00001 1 ..... ..... @rrr_e 753UQADD_s 0111 1110 ..1 ..... 00001 1 ..... ..... @rrr_e 754SQSUB_s 0101 1110 ..1 ..... 00101 1 ..... ..... @rrr_e 755UQSUB_s 0111 1110 ..1 ..... 00101 1 ..... ..... @rrr_e 756 757SUQADD_s 0101 1110 ..1 00000 00111 0 ..... ..... @r2r_e 758USQADD_s 0111 1110 ..1 00000 00111 0 ..... ..... @r2r_e 759 760SSHL_s 0101 1110 111 ..... 01000 1 ..... ..... @rrr_d 761USHL_s 0111 1110 111 ..... 01000 1 ..... ..... @rrr_d 762SRSHL_s 0101 1110 111 ..... 01010 1 ..... ..... @rrr_d 763URSHL_s 0111 1110 111 ..... 01010 1 ..... ..... @rrr_d 764SQSHL_s 0101 1110 ..1 ..... 01001 1 ..... ..... @rrr_e 765UQSHL_s 0111 1110 ..1 ..... 01001 1 ..... ..... @rrr_e 766SQRSHL_s 0101 1110 ..1 ..... 01011 1 ..... ..... @rrr_e 767UQRSHL_s 0111 1110 ..1 ..... 01011 1 ..... ..... @rrr_e 768 769ADD_s 0101 1110 111 ..... 10000 1 ..... ..... @rrr_d 770SUB_s 0111 1110 111 ..... 10000 1 ..... ..... @rrr_d 771CMGT_s 0101 1110 111 ..... 00110 1 ..... ..... @rrr_d 772CMHI_s 0111 1110 111 ..... 00110 1 ..... ..... @rrr_d 773CMGE_s 0101 1110 111 ..... 00111 1 ..... ..... @rrr_d 774CMHS_s 0111 1110 111 ..... 00111 1 ..... ..... @rrr_d 775CMTST_s 0101 1110 111 ..... 10001 1 ..... ..... @rrr_d 776CMEQ_s 0111 1110 111 ..... 10001 1 ..... ..... @rrr_d 777 778SQDMULH_s 0101 1110 ..1 ..... 10110 1 ..... ..... @rrr_e 779SQRDMULH_s 0111 1110 ..1 ..... 10110 1 ..... ..... @rrr_e 780 781### Advanced SIMD scalar pairwise 782 783FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h 784FADDP_s 0111 1110 0.11 0000 1101 10 ..... ..... @rr_sd 785 786FMAXP_s 0101 1110 0011 0000 1111 10 ..... ..... @rr_h 787FMAXP_s 0111 1110 0.11 0000 1111 10 ..... ..... @rr_sd 788 789FMINP_s 0101 1110 1011 0000 1111 10 ..... ..... @rr_h 790FMINP_s 0111 1110 1.11 0000 1111 10 ..... ..... @rr_sd 791 792FMAXNMP_s 0101 1110 0011 0000 1100 10 ..... ..... @rr_h 793FMAXNMP_s 0111 1110 0.11 0000 1100 10 ..... ..... @rr_sd 794 795FMINNMP_s 0101 1110 1011 0000 1100 10 ..... ..... @rr_h 796FMINNMP_s 0111 1110 1.11 0000 1100 10 ..... ..... @rr_sd 797 798ADDP_s 0101 1110 1111 0001 1011 10 ..... ..... @rr_d 799 800### Advanced SIMD three same 801 802FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h 803FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 804 805FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h 806FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 807 808FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h 809FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 810 811FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h 812FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 813 814FMAX_v 0.00 1110 010 ..... 00110 1 ..... ..... @qrrr_h 815FMAX_v 0.00 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 816 817FMIN_v 0.00 1110 110 ..... 00110 1 ..... ..... @qrrr_h 818FMIN_v 0.00 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 819 820FMAXNM_v 0.00 1110 010 ..... 00000 1 ..... ..... @qrrr_h 821FMAXNM_v 0.00 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 822 823FMINNM_v 0.00 1110 110 ..... 00000 1 ..... ..... @qrrr_h 824FMINNM_v 0.00 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 825 826FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h 827FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 828 829FMLA_v 0.00 1110 010 ..... 00001 1 ..... ..... @qrrr_h 830FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd 831 832FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h 833FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd 834 835FMLAL_v 0.00 1110 001 ..... 11101 1 ..... ..... @qrrr_h 836FMLSL_v 0.00 1110 101 ..... 11101 1 ..... ..... @qrrr_h 837FMLAL2_v 0.10 1110 001 ..... 11001 1 ..... ..... @qrrr_h 838FMLSL2_v 0.10 1110 101 ..... 11001 1 ..... ..... @qrrr_h 839 840FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h 841FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 842 843FCMGE_v 0.10 1110 010 ..... 00100 1 ..... ..... @qrrr_h 844FCMGE_v 0.10 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 845 846FCMGT_v 0.10 1110 110 ..... 00100 1 ..... ..... @qrrr_h 847FCMGT_v 0.10 1110 1.1 ..... 11100 1 ..... ..... @qrrr_sd 848 849FACGE_v 0.10 1110 010 ..... 00101 1 ..... ..... @qrrr_h 850FACGE_v 0.10 1110 0.1 ..... 11101 1 ..... ..... @qrrr_sd 851 852FACGT_v 0.10 1110 110 ..... 00101 1 ..... ..... @qrrr_h 853FACGT_v 0.10 1110 1.1 ..... 11101 1 ..... ..... @qrrr_sd 854 855FABD_v 0.10 1110 110 ..... 00010 1 ..... ..... @qrrr_h 856FABD_v 0.10 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 857 858FRECPS_v 0.00 1110 010 ..... 00111 1 ..... ..... @qrrr_h 859FRECPS_v 0.00 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 860 861FRSQRTS_v 0.00 1110 110 ..... 00111 1 ..... ..... @qrrr_h 862FRSQRTS_v 0.00 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd 863 864FADDP_v 0.10 1110 010 ..... 00010 1 ..... ..... @qrrr_h 865FADDP_v 0.10 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 866 867FMAXP_v 0.10 1110 010 ..... 00110 1 ..... ..... @qrrr_h 868FMAXP_v 0.10 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 869 870FMINP_v 0.10 1110 110 ..... 00110 1 ..... ..... @qrrr_h 871FMINP_v 0.10 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 872 873FMAXNMP_v 0.10 1110 010 ..... 00000 1 ..... ..... @qrrr_h 874FMAXNMP_v 0.10 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 875 876FMINNMP_v 0.10 1110 110 ..... 00000 1 ..... ..... @qrrr_h 877FMINNMP_v 0.10 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 878 879ADDP_v 0.00 1110 ..1 ..... 10111 1 ..... ..... @qrrr_e 880SMAXP_v 0.00 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 881SMINP_v 0.00 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 882UMAXP_v 0.10 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 883UMINP_v 0.10 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 884 885AND_v 0.00 1110 001 ..... 00011 1 ..... ..... @qrrr_b 886BIC_v 0.00 1110 011 ..... 00011 1 ..... ..... @qrrr_b 887ORR_v 0.00 1110 101 ..... 00011 1 ..... ..... @qrrr_b 888ORN_v 0.00 1110 111 ..... 00011 1 ..... ..... @qrrr_b 889EOR_v 0.10 1110 001 ..... 00011 1 ..... ..... @qrrr_b 890BSL_v 0.10 1110 011 ..... 00011 1 ..... ..... @qrrr_b 891BIT_v 0.10 1110 101 ..... 00011 1 ..... ..... @qrrr_b 892BIF_v 0.10 1110 111 ..... 00011 1 ..... ..... @qrrr_b 893 894SQADD_v 0.00 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e 895UQADD_v 0.10 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e 896SQSUB_v 0.00 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e 897UQSUB_v 0.10 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e 898 899SUQADD_v 0.00 1110 ..1 00000 00111 0 ..... ..... @qr2r_e 900USQADD_v 0.10 1110 ..1 00000 00111 0 ..... ..... @qr2r_e 901 902SSHL_v 0.00 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e 903USHL_v 0.10 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e 904SRSHL_v 0.00 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e 905URSHL_v 0.10 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e 906SQSHL_v 0.00 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e 907UQSHL_v 0.10 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e 908SQRSHL_v 0.00 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e 909UQRSHL_v 0.10 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e 910 911ADD_v 0.00 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e 912SUB_v 0.10 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e 913CMGT_v 0.00 1110 ..1 ..... 00110 1 ..... ..... @qrrr_e 914CMHI_v 0.10 1110 ..1 ..... 00110 1 ..... ..... @qrrr_e 915CMGE_v 0.00 1110 ..1 ..... 00111 1 ..... ..... @qrrr_e 916CMHS_v 0.10 1110 ..1 ..... 00111 1 ..... ..... @qrrr_e 917CMTST_v 0.00 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e 918CMEQ_v 0.10 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e 919SHADD_v 0.00 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e 920UHADD_v 0.10 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e 921SHSUB_v 0.00 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e 922UHSUB_v 0.10 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e 923SRHADD_v 0.00 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e 924URHADD_v 0.10 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e 925SMAX_v 0.00 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e 926UMAX_v 0.10 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e 927SMIN_v 0.00 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e 928UMIN_v 0.10 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e 929SABD_v 0.00 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e 930UABD_v 0.10 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e 931SABA_v 0.00 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e 932UABA_v 0.10 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e 933MUL_v 0.00 1110 ..1 ..... 10011 1 ..... ..... @qrrr_e 934PMUL_v 0.10 1110 001 ..... 10011 1 ..... ..... @qrrr_b 935MLA_v 0.00 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e 936MLS_v 0.10 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e 937 938SQDMULH_v 0.00 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e 939SQRDMULH_v 0.10 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e 940 941### Advanced SIMD scalar x indexed element 942 943FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 944FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 945FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 946 947FMLA_si 0101 1111 00 .. .... 0001 . 0 ..... ..... @rrx_h 948FMLA_si 0101 1111 10 .. .... 0001 . 0 ..... ..... @rrx_s 949FMLA_si 0101 1111 11 0. .... 0001 . 0 ..... ..... @rrx_d 950 951FMLS_si 0101 1111 00 .. .... 0101 . 0 ..... ..... @rrx_h 952FMLS_si 0101 1111 10 .. .... 0101 . 0 ..... ..... @rrx_s 953FMLS_si 0101 1111 11 0. .... 0101 . 0 ..... ..... @rrx_d 954 955FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 956FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 957FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 958 959SQDMULH_si 0101 1111 01 .. .... 1100 . 0 ..... ..... @rrx_h 960SQDMULH_si 0101 1111 10 .. .... 1100 . 0 ..... ..... @rrx_s 961 962SQRDMULH_si 0101 1111 01 .. .... 1101 . 0 ..... ..... @rrx_h 963SQRDMULH_si 0101 1111 10 . ..... 1101 . 0 ..... ..... @rrx_s 964 965### Advanced SIMD vector x indexed element 966 967FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 968FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 969FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 970 971FMLA_vi 0.00 1111 00 .. .... 0001 . 0 ..... ..... @qrrx_h 972FMLA_vi 0.00 1111 10 . ..... 0001 . 0 ..... ..... @qrrx_s 973FMLA_vi 0.00 1111 11 0 ..... 0001 . 0 ..... ..... @qrrx_d 974 975FMLS_vi 0.00 1111 00 .. .... 0101 . 0 ..... ..... @qrrx_h 976FMLS_vi 0.00 1111 10 . ..... 0101 . 0 ..... ..... @qrrx_s 977FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d 978 979FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 980FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 981FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 982 983FMLAL_vi 0.00 1111 10 .. .... 0000 . 0 ..... ..... @qrrx_h 984FMLSL_vi 0.00 1111 10 .. .... 0100 . 0 ..... ..... @qrrx_h 985FMLAL2_vi 0.10 1111 10 .. .... 1000 . 0 ..... ..... @qrrx_h 986FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h 987 988MUL_vi 0.00 1111 01 .. .... 1000 . 0 ..... ..... @qrrx_h 989MUL_vi 0.00 1111 10 . ..... 1000 . 0 ..... ..... @qrrx_s 990 991MLA_vi 0.10 1111 01 .. .... 0000 . 0 ..... ..... @qrrx_h 992MLA_vi 0.10 1111 10 . ..... 0000 . 0 ..... ..... @qrrx_s 993 994MLS_vi 0.10 1111 01 .. .... 0100 . 0 ..... ..... @qrrx_h 995MLS_vi 0.10 1111 10 . ..... 0100 . 0 ..... ..... @qrrx_s 996 997SQDMULH_vi 0.00 1111 01 .. .... 1100 . 0 ..... ..... @qrrx_h 998SQDMULH_vi 0.00 1111 10 . ..... 1100 . 0 ..... ..... @qrrx_s 999 1000SQRDMULH_vi 0.00 1111 01 .. .... 1101 . 0 ..... ..... @qrrx_h 1001SQRDMULH_vi 0.00 1111 10 . ..... 1101 . 0 ..... ..... @qrrx_s 1002 1003# Floating-point conditional select 1004 1005FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd 1006 1007# Floating-point data-processing (3 source) 1008 1009@rrrr_hsd .... .... .. . rm:5 . ra:5 rn:5 rd:5 &rrrr_e esz=%esz_hsd 1010 1011FMADD 0001 1111 .. 0 ..... 0 ..... ..... ..... @rrrr_hsd 1012FMSUB 0001 1111 .. 0 ..... 1 ..... ..... ..... @rrrr_hsd 1013FNMADD 0001 1111 .. 1 ..... 0 ..... ..... ..... @rrrr_hsd 1014FNMSUB 0001 1111 .. 1 ..... 1 ..... ..... ..... @rrrr_hsd 1015