1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22%rd 0:5 23%esz_sd 22:1 !function=plus_2 24%esz_hsd 22:2 !function=xor_2 25%hl 11:1 21:1 26%hlm 11:1 20:2 27 28&r rn 29&ri rd imm 30&rri_sf rd rn imm sf 31&i imm 32&rr_e rd rn esz 33&rrr_e rd rn rm esz 34&rrx_e rd rn rm idx esz 35&qrr_e q rd rn esz 36&qrrr_e q rd rn rm esz 37&qrrx_e q rd rn rm idx esz 38&qrrrr_e q rd rn rm ra esz 39 40@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1 41@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3 42@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd 43 44@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1 45@rrr_d ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=3 46@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd 47@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd 48@rrr_e ........ esz:2 . rm:5 ...... rn:5 rd:5 &rrr_e 49@r2r_e ........ esz:2 . ..... ...... rm:5 rd:5 &rrr_e rn=%rd 50 51@rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm 52@rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl 53@rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3 54 55@rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0 56@r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0 57@rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0 58@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3 59@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3 60 61@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0 62@qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1 63@qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd 64@qrrr_e . q:1 ...... esz:2 . rm:5 ...... rn:5 rd:5 &qrrr_e 65@qr2r_e . q:1 ...... esz:2 . ..... ...... rm:5 rd:5 &qrrr_e rn=%rd 66 67@qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \ 68 &qrrx_e esz=1 idx=%hlm 69@qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \ 70 &qrrx_e esz=2 idx=%hl 71@qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \ 72 &qrrx_e esz=3 73 74### Data Processing - Immediate 75 76# PC-rel addressing 77 78%imm_pcrel 5:s19 29:2 79@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 80 81ADR 0 .. 10000 ................... ..... @pcrel 82ADRP 1 .. 10000 ................... ..... @pcrel 83 84# Add/subtract (immediate) 85 86%imm12_sh12 10:12 !function=shl_12 87@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 88@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 89 90ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 91ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 92ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 93ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 94 95SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 96SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 97SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 98SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 99 100# Add/subtract (immediate with tags) 101 102&rri_tag rd rn uimm6 uimm4 103@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 104 105ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 106SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 107 108# Logical (immediate) 109 110&rri_log rd rn sf dbm 111@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 112@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 113 114AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 115AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 116ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 117ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 118EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 119EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 120ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 121ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 122 123# Move wide (immediate) 124 125&movw rd sf imm hw 126@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 127@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 128 129MOVN . 00 100101 .. ................ ..... @movw_64 130MOVN . 00 100101 .. ................ ..... @movw_32 131MOVZ . 10 100101 .. ................ ..... @movw_64 132MOVZ . 10 100101 .. ................ ..... @movw_32 133MOVK . 11 100101 .. ................ ..... @movw_64 134MOVK . 11 100101 .. ................ ..... @movw_32 135 136# Bitfield 137 138&bitfield rd rn sf immr imms 139@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 140@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 141 142SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 143SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 144BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 145BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 146UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 147UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 148 149# Extract 150 151&extract rd rn rm imm sf 152 153EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 154EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 155 156# Branches 157 158%imm26 0:s26 !function=times_4 159@branch . ..... .......................... &i imm=%imm26 160 161B 0 00101 .......................... @branch 162BL 1 00101 .......................... @branch 163 164%imm19 5:s19 !function=times_4 165&cbz rt imm sf nz 166 167CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 168 169%imm14 5:s14 !function=times_4 170%imm31_19 31:1 19:5 171&tbz rt imm nz bitpos 172 173TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 174 175# B.cond and BC.cond 176B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19 177 178BR 1101011 0000 11111 000000 rn:5 00000 &r 179BLR 1101011 0001 11111 000000 rn:5 00000 &r 180RET 1101011 0010 11111 000000 rn:5 00000 &r 181 182&braz rn m 183BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 184BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 185 186&reta m 187RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 188 189&bra rn rm m 190BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 191BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 192 193ERET 1101011 0100 11111 000000 11111 00000 194ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 195 196# We don't need to decode DRPS because it always UNDEFs except when 197# the processor is in halting debug state (which we don't implement). 198# The pattern is listed here as documentation. 199# DRPS 1101011 0101 11111 000000 11111 00000 200 201# Hint instruction group 202{ 203 [ 204 YIELD 1101 0101 0000 0011 0010 0000 001 11111 205 WFE 1101 0101 0000 0011 0010 0000 010 11111 206 WFI 1101 0101 0000 0011 0010 0000 011 11111 207 # We implement WFE to never block, so our SEV/SEVL are NOPs 208 # SEV 1101 0101 0000 0011 0010 0000 100 11111 209 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 210 # Our DGL is a NOP because we don't merge memory accesses anyway. 211 # DGL 1101 0101 0000 0011 0010 0000 110 11111 212 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 213 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 214 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 215 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 216 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 217 ESB 1101 0101 0000 0011 0010 0010 000 11111 218 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 219 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 220 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 221 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 222 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 223 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 224 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 225 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 226 ] 227 # The canonical NOP has CRm == op2 == 0, but all of the space 228 # that isn't specifically allocated to an instruction must NOP 229 NOP 1101 0101 0000 0011 0010 ---- --- 11111 230} 231 232# Barriers 233 234CLREX 1101 0101 0000 0011 0011 ---- 010 11111 235DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 236ISB 1101 0101 0000 0011 0011 ---- 110 11111 237SB 1101 0101 0000 0011 0011 0000 111 11111 238 239# PSTATE 240 241CFINV 1101 0101 0000 0 000 0100 0000 000 11111 242XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 243AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 244 245# These are architecturally all "MSR (immediate)"; we decode the destination 246# register too because there is no commonality in our implementation. 247@msr_i .... .... .... . ... .... imm:4 ... ..... 248MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 249MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 250MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 251MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 252MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 253MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 254MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 255MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 256MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 257MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 258 259# MRS, MSR (register), SYS, SYSL. These are all essentially the 260# same instruction as far as QEMU is concerned. 261# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 262# to hand-decode it. 263SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 264SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 265SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 266 267# Exception generation 268 269@i16 .... .... ... imm:16 ... .. &i 270SVC 1101 0100 000 ................ 000 01 @i16 271HVC 1101 0100 000 ................ 000 10 @i16 272SMC 1101 0100 000 ................ 000 11 @i16 273BRK 1101 0100 001 ................ 000 00 @i16 274HLT 1101 0100 010 ................ 000 00 @i16 275# These insns always UNDEF unless in halting debug state, which 276# we don't implement. So we don't need to decode them. The patterns 277# are listed here as documentation. 278# DCPS1 1101 0100 101 ................ 000 01 @i16 279# DCPS2 1101 0100 101 ................ 000 10 @i16 280# DCPS3 1101 0100 101 ................ 000 11 @i16 281 282# Loads and stores 283 284&stxr rn rt rt2 rs sz lasr 285&stlr rn rt sz lasr 286@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 287@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 288%imm1_30_p2 30:1 !function=plus_2 289@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 290STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 291LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 292STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 293LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 294 295STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 296LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 297 298# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 299# acquire/release semantics because QEMU's cmpxchg always has those) 300CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 301# CAS, CASA, CASAL, CASL 302CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 303 304&ldlit rt imm sz sign 305@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 306 307LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 308LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 309LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 310LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 311LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 312LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 313 314# PRFM 315NOP 11 011 0 00 ------------------- ----- 316 317&ldstpair rt2 rt rn imm sz sign w p 318@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 319 320# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 321# so we ignore hints about data access patterns, and handle these like 322# plain signed offset. 323STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 324LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 325STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 326LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 327STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 328LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 329STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 330LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 331STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 332LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 333 334# STP and LDP: post-indexed 335STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 336LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 337LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 338STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 339LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 340STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 341LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 342STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 343LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 344STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 345LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 346 347# STP and LDP: offset 348STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 349LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 350LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 351STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 352LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 353STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 354LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 355STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 356LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 357STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 358LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 359 360# STP and LDP: pre-indexed 361STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 362LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 363LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 364STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 365LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 366STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 367LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 368STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 369LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 370STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 371LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 372 373# STGP: store tag and pair 374STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 375STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 376STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 377 378# Load/store register (unscaled immediate) 379&ldst_imm rt rn imm sz sign w p unpriv ext 380@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 381@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 382@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 383@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 384 385STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 386LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 387LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 388LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 389LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 390LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 391LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 392LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 393LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 394LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 395 396STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 397LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 398LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 399LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 400LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 401LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 402LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 403LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 404LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 405LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 406 407STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 408LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 409LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 410LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 411LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 412LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 413LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 414LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 415LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 416LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 417 418STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 419LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 420LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 421LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 422LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 423LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 424LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 425LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 426LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 427LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 428 429# PRFM : prefetch memory: a no-op for QEMU 430NOP 11 111 0 00 10 0 --------- 00 ----- ----- 431 432STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 433STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 434LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 435LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 436 437STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 438STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 439LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 440LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 441 442STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 443STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 444LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 445LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 446 447# Load/store with an unsigned 12 bit immediate, which is scaled by the 448# element size. The function gets the sz:imm and returns the scaled immediate. 449%uimm_scaled 10:12 sz:3 !function=uimm_scaled 450 451@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 452 453STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 454LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 455LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 456LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 457LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 458LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 459LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 460LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 461LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 462LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 463 464# PRFM 465NOP 11 111 0 01 10 ------------ ----- ----- 466 467STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 468STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 469LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 470LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 471 472# Load/store with register offset 473&ldst rm rn rt sign ext sz opt s 474@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 475STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 476LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 477LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 478LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 479LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 480LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 481LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 482LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 483LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 484LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 485 486# PRFM 487NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 488 489STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 490STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 491LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 492LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 493 494# Atomic memory operations 495&atomic rs rn rt a r sz 496@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 497LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 498LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 499LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 500LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 501LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 502LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 503LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 504LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 505SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 506 507LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 508 509# Load/store register (pointer authentication) 510 511# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 512%ldra_imm 22:s1 12:9 !function=times_8 513 514LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 515 516&ldapr_stlr_i rn rt imm sz sign ext 517@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 518STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 519LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 520LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 521LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 522LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 523LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 524LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 525 526# Load/store multiple structures 527# The 4-bit opcode in [15:12] encodes repeat count and structure elements 528&ldst_mult rm rn rt sz q p rpt selem 529@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 530ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 531ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 532ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 533ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 534ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 535ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 536ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 537 538LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 539LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 540LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 541LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 542LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 543LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 544LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 545 546# Load/store single structure 547&ldst_single rm rn rt p selem index scale 548 549%ldst_single_selem 13:1 21:1 !function=plus_1 550 551%ldst_single_index_b 30:1 10:3 552%ldst_single_index_h 30:1 11:2 553%ldst_single_index_s 30:1 12:1 554 555@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 556 &ldst_single scale=0 selem=%ldst_single_selem \ 557 index=%ldst_single_index_b 558@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 559 &ldst_single scale=1 selem=%ldst_single_selem \ 560 index=%ldst_single_index_h 561@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 562 &ldst_single scale=2 selem=%ldst_single_selem \ 563 index=%ldst_single_index_s 564@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 565 &ldst_single scale=3 selem=%ldst_single_selem 566 567ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 568ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 569ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 570ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 571 572LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 573LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 574LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 575LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 576 577# Replicating load case 578LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 579 580%tag_offset 12:s9 !function=scale_by_log2_tag_granule 581&ldst_tag rn rt imm p w 582@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 583@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 584 585STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 586STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 587STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 588STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 589 590LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 591STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 592STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 593STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 594 595STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 596ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 597ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 598ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 599 600LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 601STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 602STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 603STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 604 605# Memory operations (memset, memcpy, memmove) 606# Each of these comes in a set of three, eg SETP (prologue), SETM (main), 607# SETE (epilogue), and each of those has different flavours to 608# indicate whether memory accesses should be unpriv or non-temporal. 609# We don't distinguish temporal and non-temporal accesses, but we 610# do need to report it in syndrome register values. 611 612# Memset 613&set rs rn rd unpriv nontemp 614# op2 bit 1 is nontemporal bit 615@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set 616 617SETP 00 011001110 ..... 00 . . 01 ..... ..... @set 618SETM 00 011001110 ..... 01 . . 01 ..... ..... @set 619SETE 00 011001110 ..... 10 . . 01 ..... ..... @set 620 621# Like SET, but also setting MTE tags 622SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set 623SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set 624SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set 625 626# Memmove/Memcopy: the CPY insns allow overlapping src/dest and 627# copy in the correct direction; the CPYF insns always copy forwards. 628# 629# options has the nontemporal and unpriv bits for src and dest 630&cpy rs rn rd options 631@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy 632 633CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy 634CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy 635CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy 636CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy 637CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy 638CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy 639 640### Cryptographic AES 641 642AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0 643AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0 644AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0 645AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0 646 647### Cryptographic three-register SHA 648 649SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0 650SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0 651SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0 652SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0 653SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0 654SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0 655SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0 656 657### Cryptographic two-register SHA 658 659SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0 660SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0 661SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0 662 663### Cryptographic three-register SHA512 664 665SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0 666SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0 667SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0 668RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3 669SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0 670SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0 671SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0 672 673### Cryptographic two-register SHA512 674 675SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0 676SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0 677 678### Cryptographic four-register 679 680EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3 681BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3 682SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3 683 684### Cryptographic three-register, imm2 685 686&crypto3i rd rn rm imm 687@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i 688 689SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i 690SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i 691SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i 692SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i 693 694### Cryptographic XAR 695 696XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5 697 698### Advanced SIMD scalar copy 699 700DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5 701 702### Advanced SIMD copy 703 704DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5 705DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5 706INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5 707SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5 708UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5 709INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5 710 711### Advanced SIMD scalar three same 712 713FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd 714FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd 715FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd 716FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd 717FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd 718 719FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd 720FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd 721FMAXNM_s 0001 1110 ..1 ..... 0110 10 ..... ..... @rrr_hsd 722FMINNM_s 0001 1110 ..1 ..... 0111 10 ..... ..... @rrr_hsd 723 724FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h 725FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd 726 727FCMEQ_s 0101 1110 010 ..... 00100 1 ..... ..... @rrr_h 728FCMEQ_s 0101 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 729 730FCMGE_s 0111 1110 010 ..... 00100 1 ..... ..... @rrr_h 731FCMGE_s 0111 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 732 733FCMGT_s 0111 1110 110 ..... 00100 1 ..... ..... @rrr_h 734FCMGT_s 0111 1110 1.1 ..... 11100 1 ..... ..... @rrr_sd 735 736FACGE_s 0111 1110 010 ..... 00101 1 ..... ..... @rrr_h 737FACGE_s 0111 1110 0.1 ..... 11101 1 ..... ..... @rrr_sd 738 739FACGT_s 0111 1110 110 ..... 00101 1 ..... ..... @rrr_h 740FACGT_s 0111 1110 1.1 ..... 11101 1 ..... ..... @rrr_sd 741 742FABD_s 0111 1110 110 ..... 00010 1 ..... ..... @rrr_h 743FABD_s 0111 1110 1.1 ..... 11010 1 ..... ..... @rrr_sd 744 745FRECPS_s 0101 1110 010 ..... 00111 1 ..... ..... @rrr_h 746FRECPS_s 0101 1110 0.1 ..... 11111 1 ..... ..... @rrr_sd 747 748FRSQRTS_s 0101 1110 110 ..... 00111 1 ..... ..... @rrr_h 749FRSQRTS_s 0101 1110 1.1 ..... 11111 1 ..... ..... @rrr_sd 750 751SQADD_s 0101 1110 ..1 ..... 00001 1 ..... ..... @rrr_e 752UQADD_s 0111 1110 ..1 ..... 00001 1 ..... ..... @rrr_e 753SQSUB_s 0101 1110 ..1 ..... 00101 1 ..... ..... @rrr_e 754UQSUB_s 0111 1110 ..1 ..... 00101 1 ..... ..... @rrr_e 755 756SUQADD_s 0101 1110 ..1 00000 00111 0 ..... ..... @r2r_e 757USQADD_s 0111 1110 ..1 00000 00111 0 ..... ..... @r2r_e 758 759SSHL_s 0101 1110 111 ..... 01000 1 ..... ..... @rrr_d 760USHL_s 0111 1110 111 ..... 01000 1 ..... ..... @rrr_d 761SRSHL_s 0101 1110 111 ..... 01010 1 ..... ..... @rrr_d 762URSHL_s 0111 1110 111 ..... 01010 1 ..... ..... @rrr_d 763SQSHL_s 0101 1110 ..1 ..... 01001 1 ..... ..... @rrr_e 764UQSHL_s 0111 1110 ..1 ..... 01001 1 ..... ..... @rrr_e 765SQRSHL_s 0101 1110 ..1 ..... 01011 1 ..... ..... @rrr_e 766UQRSHL_s 0111 1110 ..1 ..... 01011 1 ..... ..... @rrr_e 767 768ADD_s 0101 1110 111 ..... 10000 1 ..... ..... @rrr_d 769SUB_s 0111 1110 111 ..... 10000 1 ..... ..... @rrr_d 770CMGT_s 0101 1110 111 ..... 00110 1 ..... ..... @rrr_d 771CMHI_s 0111 1110 111 ..... 00110 1 ..... ..... @rrr_d 772CMGE_s 0101 1110 111 ..... 00111 1 ..... ..... @rrr_d 773CMHS_s 0111 1110 111 ..... 00111 1 ..... ..... @rrr_d 774CMTST_s 0101 1110 111 ..... 10001 1 ..... ..... @rrr_d 775CMEQ_s 0111 1110 111 ..... 10001 1 ..... ..... @rrr_d 776 777SQDMULH_s 0101 1110 ..1 ..... 10110 1 ..... ..... @rrr_e 778SQRDMULH_s 0111 1110 ..1 ..... 10110 1 ..... ..... @rrr_e 779 780### Advanced SIMD scalar pairwise 781 782FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h 783FADDP_s 0111 1110 0.11 0000 1101 10 ..... ..... @rr_sd 784 785FMAXP_s 0101 1110 0011 0000 1111 10 ..... ..... @rr_h 786FMAXP_s 0111 1110 0.11 0000 1111 10 ..... ..... @rr_sd 787 788FMINP_s 0101 1110 1011 0000 1111 10 ..... ..... @rr_h 789FMINP_s 0111 1110 1.11 0000 1111 10 ..... ..... @rr_sd 790 791FMAXNMP_s 0101 1110 0011 0000 1100 10 ..... ..... @rr_h 792FMAXNMP_s 0111 1110 0.11 0000 1100 10 ..... ..... @rr_sd 793 794FMINNMP_s 0101 1110 1011 0000 1100 10 ..... ..... @rr_h 795FMINNMP_s 0111 1110 1.11 0000 1100 10 ..... ..... @rr_sd 796 797ADDP_s 0101 1110 1111 0001 1011 10 ..... ..... @rr_d 798 799### Advanced SIMD three same 800 801FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h 802FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 803 804FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h 805FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 806 807FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h 808FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 809 810FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h 811FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 812 813FMAX_v 0.00 1110 010 ..... 00110 1 ..... ..... @qrrr_h 814FMAX_v 0.00 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 815 816FMIN_v 0.00 1110 110 ..... 00110 1 ..... ..... @qrrr_h 817FMIN_v 0.00 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 818 819FMAXNM_v 0.00 1110 010 ..... 00000 1 ..... ..... @qrrr_h 820FMAXNM_v 0.00 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 821 822FMINNM_v 0.00 1110 110 ..... 00000 1 ..... ..... @qrrr_h 823FMINNM_v 0.00 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 824 825FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h 826FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 827 828FMLA_v 0.00 1110 010 ..... 00001 1 ..... ..... @qrrr_h 829FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd 830 831FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h 832FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd 833 834FMLAL_v 0.00 1110 001 ..... 11101 1 ..... ..... @qrrr_h 835FMLSL_v 0.00 1110 101 ..... 11101 1 ..... ..... @qrrr_h 836FMLAL2_v 0.10 1110 001 ..... 11001 1 ..... ..... @qrrr_h 837FMLSL2_v 0.10 1110 101 ..... 11001 1 ..... ..... @qrrr_h 838 839FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h 840FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 841 842FCMGE_v 0.10 1110 010 ..... 00100 1 ..... ..... @qrrr_h 843FCMGE_v 0.10 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 844 845FCMGT_v 0.10 1110 110 ..... 00100 1 ..... ..... @qrrr_h 846FCMGT_v 0.10 1110 1.1 ..... 11100 1 ..... ..... @qrrr_sd 847 848FACGE_v 0.10 1110 010 ..... 00101 1 ..... ..... @qrrr_h 849FACGE_v 0.10 1110 0.1 ..... 11101 1 ..... ..... @qrrr_sd 850 851FACGT_v 0.10 1110 110 ..... 00101 1 ..... ..... @qrrr_h 852FACGT_v 0.10 1110 1.1 ..... 11101 1 ..... ..... @qrrr_sd 853 854FABD_v 0.10 1110 110 ..... 00010 1 ..... ..... @qrrr_h 855FABD_v 0.10 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 856 857FRECPS_v 0.00 1110 010 ..... 00111 1 ..... ..... @qrrr_h 858FRECPS_v 0.00 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 859 860FRSQRTS_v 0.00 1110 110 ..... 00111 1 ..... ..... @qrrr_h 861FRSQRTS_v 0.00 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd 862 863FADDP_v 0.10 1110 010 ..... 00010 1 ..... ..... @qrrr_h 864FADDP_v 0.10 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 865 866FMAXP_v 0.10 1110 010 ..... 00110 1 ..... ..... @qrrr_h 867FMAXP_v 0.10 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 868 869FMINP_v 0.10 1110 110 ..... 00110 1 ..... ..... @qrrr_h 870FMINP_v 0.10 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 871 872FMAXNMP_v 0.10 1110 010 ..... 00000 1 ..... ..... @qrrr_h 873FMAXNMP_v 0.10 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 874 875FMINNMP_v 0.10 1110 110 ..... 00000 1 ..... ..... @qrrr_h 876FMINNMP_v 0.10 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 877 878ADDP_v 0.00 1110 ..1 ..... 10111 1 ..... ..... @qrrr_e 879SMAXP_v 0.00 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 880SMINP_v 0.00 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 881UMAXP_v 0.10 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 882UMINP_v 0.10 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 883 884AND_v 0.00 1110 001 ..... 00011 1 ..... ..... @qrrr_b 885BIC_v 0.00 1110 011 ..... 00011 1 ..... ..... @qrrr_b 886ORR_v 0.00 1110 101 ..... 00011 1 ..... ..... @qrrr_b 887ORN_v 0.00 1110 111 ..... 00011 1 ..... ..... @qrrr_b 888EOR_v 0.10 1110 001 ..... 00011 1 ..... ..... @qrrr_b 889BSL_v 0.10 1110 011 ..... 00011 1 ..... ..... @qrrr_b 890BIT_v 0.10 1110 101 ..... 00011 1 ..... ..... @qrrr_b 891BIF_v 0.10 1110 111 ..... 00011 1 ..... ..... @qrrr_b 892 893SQADD_v 0.00 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e 894UQADD_v 0.10 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e 895SQSUB_v 0.00 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e 896UQSUB_v 0.10 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e 897 898SUQADD_v 0.00 1110 ..1 00000 00111 0 ..... ..... @qr2r_e 899USQADD_v 0.10 1110 ..1 00000 00111 0 ..... ..... @qr2r_e 900 901SSHL_v 0.00 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e 902USHL_v 0.10 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e 903SRSHL_v 0.00 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e 904URSHL_v 0.10 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e 905SQSHL_v 0.00 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e 906UQSHL_v 0.10 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e 907SQRSHL_v 0.00 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e 908UQRSHL_v 0.10 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e 909 910ADD_v 0.00 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e 911SUB_v 0.10 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e 912CMGT_v 0.00 1110 ..1 ..... 00110 1 ..... ..... @qrrr_e 913CMHI_v 0.10 1110 ..1 ..... 00110 1 ..... ..... @qrrr_e 914CMGE_v 0.00 1110 ..1 ..... 00111 1 ..... ..... @qrrr_e 915CMHS_v 0.10 1110 ..1 ..... 00111 1 ..... ..... @qrrr_e 916CMTST_v 0.00 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e 917CMEQ_v 0.10 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e 918SHADD_v 0.00 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e 919UHADD_v 0.10 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e 920SHSUB_v 0.00 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e 921UHSUB_v 0.10 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e 922SRHADD_v 0.00 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e 923URHADD_v 0.10 1110 ..1 ..... 00010 1 ..... ..... @qrrr_e 924SMAX_v 0.00 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e 925UMAX_v 0.10 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e 926SMIN_v 0.00 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e 927UMIN_v 0.10 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e 928SABD_v 0.00 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e 929UABD_v 0.10 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e 930SABA_v 0.00 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e 931UABA_v 0.10 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e 932MUL_v 0.00 1110 ..1 ..... 10011 1 ..... ..... @qrrr_e 933PMUL_v 0.10 1110 001 ..... 10011 1 ..... ..... @qrrr_b 934MLA_v 0.00 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e 935MLS_v 0.10 1110 ..1 ..... 10010 1 ..... ..... @qrrr_e 936 937SQDMULH_v 0.00 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e 938SQRDMULH_v 0.10 1110 ..1 ..... 10110 1 ..... ..... @qrrr_e 939 940### Advanced SIMD scalar x indexed element 941 942FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 943FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 944FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 945 946FMLA_si 0101 1111 00 .. .... 0001 . 0 ..... ..... @rrx_h 947FMLA_si 0101 1111 10 .. .... 0001 . 0 ..... ..... @rrx_s 948FMLA_si 0101 1111 11 0. .... 0001 . 0 ..... ..... @rrx_d 949 950FMLS_si 0101 1111 00 .. .... 0101 . 0 ..... ..... @rrx_h 951FMLS_si 0101 1111 10 .. .... 0101 . 0 ..... ..... @rrx_s 952FMLS_si 0101 1111 11 0. .... 0101 . 0 ..... ..... @rrx_d 953 954FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 955FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 956FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 957 958SQDMULH_si 0101 1111 01 .. .... 1100 . 0 ..... ..... @rrx_h 959SQDMULH_si 0101 1111 10 .. .... 1100 . 0 ..... ..... @rrx_s 960 961SQRDMULH_si 0101 1111 01 .. .... 1101 . 0 ..... ..... @rrx_h 962SQRDMULH_si 0101 1111 10 . ..... 1101 . 0 ..... ..... @rrx_s 963 964### Advanced SIMD vector x indexed element 965 966FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 967FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 968FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 969 970FMLA_vi 0.00 1111 00 .. .... 0001 . 0 ..... ..... @qrrx_h 971FMLA_vi 0.00 1111 10 . ..... 0001 . 0 ..... ..... @qrrx_s 972FMLA_vi 0.00 1111 11 0 ..... 0001 . 0 ..... ..... @qrrx_d 973 974FMLS_vi 0.00 1111 00 .. .... 0101 . 0 ..... ..... @qrrx_h 975FMLS_vi 0.00 1111 10 . ..... 0101 . 0 ..... ..... @qrrx_s 976FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d 977 978FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 979FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 980FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 981 982FMLAL_vi 0.00 1111 10 .. .... 0000 . 0 ..... ..... @qrrx_h 983FMLSL_vi 0.00 1111 10 .. .... 0100 . 0 ..... ..... @qrrx_h 984FMLAL2_vi 0.10 1111 10 .. .... 1000 . 0 ..... ..... @qrrx_h 985FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h 986 987MUL_vi 0.00 1111 01 .. .... 1000 . 0 ..... ..... @qrrx_h 988MUL_vi 0.00 1111 10 . ..... 1000 . 0 ..... ..... @qrrx_s 989 990MLA_vi 0.10 1111 01 .. .... 0000 . 0 ..... ..... @qrrx_h 991MLA_vi 0.10 1111 10 . ..... 0000 . 0 ..... ..... @qrrx_s 992 993MLS_vi 0.10 1111 01 .. .... 0100 . 0 ..... ..... @qrrx_h 994MLS_vi 0.10 1111 10 . ..... 0100 . 0 ..... ..... @qrrx_s 995 996SQDMULH_vi 0.00 1111 01 .. .... 1100 . 0 ..... ..... @qrrx_h 997SQDMULH_vi 0.00 1111 10 . ..... 1100 . 0 ..... ..... @qrrx_s 998 999SQRDMULH_vi 0.00 1111 01 .. .... 1101 . 0 ..... ..... @qrrx_h 1000SQRDMULH_vi 0.00 1111 10 . ..... 1101 . 0 ..... ..... @qrrx_s 1001