1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22%rd 0:5 23%esz_sd 22:1 !function=plus_2 24%hl 11:1 21:1 25%hlm 11:1 20:2 26 27&r rn 28&ri rd imm 29&rri_sf rd rn imm sf 30&i imm 31&rrr_e rd rn rm esz 32&rrx_e rd rn rm idx esz 33&qrr_e q rd rn esz 34&qrrr_e q rd rn rm esz 35&qrrx_e q rd rn rm idx esz 36&qrrrr_e q rd rn rm ra esz 37 38@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1 39@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd 40 41@rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm 42@rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl 43@rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3 44 45@rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0 46@r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0 47@rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0 48@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3 49@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3 50 51@qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1 52@qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd 53 54@qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \ 55 &qrrx_e esz=1 idx=%hlm 56@qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \ 57 &qrrx_e esz=2 idx=%hl 58@qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \ 59 &qrrx_e esz=3 60 61### Data Processing - Immediate 62 63# PC-rel addressing 64 65%imm_pcrel 5:s19 29:2 66@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 67 68ADR 0 .. 10000 ................... ..... @pcrel 69ADRP 1 .. 10000 ................... ..... @pcrel 70 71# Add/subtract (immediate) 72 73%imm12_sh12 10:12 !function=shl_12 74@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 75@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 76 77ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 78ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 79ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 80ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 81 82SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 83SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 84SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 85SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 86 87# Add/subtract (immediate with tags) 88 89&rri_tag rd rn uimm6 uimm4 90@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 91 92ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 93SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 94 95# Logical (immediate) 96 97&rri_log rd rn sf dbm 98@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 99@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 100 101AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 102AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 103ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 104ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 105EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 106EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 107ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 108ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 109 110# Move wide (immediate) 111 112&movw rd sf imm hw 113@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 114@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 115 116MOVN . 00 100101 .. ................ ..... @movw_64 117MOVN . 00 100101 .. ................ ..... @movw_32 118MOVZ . 10 100101 .. ................ ..... @movw_64 119MOVZ . 10 100101 .. ................ ..... @movw_32 120MOVK . 11 100101 .. ................ ..... @movw_64 121MOVK . 11 100101 .. ................ ..... @movw_32 122 123# Bitfield 124 125&bitfield rd rn sf immr imms 126@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 127@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 128 129SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 130SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 131BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 132BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 133UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 134UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 135 136# Extract 137 138&extract rd rn rm imm sf 139 140EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 141EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 142 143# Branches 144 145%imm26 0:s26 !function=times_4 146@branch . ..... .......................... &i imm=%imm26 147 148B 0 00101 .......................... @branch 149BL 1 00101 .......................... @branch 150 151%imm19 5:s19 !function=times_4 152&cbz rt imm sf nz 153 154CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 155 156%imm14 5:s14 !function=times_4 157%imm31_19 31:1 19:5 158&tbz rt imm nz bitpos 159 160TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 161 162# B.cond and BC.cond 163B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19 164 165BR 1101011 0000 11111 000000 rn:5 00000 &r 166BLR 1101011 0001 11111 000000 rn:5 00000 &r 167RET 1101011 0010 11111 000000 rn:5 00000 &r 168 169&braz rn m 170BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 171BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 172 173&reta m 174RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 175 176&bra rn rm m 177BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 178BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 179 180ERET 1101011 0100 11111 000000 11111 00000 181ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 182 183# We don't need to decode DRPS because it always UNDEFs except when 184# the processor is in halting debug state (which we don't implement). 185# The pattern is listed here as documentation. 186# DRPS 1101011 0101 11111 000000 11111 00000 187 188# Hint instruction group 189{ 190 [ 191 YIELD 1101 0101 0000 0011 0010 0000 001 11111 192 WFE 1101 0101 0000 0011 0010 0000 010 11111 193 WFI 1101 0101 0000 0011 0010 0000 011 11111 194 # We implement WFE to never block, so our SEV/SEVL are NOPs 195 # SEV 1101 0101 0000 0011 0010 0000 100 11111 196 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 197 # Our DGL is a NOP because we don't merge memory accesses anyway. 198 # DGL 1101 0101 0000 0011 0010 0000 110 11111 199 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 200 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 201 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 202 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 203 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 204 ESB 1101 0101 0000 0011 0010 0010 000 11111 205 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 206 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 207 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 208 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 209 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 210 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 211 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 212 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 213 ] 214 # The canonical NOP has CRm == op2 == 0, but all of the space 215 # that isn't specifically allocated to an instruction must NOP 216 NOP 1101 0101 0000 0011 0010 ---- --- 11111 217} 218 219# Barriers 220 221CLREX 1101 0101 0000 0011 0011 ---- 010 11111 222DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 223ISB 1101 0101 0000 0011 0011 ---- 110 11111 224SB 1101 0101 0000 0011 0011 0000 111 11111 225 226# PSTATE 227 228CFINV 1101 0101 0000 0 000 0100 0000 000 11111 229XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 230AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 231 232# These are architecturally all "MSR (immediate)"; we decode the destination 233# register too because there is no commonality in our implementation. 234@msr_i .... .... .... . ... .... imm:4 ... ..... 235MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 236MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 237MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 238MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 239MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 240MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 241MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 242MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 243MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 244MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 245 246# MRS, MSR (register), SYS, SYSL. These are all essentially the 247# same instruction as far as QEMU is concerned. 248# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 249# to hand-decode it. 250SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 251SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 252SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 253 254# Exception generation 255 256@i16 .... .... ... imm:16 ... .. &i 257SVC 1101 0100 000 ................ 000 01 @i16 258HVC 1101 0100 000 ................ 000 10 @i16 259SMC 1101 0100 000 ................ 000 11 @i16 260BRK 1101 0100 001 ................ 000 00 @i16 261HLT 1101 0100 010 ................ 000 00 @i16 262# These insns always UNDEF unless in halting debug state, which 263# we don't implement. So we don't need to decode them. The patterns 264# are listed here as documentation. 265# DCPS1 1101 0100 101 ................ 000 01 @i16 266# DCPS2 1101 0100 101 ................ 000 10 @i16 267# DCPS3 1101 0100 101 ................ 000 11 @i16 268 269# Loads and stores 270 271&stxr rn rt rt2 rs sz lasr 272&stlr rn rt sz lasr 273@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 274@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 275%imm1_30_p2 30:1 !function=plus_2 276@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 277STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 278LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 279STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 280LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 281 282STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 283LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 284 285# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 286# acquire/release semantics because QEMU's cmpxchg always has those) 287CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 288# CAS, CASA, CASAL, CASL 289CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 290 291&ldlit rt imm sz sign 292@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 293 294LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 295LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 296LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 297LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 298LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 299LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 300 301# PRFM 302NOP 11 011 0 00 ------------------- ----- 303 304&ldstpair rt2 rt rn imm sz sign w p 305@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 306 307# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 308# so we ignore hints about data access patterns, and handle these like 309# plain signed offset. 310STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 311LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 312STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 313LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 314STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 315LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 316STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 317LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 318STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 319LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 320 321# STP and LDP: post-indexed 322STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 323LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 324LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 325STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 326LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 327STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 328LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 329STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 330LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 331STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 332LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 333 334# STP and LDP: offset 335STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 336LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 337LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 338STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 339LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 340STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 341LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 342STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 343LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 344STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 345LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 346 347# STP and LDP: pre-indexed 348STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 349LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 350LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 351STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 352LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 353STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 354LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 355STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 356LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 357STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 358LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 359 360# STGP: store tag and pair 361STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 362STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 363STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 364 365# Load/store register (unscaled immediate) 366&ldst_imm rt rn imm sz sign w p unpriv ext 367@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 368@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 369@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 370@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 371 372STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 373LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 374LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 375LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 376LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 377LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 378LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 379LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 380LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 381LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 382 383STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 384LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 385LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 386LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 387LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 388LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 389LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 390LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 391LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 392LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 393 394STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 395LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 396LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 397LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 398LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 399LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 400LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 401LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 402LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 403LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 404 405STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 406LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 407LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 408LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 409LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 410LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 411LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 412LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 413LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 414LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 415 416# PRFM : prefetch memory: a no-op for QEMU 417NOP 11 111 0 00 10 0 --------- 00 ----- ----- 418 419STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 420STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 421LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 422LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 423 424STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 425STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 426LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 427LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 428 429STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 430STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 431LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 432LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 433 434# Load/store with an unsigned 12 bit immediate, which is scaled by the 435# element size. The function gets the sz:imm and returns the scaled immediate. 436%uimm_scaled 10:12 sz:3 !function=uimm_scaled 437 438@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 439 440STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 441LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 442LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 443LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 444LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 445LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 446LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 447LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 448LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 449LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 450 451# PRFM 452NOP 11 111 0 01 10 ------------ ----- ----- 453 454STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 455STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 456LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 457LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 458 459# Load/store with register offset 460&ldst rm rn rt sign ext sz opt s 461@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 462STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 463LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 464LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 465LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 466LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 467LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 468LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 469LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 470LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 471LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 472 473# PRFM 474NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 475 476STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 477STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 478LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 479LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 480 481# Atomic memory operations 482&atomic rs rn rt a r sz 483@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 484LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 485LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 486LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 487LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 488LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 489LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 490LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 491LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 492SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 493 494LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 495 496# Load/store register (pointer authentication) 497 498# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 499%ldra_imm 22:s1 12:9 !function=times_8 500 501LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 502 503&ldapr_stlr_i rn rt imm sz sign ext 504@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 505STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 506LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 507LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 508LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 509LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 510LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 511LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 512 513# Load/store multiple structures 514# The 4-bit opcode in [15:12] encodes repeat count and structure elements 515&ldst_mult rm rn rt sz q p rpt selem 516@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 517ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 518ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 519ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 520ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 521ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 522ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 523ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 524 525LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 526LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 527LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 528LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 529LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 530LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 531LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 532 533# Load/store single structure 534&ldst_single rm rn rt p selem index scale 535 536%ldst_single_selem 13:1 21:1 !function=plus_1 537 538%ldst_single_index_b 30:1 10:3 539%ldst_single_index_h 30:1 11:2 540%ldst_single_index_s 30:1 12:1 541 542@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 543 &ldst_single scale=0 selem=%ldst_single_selem \ 544 index=%ldst_single_index_b 545@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 546 &ldst_single scale=1 selem=%ldst_single_selem \ 547 index=%ldst_single_index_h 548@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 549 &ldst_single scale=2 selem=%ldst_single_selem \ 550 index=%ldst_single_index_s 551@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 552 &ldst_single scale=3 selem=%ldst_single_selem 553 554ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 555ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 556ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 557ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 558 559LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 560LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 561LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 562LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 563 564# Replicating load case 565LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 566 567%tag_offset 12:s9 !function=scale_by_log2_tag_granule 568&ldst_tag rn rt imm p w 569@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 570@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 571 572STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 573STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 574STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 575STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 576 577LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 578STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 579STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 580STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 581 582STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 583ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 584ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 585ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 586 587LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 588STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 589STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 590STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 591 592# Memory operations (memset, memcpy, memmove) 593# Each of these comes in a set of three, eg SETP (prologue), SETM (main), 594# SETE (epilogue), and each of those has different flavours to 595# indicate whether memory accesses should be unpriv or non-temporal. 596# We don't distinguish temporal and non-temporal accesses, but we 597# do need to report it in syndrome register values. 598 599# Memset 600&set rs rn rd unpriv nontemp 601# op2 bit 1 is nontemporal bit 602@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set 603 604SETP 00 011001110 ..... 00 . . 01 ..... ..... @set 605SETM 00 011001110 ..... 01 . . 01 ..... ..... @set 606SETE 00 011001110 ..... 10 . . 01 ..... ..... @set 607 608# Like SET, but also setting MTE tags 609SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set 610SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set 611SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set 612 613# Memmove/Memcopy: the CPY insns allow overlapping src/dest and 614# copy in the correct direction; the CPYF insns always copy forwards. 615# 616# options has the nontemporal and unpriv bits for src and dest 617&cpy rs rn rd options 618@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy 619 620CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy 621CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy 622CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy 623CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy 624CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy 625CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy 626 627### Cryptographic AES 628 629AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0 630AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0 631AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0 632AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0 633 634### Cryptographic three-register SHA 635 636SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0 637SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0 638SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0 639SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0 640SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0 641SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0 642SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0 643 644### Cryptographic two-register SHA 645 646SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0 647SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0 648SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0 649 650### Cryptographic three-register SHA512 651 652SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0 653SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0 654SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0 655RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3 656SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0 657SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0 658SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0 659 660### Cryptographic two-register SHA512 661 662SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0 663SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0 664 665### Cryptographic four-register 666 667EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3 668BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3 669SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3 670 671### Cryptographic three-register, imm2 672 673&crypto3i rd rn rm imm 674@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i 675 676SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i 677SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i 678SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i 679SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i 680 681### Cryptographic XAR 682 683XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5 684 685### Advanced SIMD scalar copy 686 687DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5 688 689### Advanced SIMD copy 690 691DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5 692DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5 693INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5 694SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5 695UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5 696INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5 697 698### Advanced SIMD scalar three same 699 700FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h 701FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd 702 703### Advanced SIMD three same 704 705FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h 706FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 707 708### Advanced SIMD scalar x indexed element 709 710FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 711FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 712FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 713 714### Advanced SIMD vector x indexed element 715 716FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 717FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 718FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 719