1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22%rd 0:5 23%esz_sd 22:1 !function=plus_2 24%esz_hsd 22:2 !function=xor_2 25%hl 11:1 21:1 26%hlm 11:1 20:2 27 28&r rn 29&ri rd imm 30&rri_sf rd rn imm sf 31&i imm 32&rr_e rd rn esz 33&rrr_e rd rn rm esz 34&rrx_e rd rn rm idx esz 35&qrr_e q rd rn esz 36&qrrr_e q rd rn rm esz 37&qrrx_e q rd rn rm idx esz 38&qrrrr_e q rd rn rm ra esz 39 40@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1 41@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3 42@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd 43 44@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1 45@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd 46@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd 47 48@rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm 49@rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl 50@rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3 51 52@rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0 53@r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0 54@rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0 55@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3 56@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3 57 58@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0 59@qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1 60@qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd 61@qrrr_e . q:1 ...... esz:2 . rm:5 ...... rn:5 rd:5 &qrrr_e 62 63@qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \ 64 &qrrx_e esz=1 idx=%hlm 65@qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \ 66 &qrrx_e esz=2 idx=%hl 67@qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \ 68 &qrrx_e esz=3 69 70### Data Processing - Immediate 71 72# PC-rel addressing 73 74%imm_pcrel 5:s19 29:2 75@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 76 77ADR 0 .. 10000 ................... ..... @pcrel 78ADRP 1 .. 10000 ................... ..... @pcrel 79 80# Add/subtract (immediate) 81 82%imm12_sh12 10:12 !function=shl_12 83@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 84@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 85 86ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 87ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 88ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 89ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 90 91SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 92SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 93SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 94SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 95 96# Add/subtract (immediate with tags) 97 98&rri_tag rd rn uimm6 uimm4 99@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 100 101ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 102SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 103 104# Logical (immediate) 105 106&rri_log rd rn sf dbm 107@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 108@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 109 110AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 111AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 112ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 113ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 114EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 115EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 116ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 117ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 118 119# Move wide (immediate) 120 121&movw rd sf imm hw 122@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 123@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 124 125MOVN . 00 100101 .. ................ ..... @movw_64 126MOVN . 00 100101 .. ................ ..... @movw_32 127MOVZ . 10 100101 .. ................ ..... @movw_64 128MOVZ . 10 100101 .. ................ ..... @movw_32 129MOVK . 11 100101 .. ................ ..... @movw_64 130MOVK . 11 100101 .. ................ ..... @movw_32 131 132# Bitfield 133 134&bitfield rd rn sf immr imms 135@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 136@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 137 138SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 139SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 140BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 141BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 142UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 143UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 144 145# Extract 146 147&extract rd rn rm imm sf 148 149EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 150EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 151 152# Branches 153 154%imm26 0:s26 !function=times_4 155@branch . ..... .......................... &i imm=%imm26 156 157B 0 00101 .......................... @branch 158BL 1 00101 .......................... @branch 159 160%imm19 5:s19 !function=times_4 161&cbz rt imm sf nz 162 163CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 164 165%imm14 5:s14 !function=times_4 166%imm31_19 31:1 19:5 167&tbz rt imm nz bitpos 168 169TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 170 171# B.cond and BC.cond 172B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19 173 174BR 1101011 0000 11111 000000 rn:5 00000 &r 175BLR 1101011 0001 11111 000000 rn:5 00000 &r 176RET 1101011 0010 11111 000000 rn:5 00000 &r 177 178&braz rn m 179BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 180BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 181 182&reta m 183RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 184 185&bra rn rm m 186BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 187BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 188 189ERET 1101011 0100 11111 000000 11111 00000 190ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 191 192# We don't need to decode DRPS because it always UNDEFs except when 193# the processor is in halting debug state (which we don't implement). 194# The pattern is listed here as documentation. 195# DRPS 1101011 0101 11111 000000 11111 00000 196 197# Hint instruction group 198{ 199 [ 200 YIELD 1101 0101 0000 0011 0010 0000 001 11111 201 WFE 1101 0101 0000 0011 0010 0000 010 11111 202 WFI 1101 0101 0000 0011 0010 0000 011 11111 203 # We implement WFE to never block, so our SEV/SEVL are NOPs 204 # SEV 1101 0101 0000 0011 0010 0000 100 11111 205 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 206 # Our DGL is a NOP because we don't merge memory accesses anyway. 207 # DGL 1101 0101 0000 0011 0010 0000 110 11111 208 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 209 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 210 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 211 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 212 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 213 ESB 1101 0101 0000 0011 0010 0010 000 11111 214 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 215 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 216 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 217 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 218 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 219 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 220 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 221 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 222 ] 223 # The canonical NOP has CRm == op2 == 0, but all of the space 224 # that isn't specifically allocated to an instruction must NOP 225 NOP 1101 0101 0000 0011 0010 ---- --- 11111 226} 227 228# Barriers 229 230CLREX 1101 0101 0000 0011 0011 ---- 010 11111 231DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 232ISB 1101 0101 0000 0011 0011 ---- 110 11111 233SB 1101 0101 0000 0011 0011 0000 111 11111 234 235# PSTATE 236 237CFINV 1101 0101 0000 0 000 0100 0000 000 11111 238XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 239AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 240 241# These are architecturally all "MSR (immediate)"; we decode the destination 242# register too because there is no commonality in our implementation. 243@msr_i .... .... .... . ... .... imm:4 ... ..... 244MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 245MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 246MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 247MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 248MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 249MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 250MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 251MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 252MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111 253MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 254 255# MRS, MSR (register), SYS, SYSL. These are all essentially the 256# same instruction as far as QEMU is concerned. 257# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 258# to hand-decode it. 259SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 260SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 261SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 262 263# Exception generation 264 265@i16 .... .... ... imm:16 ... .. &i 266SVC 1101 0100 000 ................ 000 01 @i16 267HVC 1101 0100 000 ................ 000 10 @i16 268SMC 1101 0100 000 ................ 000 11 @i16 269BRK 1101 0100 001 ................ 000 00 @i16 270HLT 1101 0100 010 ................ 000 00 @i16 271# These insns always UNDEF unless in halting debug state, which 272# we don't implement. So we don't need to decode them. The patterns 273# are listed here as documentation. 274# DCPS1 1101 0100 101 ................ 000 01 @i16 275# DCPS2 1101 0100 101 ................ 000 10 @i16 276# DCPS3 1101 0100 101 ................ 000 11 @i16 277 278# Loads and stores 279 280&stxr rn rt rt2 rs sz lasr 281&stlr rn rt sz lasr 282@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr 283@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr 284%imm1_30_p2 30:1 !function=plus_2 285@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2 286STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR 287LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR 288STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR 289LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR 290 291STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP 292LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP 293 294# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine 295# acquire/release semantics because QEMU's cmpxchg always has those) 296CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2 297# CAS, CASA, CASAL, CASL 298CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 299 300&ldlit rt imm sz sign 301@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19 302 303LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0 304LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0 305LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1 306LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0 307LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0 308LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0 309 310# PRFM 311NOP 11 011 0 00 ------------------- ----- 312 313&ldstpair rt2 rt rn imm sz sign w p 314@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair 315 316# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches 317# so we ignore hints about data access patterns, and handle these like 318# plain signed offset. 319STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 320LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 321STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 322LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 323STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 324LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 325STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 326LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 327STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 328LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 329 330# STP and LDP: post-indexed 331STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 332LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 333LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1 334STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 335LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 336STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 337LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1 338STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 339LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 340STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 341LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1 342 343# STP and LDP: offset 344STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 345LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 346LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0 347STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 348LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 349STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 350LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0 351STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 352LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 353STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 354LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0 355 356# STP and LDP: pre-indexed 357STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 358LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 359LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1 360STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 361LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 362STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 363LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1 364STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 365LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 366STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 367LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1 368 369# STGP: store tag and pair 370STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1 371STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0 372STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1 373 374# Load/store register (unscaled immediate) 375&ldst_imm rt rn imm sz sign w p unpriv ext 376@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 377@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1 378@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1 379@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0 380 381STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 382LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0 383LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1 384LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2 385LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3 386LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0 387LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1 388LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2 389LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0 390LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1 391 392STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 393LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0 394LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1 395LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2 396LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3 397LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0 398LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1 399LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2 400LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0 401LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1 402 403STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 404LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0 405LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1 406LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2 407LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3 408LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0 409LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1 410LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2 411LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0 412LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1 413 414STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 415LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0 416LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1 417LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2 418LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3 419LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0 420LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1 421LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2 422LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0 423LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1 424 425# PRFM : prefetch memory: a no-op for QEMU 426NOP 11 111 0 00 10 0 --------- 00 ----- ----- 427 428STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 429STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 430LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 431LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4 432 433STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 434STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 435LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 436LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4 437 438STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 439STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 440LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 441LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4 442 443# Load/store with an unsigned 12 bit immediate, which is scaled by the 444# element size. The function gets the sz:imm and returns the scaled immediate. 445%uimm_scaled 10:12 sz:3 !function=uimm_scaled 446 447@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled 448 449STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 450LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0 451LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1 452LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2 453LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3 454LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0 455LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1 456LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2 457LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0 458LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1 459 460# PRFM 461NOP 11 111 0 01 10 ------------ ----- ----- 462 463STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0 464STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 465LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 466LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4 467 468# Load/store with register offset 469&ldst rm rn rt sign ext sz opt s 470@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst 471STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 472LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0 473LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1 474LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2 475LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3 476LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0 477LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1 478LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2 479LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0 480LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1 481 482# PRFM 483NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- 484 485STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 486STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 487LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 488LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4 489 490# Atomic memory operations 491&atomic rs rn rt a r sz 492@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic 493LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic 494LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic 495LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic 496LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic 497LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic 498LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic 499LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic 500LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic 501SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic 502 503LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 504 505# Load/store register (pointer authentication) 506 507# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous 508%ldra_imm 22:s1 12:9 !function=times_8 509 510LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm 511 512&ldapr_stlr_i rn rt imm sz sign ext 513@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i 514STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 515LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0 516LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0 517LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1 518LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2 519LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0 520LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1 521 522# Load/store multiple structures 523# The 4-bit opcode in [15:12] encodes repeat count and structure elements 524&ldst_mult rm rn rt sz q p rpt selem 525@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult 526ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 527ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 528ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 529ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 530ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 531ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 532ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 533 534LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4 535LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1 536LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3 537LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1 538LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1 539LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2 540LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1 541 542# Load/store single structure 543&ldst_single rm rn rt p selem index scale 544 545%ldst_single_selem 13:1 21:1 !function=plus_1 546 547%ldst_single_index_b 30:1 10:3 548%ldst_single_index_h 30:1 11:2 549%ldst_single_index_s 30:1 12:1 550 551@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 552 &ldst_single scale=0 selem=%ldst_single_selem \ 553 index=%ldst_single_index_b 554@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 555 &ldst_single scale=1 selem=%ldst_single_selem \ 556 index=%ldst_single_index_h 557@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 558 &ldst_single scale=2 selem=%ldst_single_selem \ 559 index=%ldst_single_index_s 560@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ 561 &ldst_single scale=3 selem=%ldst_single_selem 562 563ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b 564ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h 565ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s 566ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d 567 568LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b 569LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h 570LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s 571LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d 572 573# Replicating load case 574LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem 575 576%tag_offset 12:s9 !function=scale_by_log2_tag_granule 577&ldst_tag rn rt imm p w 578@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset 579@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0 580 581STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 582STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 583STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 584STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 585 586LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0 587STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 588STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 589STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 590 591STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 592ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 593ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 594ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 595 596LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0 597STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1 598STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0 599STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1 600 601# Memory operations (memset, memcpy, memmove) 602# Each of these comes in a set of three, eg SETP (prologue), SETM (main), 603# SETE (epilogue), and each of those has different flavours to 604# indicate whether memory accesses should be unpriv or non-temporal. 605# We don't distinguish temporal and non-temporal accesses, but we 606# do need to report it in syndrome register values. 607 608# Memset 609&set rs rn rd unpriv nontemp 610# op2 bit 1 is nontemporal bit 611@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set 612 613SETP 00 011001110 ..... 00 . . 01 ..... ..... @set 614SETM 00 011001110 ..... 01 . . 01 ..... ..... @set 615SETE 00 011001110 ..... 10 . . 01 ..... ..... @set 616 617# Like SET, but also setting MTE tags 618SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set 619SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set 620SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set 621 622# Memmove/Memcopy: the CPY insns allow overlapping src/dest and 623# copy in the correct direction; the CPYF insns always copy forwards. 624# 625# options has the nontemporal and unpriv bits for src and dest 626&cpy rs rn rd options 627@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy 628 629CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy 630CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy 631CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy 632CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy 633CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy 634CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy 635 636### Cryptographic AES 637 638AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0 639AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0 640AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0 641AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0 642 643### Cryptographic three-register SHA 644 645SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0 646SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0 647SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0 648SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0 649SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0 650SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0 651SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0 652 653### Cryptographic two-register SHA 654 655SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0 656SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0 657SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0 658 659### Cryptographic three-register SHA512 660 661SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0 662SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0 663SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0 664RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3 665SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0 666SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0 667SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0 668 669### Cryptographic two-register SHA512 670 671SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0 672SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0 673 674### Cryptographic four-register 675 676EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3 677BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3 678SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3 679 680### Cryptographic three-register, imm2 681 682&crypto3i rd rn rm imm 683@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i 684 685SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i 686SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i 687SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i 688SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i 689 690### Cryptographic XAR 691 692XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5 693 694### Advanced SIMD scalar copy 695 696DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5 697 698### Advanced SIMD copy 699 700DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5 701DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5 702INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5 703SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5 704UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5 705INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5 706 707### Advanced SIMD scalar three same 708 709FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd 710FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd 711FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd 712FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd 713FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd 714 715FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd 716FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd 717FMAXNM_s 0001 1110 ..1 ..... 0110 10 ..... ..... @rrr_hsd 718FMINNM_s 0001 1110 ..1 ..... 0111 10 ..... ..... @rrr_hsd 719 720FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h 721FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd 722 723FCMEQ_s 0101 1110 010 ..... 00100 1 ..... ..... @rrr_h 724FCMEQ_s 0101 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 725 726FCMGE_s 0111 1110 010 ..... 00100 1 ..... ..... @rrr_h 727FCMGE_s 0111 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd 728 729FCMGT_s 0111 1110 110 ..... 00100 1 ..... ..... @rrr_h 730FCMGT_s 0111 1110 1.1 ..... 11100 1 ..... ..... @rrr_sd 731 732FACGE_s 0111 1110 010 ..... 00101 1 ..... ..... @rrr_h 733FACGE_s 0111 1110 0.1 ..... 11101 1 ..... ..... @rrr_sd 734 735FACGT_s 0111 1110 110 ..... 00101 1 ..... ..... @rrr_h 736FACGT_s 0111 1110 1.1 ..... 11101 1 ..... ..... @rrr_sd 737 738FABD_s 0111 1110 110 ..... 00010 1 ..... ..... @rrr_h 739FABD_s 0111 1110 1.1 ..... 11010 1 ..... ..... @rrr_sd 740 741FRECPS_s 0101 1110 010 ..... 00111 1 ..... ..... @rrr_h 742FRECPS_s 0101 1110 0.1 ..... 11111 1 ..... ..... @rrr_sd 743 744FRSQRTS_s 0101 1110 110 ..... 00111 1 ..... ..... @rrr_h 745FRSQRTS_s 0101 1110 1.1 ..... 11111 1 ..... ..... @rrr_sd 746 747### Advanced SIMD scalar pairwise 748 749FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h 750FADDP_s 0111 1110 0.11 0000 1101 10 ..... ..... @rr_sd 751 752FMAXP_s 0101 1110 0011 0000 1111 10 ..... ..... @rr_h 753FMAXP_s 0111 1110 0.11 0000 1111 10 ..... ..... @rr_sd 754 755FMINP_s 0101 1110 1011 0000 1111 10 ..... ..... @rr_h 756FMINP_s 0111 1110 1.11 0000 1111 10 ..... ..... @rr_sd 757 758FMAXNMP_s 0101 1110 0011 0000 1100 10 ..... ..... @rr_h 759FMAXNMP_s 0111 1110 0.11 0000 1100 10 ..... ..... @rr_sd 760 761FMINNMP_s 0101 1110 1011 0000 1100 10 ..... ..... @rr_h 762FMINNMP_s 0111 1110 1.11 0000 1100 10 ..... ..... @rr_sd 763 764ADDP_s 0101 1110 1111 0001 1011 10 ..... ..... @rr_d 765 766### Advanced SIMD three same 767 768FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h 769FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 770 771FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h 772FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 773 774FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h 775FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 776 777FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h 778FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 779 780FMAX_v 0.00 1110 010 ..... 00110 1 ..... ..... @qrrr_h 781FMAX_v 0.00 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 782 783FMIN_v 0.00 1110 110 ..... 00110 1 ..... ..... @qrrr_h 784FMIN_v 0.00 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 785 786FMAXNM_v 0.00 1110 010 ..... 00000 1 ..... ..... @qrrr_h 787FMAXNM_v 0.00 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 788 789FMINNM_v 0.00 1110 110 ..... 00000 1 ..... ..... @qrrr_h 790FMINNM_v 0.00 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 791 792FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h 793FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd 794 795FMLA_v 0.00 1110 010 ..... 00001 1 ..... ..... @qrrr_h 796FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd 797 798FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h 799FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd 800 801FMLAL_v 0.00 1110 001 ..... 11101 1 ..... ..... @qrrr_h 802FMLSL_v 0.00 1110 101 ..... 11101 1 ..... ..... @qrrr_h 803FMLAL2_v 0.10 1110 001 ..... 11001 1 ..... ..... @qrrr_h 804FMLSL2_v 0.10 1110 101 ..... 11001 1 ..... ..... @qrrr_h 805 806FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h 807FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 808 809FCMGE_v 0.10 1110 010 ..... 00100 1 ..... ..... @qrrr_h 810FCMGE_v 0.10 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd 811 812FCMGT_v 0.10 1110 110 ..... 00100 1 ..... ..... @qrrr_h 813FCMGT_v 0.10 1110 1.1 ..... 11100 1 ..... ..... @qrrr_sd 814 815FACGE_v 0.10 1110 010 ..... 00101 1 ..... ..... @qrrr_h 816FACGE_v 0.10 1110 0.1 ..... 11101 1 ..... ..... @qrrr_sd 817 818FACGT_v 0.10 1110 110 ..... 00101 1 ..... ..... @qrrr_h 819FACGT_v 0.10 1110 1.1 ..... 11101 1 ..... ..... @qrrr_sd 820 821FABD_v 0.10 1110 110 ..... 00010 1 ..... ..... @qrrr_h 822FABD_v 0.10 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd 823 824FRECPS_v 0.00 1110 010 ..... 00111 1 ..... ..... @qrrr_h 825FRECPS_v 0.00 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd 826 827FRSQRTS_v 0.00 1110 110 ..... 00111 1 ..... ..... @qrrr_h 828FRSQRTS_v 0.00 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd 829 830FADDP_v 0.10 1110 010 ..... 00010 1 ..... ..... @qrrr_h 831FADDP_v 0.10 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd 832 833FMAXP_v 0.10 1110 010 ..... 00110 1 ..... ..... @qrrr_h 834FMAXP_v 0.10 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd 835 836FMINP_v 0.10 1110 110 ..... 00110 1 ..... ..... @qrrr_h 837FMINP_v 0.10 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd 838 839FMAXNMP_v 0.10 1110 010 ..... 00000 1 ..... ..... @qrrr_h 840FMAXNMP_v 0.10 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd 841 842FMINNMP_v 0.10 1110 110 ..... 00000 1 ..... ..... @qrrr_h 843FMINNMP_v 0.10 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd 844 845ADDP_v 0.00 1110 ..1 ..... 10111 1 ..... ..... @qrrr_e 846SMAXP_v 0.00 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 847SMINP_v 0.00 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 848UMAXP_v 0.10 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e 849UMINP_v 0.10 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e 850 851AND_v 0.00 1110 001 ..... 00011 1 ..... ..... @qrrr_b 852BIC_v 0.00 1110 011 ..... 00011 1 ..... ..... @qrrr_b 853ORR_v 0.00 1110 101 ..... 00011 1 ..... ..... @qrrr_b 854ORN_v 0.00 1110 111 ..... 00011 1 ..... ..... @qrrr_b 855EOR_v 0.10 1110 001 ..... 00011 1 ..... ..... @qrrr_b 856BSL_v 0.10 1110 011 ..... 00011 1 ..... ..... @qrrr_b 857BIT_v 0.10 1110 101 ..... 00011 1 ..... ..... @qrrr_b 858BIF_v 0.10 1110 111 ..... 00011 1 ..... ..... @qrrr_b 859 860### Advanced SIMD scalar x indexed element 861 862FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 863FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 864FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 865 866FMLA_si 0101 1111 00 .. .... 0001 . 0 ..... ..... @rrx_h 867FMLA_si 0101 1111 10 .. .... 0001 . 0 ..... ..... @rrx_s 868FMLA_si 0101 1111 11 0. .... 0001 . 0 ..... ..... @rrx_d 869 870FMLS_si 0101 1111 00 .. .... 0101 . 0 ..... ..... @rrx_h 871FMLS_si 0101 1111 10 .. .... 0101 . 0 ..... ..... @rrx_s 872FMLS_si 0101 1111 11 0. .... 0101 . 0 ..... ..... @rrx_d 873 874FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h 875FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s 876FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d 877 878### Advanced SIMD vector x indexed element 879 880FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 881FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 882FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 883 884FMLA_vi 0.00 1111 00 .. .... 0001 . 0 ..... ..... @qrrx_h 885FMLA_vi 0.00 1111 10 . ..... 0001 . 0 ..... ..... @qrrx_s 886FMLA_vi 0.00 1111 11 0 ..... 0001 . 0 ..... ..... @qrrx_d 887 888FMLS_vi 0.00 1111 00 .. .... 0101 . 0 ..... ..... @qrrx_h 889FMLS_vi 0.00 1111 10 . ..... 0101 . 0 ..... ..... @qrrx_s 890FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d 891 892FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h 893FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s 894FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d 895 896FMLAL_vi 0.00 1111 10 .. .... 0000 . 0 ..... ..... @qrrx_h 897FMLSL_vi 0.00 1111 10 .. .... 0100 . 0 ..... ..... @qrrx_h 898FMLAL2_vi 0.10 1111 10 .. .... 1000 . 0 ..... ..... @qrrx_h 899FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h 900