1# AArch64 A64 allowed instruction decoding 2# 3# Copyright (c) 2023 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22&r rn 23&ri rd imm 24&rri_sf rd rn imm sf 25&i imm 26 27 28### Data Processing - Immediate 29 30# PC-rel addressing 31 32%imm_pcrel 5:s19 29:2 33@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel 34 35ADR 0 .. 10000 ................... ..... @pcrel 36ADRP 1 .. 10000 ................... ..... @pcrel 37 38# Add/subtract (immediate) 39 40%imm12_sh12 10:12 !function=shl_12 41@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 42@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 43 44ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm 45ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 46ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm 47ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 48 49SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm 50SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 51SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm 52SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 53 54# Add/subtract (immediate with tags) 55 56&rri_tag rd rn uimm6 uimm4 57@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag 58 59ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 60SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag 61 62# Logical (immediate) 63 64&rri_log rd rn sf dbm 65@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 66@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 67 68AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 69AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 70ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 71ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 72EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 73EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 74ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 75ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 76 77# Move wide (immediate) 78 79&movw rd sf imm hw 80@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 81@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 82 83MOVN . 00 100101 .. ................ ..... @movw_64 84MOVN . 00 100101 .. ................ ..... @movw_32 85MOVZ . 10 100101 .. ................ ..... @movw_64 86MOVZ . 10 100101 .. ................ ..... @movw_32 87MOVK . 11 100101 .. ................ ..... @movw_64 88MOVK . 11 100101 .. ................ ..... @movw_32 89 90# Bitfield 91 92&bitfield rd rn sf immr imms 93@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 94@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 95 96SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 97SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 98BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 99BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 100UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 101UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 102 103# Extract 104 105&extract rd rn rm imm sf 106 107EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1 108EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 109 110# Branches 111 112%imm26 0:s26 !function=times_4 113@branch . ..... .......................... &i imm=%imm26 114 115B 0 00101 .......................... @branch 116BL 1 00101 .......................... @branch 117 118%imm19 5:s19 !function=times_4 119&cbz rt imm sf nz 120 121CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19 122 123%imm14 5:s14 !function=times_4 124%imm31_19 31:1 19:5 125&tbz rt imm nz bitpos 126 127TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 128 129B_cond 0101010 0 ................... 0 cond:4 imm=%imm19 130 131BR 1101011 0000 11111 000000 rn:5 00000 &r 132BLR 1101011 0001 11111 000000 rn:5 00000 &r 133RET 1101011 0010 11111 000000 rn:5 00000 &r 134 135&braz rn m 136BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ 137BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ 138 139&reta m 140RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB 141 142&bra rn rm m 143BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB 144BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB 145 146ERET 1101011 0100 11111 000000 11111 00000 147ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB 148 149# We don't need to decode DRPS because it always UNDEFs except when 150# the processor is in halting debug state (which we don't implement). 151# The pattern is listed here as documentation. 152# DRPS 1101011 0101 11111 000000 11111 00000 153 154# Hint instruction group 155{ 156 [ 157 YIELD 1101 0101 0000 0011 0010 0000 001 11111 158 WFE 1101 0101 0000 0011 0010 0000 010 11111 159 WFI 1101 0101 0000 0011 0010 0000 011 11111 160 # We implement WFE to never block, so our SEV/SEVL are NOPs 161 # SEV 1101 0101 0000 0011 0010 0000 100 11111 162 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 163 # Our DGL is a NOP because we don't merge memory accesses anyway. 164 # DGL 1101 0101 0000 0011 0010 0000 110 11111 165 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 166 PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 167 PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 168 AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 169 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 170 ESB 1101 0101 0000 0011 0010 0010 000 11111 171 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 172 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 173 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 174 PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 175 AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 176 AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 177 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 178 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 179 ] 180 # The canonical NOP has CRm == op2 == 0, but all of the space 181 # that isn't specifically allocated to an instruction must NOP 182 NOP 1101 0101 0000 0011 0010 ---- --- 11111 183} 184 185# Barriers 186 187CLREX 1101 0101 0000 0011 0011 ---- 010 11111 188DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 189ISB 1101 0101 0000 0011 0011 ---- 110 11111 190SB 1101 0101 0000 0011 0011 0000 111 11111 191 192# PSTATE 193 194CFINV 1101 0101 0000 0 000 0100 0000 000 11111 195XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 196AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 197 198# These are architecturally all "MSR (immediate)"; we decode the destination 199# register too because there is no commonality in our implementation. 200@msr_i .... .... .... . ... .... imm:4 ... ..... 201MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i 202MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i 203MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i 204MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i 205MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i 206MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i 207MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i 208MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i 209MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 210 211# MRS, MSR (register), SYS, SYSL. These are all essentially the 212# same instruction as far as QEMU is concerned. 213# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have 214# to hand-decode it. 215SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 216SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 217SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 218 219# Exception generation 220 221@i16 .... .... ... imm:16 ... .. &i 222SVC 1101 0100 000 ................ 000 01 @i16 223HVC 1101 0100 000 ................ 000 10 @i16 224SMC 1101 0100 000 ................ 000 11 @i16 225BRK 1101 0100 001 ................ 000 00 @i16 226HLT 1101 0100 010 ................ 000 00 @i16 227# These insns always UNDEF unless in halting debug state, which 228# we don't implement. So we don't need to decode them. The patterns 229# are listed here as documentation. 230# DCPS1 1101 0100 101 ................ 000 01 @i16 231# DCPS2 1101 0100 101 ................ 000 10 @i16 232# DCPS3 1101 0100 101 ................ 000 11 @i16 233